/openbmc/linux/Documentation/devicetree/bindings/mmc/ |
H A D | samsung,exynos-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/mmc/samsung,exynos-dw-mshc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 12 - Jaehoon Chung <jh80.chung@samsung.com> 13 - Krzysztof Kozlowski <krzk@kernel.org> 18 - samsung,exynos4210-dw-mshc 19 - samsung,exynos4412-dw-mshc 20 - samsung,exynos5250-dw-mshc 21 - samsung,exynos5420-dw-mshc [all …]
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H A D | synopsys-dw-mshc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Ulf Hansson <ulf.hansson@linaro.org> 16 - altr,socfpga-dw-mshc 17 - img,pistachio-dw-mshc 18 - snps,dw-mshc 33 clock-names: 35 - const: biu [all …]
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/openbmc/linux/drivers/clk/hisilicon/ |
H A D | clk-hisi-phase.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Simple HiSilicon phase clock implementation. 23 u8 shift; member 30 static int hisi_phase_regval_to_degrees(struct clk_hisi_phase *phase, in hisi_phase_regval_to_degrees() argument 35 for (i = 0; i < phase->phase_num; i++) in hisi_phase_regval_to_degrees() 36 if (phase->phase_regvals[i] == regval) in hisi_phase_regval_to_degrees() 37 return phase->phase_degrees[i]; in hisi_phase_regval_to_degrees() 39 return -EINVAL; in hisi_phase_regval_to_degrees() 44 struct clk_hisi_phase *phase = to_clk_hisi_phase(hw); in hisi_clk_get_phase() local 47 regval = readl(phase->reg); in hisi_clk_get_phase() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/spi/ |
H A D | samsung,spi-peripheral-props.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/samsung,spi-peripheral-props.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Peripheral-specific properties for Samsung S3C/S5P/Exynos SoC SPI controller 10 - Krzysztof Kozlowski <krzk@kernel.org> 13 See spi-peripheral-props.yaml for more info. 16 controller-data: 21 samsung,spi-feedback-delay: 23 The sampling phase shift to be applied on the miso line (to account [all …]
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/openbmc/linux/drivers/clk/sunxi-ng/ |
H A D | ccu_phase.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 #include <linux/clk-provider.h> 15 struct ccu_phase *phase = hw_to_ccu_phase(hw); in ccu_phase_get_phase() local 22 reg = readl(phase->common.base + phase->common.reg); in ccu_phase_get_phase() 23 delay = (reg >> phase->shift); in ccu_phase_get_phase() 24 delay &= (1 << phase->width) - 1; in ccu_phase_get_phase() 32 return -EINVAL; in ccu_phase_get_phase() 37 return -EINVAL; in ccu_phase_get_phase() 42 return -EINVAL; in ccu_phase_get_phase() [all …]
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/openbmc/linux/drivers/clk/rockchip/ |
H A D | clk-mmc-phase.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 9 #include <linux/clk-provider.h> 18 int shift; member 41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to 54 /* Constant signal, no measurable phase shift */ in rockchip_mmc_get_phase() 58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase() 86 * MMC host to the card, which expects the phase clock inherits in rockchip_mmc_set_phase() 98 return -EINVAL; in rockchip_mmc_set_phase() 106 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase() 125 * don't overflow 32-bit / 64-bit numbers. in rockchip_mmc_set_phase() [all …]
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H A D | clk-inverter.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 7 #include <linux/clk-provider.h> 16 int shift; member 30 val = readl(inv_clock->reg) >> inv_clock->shift; in rockchip_inv_get_phase() 43 pr_err("%s: unsupported phase %d for %s\n", in rockchip_inv_set_phase() 45 return -EINVAL; in rockchip_inv_set_phase() 48 if (inv_clock->flags & ROCKCHIP_INVERTER_HIWORD_MASK) { in rockchip_inv_set_phase() 49 writel(HIWORD_UPDATE(val, INVERTER_MASK, inv_clock->shift), in rockchip_inv_set_phase() 50 inv_clock->reg); in rockchip_inv_set_phase() 55 spin_lock_irqsave(inv_clock->lock, flags); in rockchip_inv_set_phase() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/leds/backlight/ |
H A D | sky81452-backlight.txt | 1 SKY81452-backlight bindings 4 - compatible : Must be "skyworks,sky81452-backlight" 7 - name : Name of backlight device. Default is 'lcd-backlight'. 8 - gpios : GPIO to use to EN pin. 10 - led-sources : List of enabled channels from 0 to 5. 12 - skyworks,ignore-pwm : Ignore both PWM input 13 - skyworks,dpwm-mode : Enable DPWM dimming mode, otherwise Analog dimming. 14 - skyworks,phase-shift : Enable phase shift mode 15 - skyworks,short-detection-threshold-volt 17 - skyworks,current-limit-mA [all …]
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/openbmc/linux/drivers/staging/iio/Documentation/ |
H A D | sysfs-bus-iio-dds | 4 Contact: linux-iio@vger.kernel.org 8 which allows for pin controlled FSK Frequency Shift Keying 15 Contact: linux-iio@vger.kernel.org 24 Contact: linux-iio@vger.kernel.org 34 Contact: linux-iio@vger.kernel.org 36 Stores phase into Y. 38 allows for pin controlled PSK Phase Shift Keying 40 control the desired phase Y which is added to the phase 45 Contact: linux-iio@vger.kernel.org 48 the desired value in rad. If shared across all phase registers [all …]
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/openbmc/qemu/hw/m68k/ |
H A D | next-cube.c | 17 #include "hw/m68k/next-cube.h" 25 #include "hw/qdev-properties.h" 27 #include "qemu/error-report.h" 40 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 65 int8_t phase; member 86 #define TYPE_NEXT_PC "next-pc" 135 if (s->scr2 & 0x1) { in next_scr2_led_update() 137 s->led++; in next_scr2_led_update() 138 if (s->led == 10) { in next_scr2_led_update() 140 s->led = 0; in next_scr2_led_update() [all …]
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/openbmc/linux/drivers/mmc/host/ |
H A D | sdhci-of-arasan.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu> 9 * Based on sdhci-of-esdhc.c 18 #include <linux/clk-provider.h> 26 #include <linux/firmware/xlnx-zynqmp.h> 29 #include "sdhci-cqhci.h" 30 #include "sdhci-pltfm.h" 92 * On some SoCs the syscon area has a feature where the upper 16-bits of 93 * each 32-bit register act as a write mask for the lower 16-bits. This allows 97 #define HIWORD_UPDATE(val, mask, shift) \ argument [all …]
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/openbmc/qemu/hw/audio/ |
H A D | asc.c | 7 * Copyright (c) 2012-2018 Laurent Vivier <laurent@vivier.eu> 8 * Copyright (c) 2022 Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> 10 * SPDX-License-Identifier: GPL-2.0-or-later 19 #include "hw/qdev-properties.h" 44 * bit 1="non-ROM companding", 52 * bits 0-3 wavetables 0-3 start 54 * bits 2-4 = 3 bit internal ASC volume, 55 * bits 5-7 = volume control sent to Sony sound chip 63 * bits 6-7 = digital test, 64 * bits 4-5 = analog test [all …]
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H A D | fmopl.h | 10 /* ---------- OPL one of slot ---------- */ 14 uint8_t KSR; /* key scale rate :(shift down bit) */ 19 uint8_t ksl; /* keyscale level :(shift down bits) */ 26 uint8_t evm; /* envelope phase */ 40 /* ---------- OPL one of channel ---------- */ 44 uint8_t FB; /* feed back :(shift down bit) */ 48 /* phase generator state */ 77 uint32_t FN_TABLE[1024]; /* fnumber -> increment counter */ 92 /* ---------- Generic interface section ---------- */
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/openbmc/linux/Documentation/ABI/testing/ |
H A D | sysfs-bus-iio-frequency-admv1013 | 1 What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-1_i_calibphase 3 Contact: linux-iio@vger.kernel.org 5 Read/write unscaled value for the Local Oscillatior path quadrature I phase shift. 7 What: /sys/bus/iio/devices/iio:deviceX/in_altvoltage0-1_q_calibphase 9 Contact: linux-iio@vger.kernel.org 11 Read/write unscaled value for the Local Oscillatior path quadrature Q phase shift. 15 Contact: linux-iio@vger.kernel.org 22 Contact: linux-iio@vger.kernel.org 28 Contact: linux-iio@vger.kernel.org 35 Contact: linux-iio@vger.kernel.org
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/openbmc/linux/include/linux/ |
H A D | timex.h | 28 * Added defines for hybrid phase/frequency-lock loop. 32 * defines for PPS phase-lock loop. 46 * 1995-08-13 Torsten Duwe 47 * kernel PLL updated to 1994-12-13 specs (rfc-1589) 48 * 1997-08-30 Ulrich Windl 50 * 2004-08-12 Christoph Lameter 59 #define ADJ_OFFSET_SINGLESHOT 0x0001 /* old-fashioned adjtime */ 60 #define ADJ_OFFSET_READONLY 0x2000 /* read-only adjtime */ 73 * when an interrupt takes places versus a high speed, fine-grained 102 * https://lists.ntp.org/pipermail/hackers/2008-January/003487.html [all …]
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/openbmc/linux/drivers/gpu/drm/i915/selftests/ |
H A D | i915_syncmap.c | 41 for (d = 0; d < depth - 1; d++) { in __sync_print() 42 if (last & BIT(depth - d - 1)) in __sync_print() 47 *sz -= len; in __sync_print() 49 len = scnprintf(buf, *sz, "%x-> ", idx); in __sync_print() 51 *sz -= len; in __sync_print() 55 len = scnprintf(buf, *sz, "0x%016llx", p->prefix << p->height << SHIFT); in __sync_print() 57 *sz -= len; in __sync_print() 58 X = (p->height + SHIFT) / 4; in __sync_print() 59 scnprintf(buf - X, *sz + X, "%*s", X, "XXXXXXXXXXXXXXXXX"); in __sync_print() 61 if (!p->height) { in __sync_print() [all …]
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/openbmc/linux/arch/parisc/include/asm/ |
H A D | hash.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 6 * HP-PA only implements integer multiply in the FPU. However, for 7 * integer multiplies by constant, it has a number of shift-and-add 8 * (but no shift-and-subtract, sigh!) instructions that a compiler 20 * PA7100 pairing rules. This is an in-order 2-way superscalar processor. 21 * Only one instruction in a pair may be a shift (by more than 3 bits), 22 * but other than that, simple ALU ops (including shift-and-add by up 25 * PA8xxx processors also dual-issue ALU instructions, although with 28 * This 6-step sequence was found by Yevgen Voronenko's implementation 36 * Phase 1: Compute a = (x << 19) + x, in __hash_32() [all …]
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/openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/ |
H A D | dpu_hw_util.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved. 15 #define REG_MASK(n) ((BIT(n)) - 1) 35 * struct dpu_hw_blk - opaque hardware block object 46 * @ clip: clip shift 52 * @ prec_shift: precision shift 53 * @ adjust_a: A-coefficients for mapping curve 54 * @ adjust_b: B-coefficients for mapping curve 55 * @ adjust_c: C-coefficients for mapping curve [all …]
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | altr_socfpga.txt | 5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 8 - compatible : shall be one of the following: 9 "altr,socfpga-pll-clock" - for a PLL clock 10 "altr,socfpga-perip-clock" - The peripheral clock divided from the 12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and 15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock. 16 - clocks : shall be the input parent clock phandle for the clock. This is 18 - #clock-cells : from common clock binding, shall be set to 0. 21 - fixed-divider : If clocks have a fixed divider value, use this property. 22 - clk-gate : For "socfpga-gate-clk", clk-gate contains the gating register [all …]
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/openbmc/linux/Documentation/devicetree/bindings/clock/ti/ |
H A D | apll.txt | 3 Binding status: Unstable - ABI compatibility may be broken in the future 6 register-mapped APLL with usually two selectable input clocks 7 (reference clock and bypass clock), with analog phase locked 13 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 17 - compatible : shall be "ti,dra7-apll-clock" or "ti,omap2-apll-clock" 18 - #clock-cells : from common clock binding; shall be set to 0. 19 - clocks : link phandles of parent clocks (clk-ref and clk-bypass) 20 - reg : address and length of the register set for controlling the APLL. 22 "control" - contains the control register offset 23 "idlest" - contains the idlest register offset [all …]
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/openbmc/linux/kernel/time/ |
H A D | ntp.c | 1 // SPDX-License-Identifier: GPL-2.0 49 * phase-lock loop variables 82 /* constant (boot-param configurable) NTP tick adjustment (upscaled) */ 91 * The following variables are used when a pulse-per-second (PPS) signal 96 #define PPS_POPCORN 4 /* popcorn spike threshold (shift) */ 97 #define PPS_INTMIN 2 /* min freq interval (s) (shift) */ 98 #define PPS_INTMAX 8 /* max freq interval (s) (shift) */ 105 static long pps_tf[3]; /* phase median filter */ 108 static int pps_shift; /* current interval duration (s) (shift) */ 122 /* PPS kernel consumer compensates the whole phase error immediately. [all …]
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/openbmc/linux/arch/x86/crypto/ |
H A D | aesni-intel_avx-x86_64.S | 48 ## Vinodh Gopal et. al. Optimized Galois-Counter-Mode Implementation 51 ## Erdinc Ozturk et. al. Enabling High-Performance Galois-Counter-Mode 61 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 63 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 66 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 68 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 82 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 84 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ 85 ## | 32-bit Sequence Number (A0) | 86 ## +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ [all …]
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/openbmc/linux/drivers/regulator/ |
H A D | pf8x00-regulator.c | 1 // SPDX-License-Identifier: GPL-2.0+ 97 #define PF8X00_SW_BASE(i) (8 * (i - PF8X00_BUCK1) + PF8X00_SW1_CONFIG1) 106 #define PF8X00_LDO_BASE(i) (6 * (i - PF8X00_LDO1) + PF8X00_LDO1_CONFIG1) 202 regmap_update_bits(chip->regmap, reg, in swxilim_select() 211 struct pf8x00_chip *chip = config->driver_data; in handle_ilim_property() 215 if ((desc->id >= PF8X00_BUCK1) && (desc->id <= PF8X00_BUCK7)) { in handle_ilim_property() 216 ret = of_property_read_u32(np, "nxp,ilim-ma", &val); in handle_ilim_property() 218 dev_dbg(chip->dev, "unspecified ilim for BUCK%d, use value stored in OTP\n", in handle_ilim_property() 219 desc->id - PF8X00_LDO4); in handle_ilim_property() 223 dev_warn(chip->dev, "nxp,ilim-ma is deprecated, please use regulator-max-microamp\n"); in handle_ilim_property() [all …]
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/openbmc/u-boot/drivers/ddr/marvell/axp/ |
H A D | ddr3_pbs.c | 1 // SPDX-License-Identifier: GPL-2.0 70 * Desc: Execute the PBS TX phase. 92 /* bit array for unlock pups - used to repeat on the RX operation */ in ddr3_pbs_tx() 102 DEBUG_PBS_S("DDR3 - PBS TX - Starting PBS TX procedure\n"); in ddr3_pbs_tx() 104 pups = dram_info->num_of_total_pups; in ddr3_pbs_tx() 105 max_pup = dram_info->num_of_total_pups; in ddr3_pbs_tx() 110 /* [0] = 1 - Enable SW override */ in ddr3_pbs_tx() 111 /* 0x15B8 - Training SW 2 Register */ in ddr3_pbs_tx() 113 DEBUG_PBS_S("DDR3 - PBS RX - SW Override Enabled\n"); in ddr3_pbs_tx() 116 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_pbs_tx() [all …]
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/openbmc/u-boot/drivers/ddr/altera/ |
H A D | sequencer.c | 1 // SPDX-License-Identifier: BSD-3-Clause 3 * Copyright Altera Corporation (C) 2012-2015 44 * However, to support simulation-time selection of fast simulation mode, where 47 * check, which is based on the rtl-supplied value, or we dynamically compute 48 * the value to use based on the dynamically-chosen calibration mode 64 * non-skip and skip values 66 * The mask is set to include all bits when not-skipping, but is 70 static u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */ 85 if (gbl->error_stage == CAL_STAGE_NIL) { in set_failing_group_stage() 86 gbl->error_substage = substage; in set_failing_group_stage() [all …]
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