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/openbmc/qemu/hw/audio/
H A Dasc.c7 * Copyright (c) 2012-2018 Laurent Vivier <laurent@vivier.eu>
8 * Copyright (c) 2022 Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
10 * SPDX-License-Identifier: GPL-2.0-or-later
20 #include "hw/qdev-properties.h"
45 * bit 1="non-ROM companding",
53 * bits 0-3 wavetables 0-3 start
55 * bits 2-4 = 3 bit internal ASC volume,
56 * bits 5-7 = volume control sent to Sony sound chip
64 * bits 6-7 = digital test,
65 * bits 4-5 = analog test
[all …]
H A Dfmopl.h10 /* ---------- OPL one of slot ---------- */
14 uint8_t KSR; /* key scale rate :(shift down bit) */
19 uint8_t ksl; /* keyscale level :(shift down bits) */
26 uint8_t evm; /* envelope phase */
40 /* ---------- OPL one of channel ---------- */
44 uint8_t FB; /* feed back :(shift down bit) */
48 /* phase generator state */
77 uint32_t FN_TABLE[1024]; /* fnumber -> increment counter */
92 /* ---------- Generic interface section ---------- */
/openbmc/qemu/hw/m68k/
H A Dnext-cube.c5 * Copyright (c) 2024 Mark Cave-Ayland
15 #include "exec/cpu-interrupt.h"
19 #include "hw/m68k/next-cube.h"
28 #include "hw/qdev-properties.h"
30 #include "qemu/error-report.h"
48 #define TYPE_NEXT_RTC "next-rtc"
54 int8_t phase; member
66 #define TYPE_NEXT_SCSI "next-scsi"
82 #define TYPE_NEXT_PC "next-pc"
133 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube")
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c1 // SPDX-License-Identifier: GPL-2.0
70 * Desc: Execute the PBS TX phase.
92 /* bit array for unlock pups - used to repeat on the RX operation */ in ddr3_pbs_tx()
102 DEBUG_PBS_S("DDR3 - PBS TX - Starting PBS TX procedure\n"); in ddr3_pbs_tx()
104 pups = dram_info->num_of_total_pups; in ddr3_pbs_tx()
105 max_pup = dram_info->num_of_total_pups; in ddr3_pbs_tx()
110 /* [0] = 1 - Enable SW override */ in ddr3_pbs_tx()
111 /* 0x15B8 - Training SW 2 Register */ in ddr3_pbs_tx()
113 DEBUG_PBS_S("DDR3 - PBS RX - SW Override Enabled\n"); in ddr3_pbs_tx()
116 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_pbs_tx()
[all …]
H A Dddr3_write_leveling.c1 // SPDX-License-Identifier: GPL-2.0
58 * Desc: Execute Write leveling phase by HW
59 * Args: freq - current sequence frequency
60 * dram_info - main struct
66 u32 reg, phase, delay, cs, pup; in ddr3_write_leveling_hw() local
70 /* Debug message - Start Read leveling procedure */ in ddr3_write_leveling_hw()
71 DEBUG_WL_S("DDR3 - Write Leveling - Starting HW WL procedure\n"); in ddr3_write_leveling_hw()
86 reg |= (dram_info->cs_ena << (REG_DRAM_TRAINING_CS_OFFS)); in ddr3_write_leveling_hw()
87 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_write_leveling_hw()
103 * Read results to arrays - Results are required for WL in ddr3_write_leveling_hw()
[all …]
/openbmc/u-boot/drivers/ddr/altera/
H A Dsequencer.c1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright Altera Corporation (C) 2012-2015
44 * However, to support simulation-time selection of fast simulation mode, where
47 * check, which is based on the rtl-supplied value, or we dynamically compute
48 * the value to use based on the dynamically-chosen calibration mode
64 * non-skip and skip values
66 * The mask is set to include all bits when not-skipping, but is
70 static u16 skip_delay_mask; /* mask off bits when skipping/not-skipping */
85 if (gbl->error_stage == CAL_STAGE_NIL) { in set_failing_group_stage()
86 gbl->error_substage = substage; in set_failing_group_stage()
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/openbmc/u-boot/drivers/nvme/
H A Dnvme.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dm/device-internal.h>
57 timeout = NVME_CAP_TIMEOUT(dev->cap) * 500; in nvme_wait_ready()
61 if ((readl(&dev->bar->csts) & NVME_CSTS_RDY) == bit) in nvme_wait_ready()
65 return -ETIME; in nvme_wait_ready()
71 u32 page_size = dev->page_size; in nvme_setup_prps()
72 int offset = dma_addr & (page_size - 1); in nvme_setup_prps()
76 length -= (page_size - offset); in nvme_setup_prps()
84 dma_addr += (page_size - offset); in nvme_setup_prps()
93 if (nprps > dev->prp_entry_num) { in nvme_setup_prps()
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/openbmc/u-boot/drivers/spi/
H A Dzynq_spi.c1 // SPDX-License-Identifier: GPL-2.0+
22 #define ZYNQ_SPI_CR_CPHA_MASK BIT(2) /* Clock phase */
31 #define ZYNQ_SPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
32 #define ZYNQ_SPI_CR_SS_SHIFT 10 /* Slave select shift */
74 struct zynq_spi_platdata *plat = bus->platdata; in zynq_spi_ofdata_to_platdata()
75 const void *blob = gd->fdt_blob; in zynq_spi_ofdata_to_platdata()
78 plat->regs = (struct zynq_spi_regs *)devfdt_get_addr(bus); in zynq_spi_ofdata_to_platdata()
81 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", in zynq_spi_ofdata_to_platdata()
83 plat->deactivate_delay_us = fdtdec_get_int(blob, node, in zynq_spi_ofdata_to_platdata()
84 "spi-deactivate-delay", 0); in zynq_spi_ofdata_to_platdata()
[all …]
H A Dzynq_qspi.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
25 #define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
35 #define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
36 #define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
37 #define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
38 #define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
44 #define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
45 #define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
101 struct zynq_qspi_platdata *plat = bus->platdata; in zynq_qspi_ofdata_to_platdata()
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/openbmc/u-boot/lib/efi_selftest/
H A Defi_selftest_textinputex.c1 // SPDX-License-Identifier: GPL-2.0+
28 * efi_key_notify_function() - key notification function
66 boottime = systable->boottime; in setup()
68 ret = boottime->locate_protocol(&text_input_ex_protocol_guid, NULL, in setup()
77 ret = con_in_ex->register_key_notify(con_in_ex, &key_data, in setup()
102 ret = con_in_ex->unregister_key_notify in teardown()
129 ret = con_in_ex->reset(con_in_ex, true); in execute()
134 ret = con_in_ex->read_key_stroke_ex(con_in_ex, &input_key); in execute()
145 ret = boottime->wait_for_event(1, &con_in_ex->wait_for_key_ex, in execute()
151 ret = con_in_ex->read_key_stroke_ex(con_in_ex, &input_key); in execute()
[all …]
/openbmc/u-boot/include/
H A Dsym53c8xx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
14 #define SCNTL0 0x00 /* full arb., ena parity, par->ATN */
30 /* bits 0-2, 7 rsvd for C1010 */
37 /* bits 6-7 rsvd for C1010 */
39 #define SDID 0x06 /* ### Destination-ID */
41 #define GPREG 0x07 /* ??? IO-Pins */
43 #define SFBR 0x08 /* ### First byte in phase */
46 #define CREQ 0x80 /* r/w: SCSI-REQ */
47 #define CACK 0x40 /* r/w: SCSI-ACK */
48 #define CBSY 0x20 /* r/w: SCSI-BSY */
[all …]
H A Dfsl_ifc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
36 * CSPR - Chip Select Property Register
73 (LOG2(n) - IFC_AMASK_SHIFT))
114 #define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT)
127 * Chip Select Option Register - NOR Flash Mode
129 /* Enable Address shift Mode */
135 /* Address Data Multiplexing Shift */
154 * Chip Select Option Register - GPCM Mode
156 /* GPCM Mode - Normal */
[all …]
/openbmc/u-boot/drivers/ddr/marvell/a38x/
H A Dddr3_training_leveling.c1 // SPDX-License-Identifier: GPL-2.0
55 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) in ddr3_tip_dynamic_read_leveling()
59 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
60 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
77 * Phase 1: Load pattern (using ODPG) in ddr3_tip_dynamic_read_leveling()
81 * assuming non multi-CS configuration in ddr3_tip_dynamic_read_leveling()
103 * Phase 2: ODPG to Read Leveling mode in ddr3_tip_dynamic_read_leveling()
118 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) { in ddr3_tip_dynamic_read_leveling()
119 VALIDATE_IF_ACTIVE(tm->if_act_mask, if_id); in ddr3_tip_dynamic_read_leveling()
121 tm->interface_params[if_id].speed_bin_index; in ddr3_tip_dynamic_read_leveling()
[all …]
/openbmc/qemu/hw/scsi/
H A Dlsi53c895a.c13 * as well-behaved operating systems will not try to use them.
304 uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
327 static const char *scsi_phase_name(int phase) in scsi_phase_name() argument
329 return scsi_phases[phase & PHASE_MASK]; in scsi_phase_name()
334 return (s->sien0 & LSI_SIST0_RSL) && (s->scid & LSI_SCID_RRE); in lsi_irq_on_rsl()
341 QTAILQ_FOREACH(p, &s->queue, next) { in get_pending_req()
342 if (p->pending) { in get_pending_req()
352 s->carry = 0; in lsi_soft_reset()
354 s->msg_action = LSI_MSG_ACTION_COMMAND; in lsi_soft_reset()
355 s->msg_len = 0; in lsi_soft_reset()
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/openbmc/u-boot/arch/arm/mach-exynos/
H A Ddmc_init_exynos4.c23 * MA 02111-1307 USA
55 &dmc->phycontrol1); in phy_control_reset()
57 &dmc->phycontrol1); in phy_control_reset()
60 &dmc->phycontrol0); in phy_control_reset()
62 &dmc->phycontrol0); in phy_control_reset()
76 &dmc->directcmd); in dmc_config_mrs()
85 * Phase Delay for DQS Cleaning: 180' Shift in dmc_init()
87 writel(mem.control1, &dmc->phycontrol1); in dmc_init()
94 writel(mem.zqcontrol, &dmc->phyzqcontrol); in dmc_init()
105 writel(mem.control1, &dmc->phycontrol1); in dmc_init()
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Drk3036.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3036-cru.h>
13 interrupt-parent = <&gic>;
32 arm-pmu {
33 compatible = "arm,cortex-a7-pmu";
36 interrupt-affinity = <&cpu0>, <&cpu1>;
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H A Drk3128.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3128-cru.h>
16 interrupt-parent = <&gic>;
17 #address-cells = <1>;
18 #size-cells = <1>;
42 arm-pmu {
[all …]
H A Drk322x.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/pinctrl/rockchip.h>
10 #include <dt-bindings/clock/rk3228-cru.h>
11 #include <dt-bindings/thermal/thermal.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
17 interrupt-parent = <&gic>;
[all …]
/openbmc/u-boot/arch/mips/mach-ath79/ar933x/
H A Dlowlevel_init.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
4 * Based on Atheros LSDK/QSDK and u-boot_mod project
26 (((0x3 & (cpudiv - 1)) << 5) | \
27 ((0x3 & (ddrdiv - 1)) << 10) | \
28 ((0x3 & (ahbdiv - 1)) << 15) )
33 * Bit30 is set (CPU_PLLPWD = 1 -> power down control for CPU PLL)
56 * In PLL_CLK_CONTROL_VAL bit 2 is set (BYPASS = 1 -> bypass PLL)
91 addi t3, t3, -1
99 addi t2, t2, -1
[all …]
/openbmc/u-boot/arch/arm/mach-sunxi/
H A DKconfig4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
87 ---help---
100 ---help---
102 as the original A10 (mach-sun4i).
106 ---help---
113 ---help---
116 not have official open-source DRAM initialization code, but can
122 ---help---
124 have only 16-bit memory buswidth.
128 ---help---
[all …]
/openbmc/qemu/include/standard-headers/linux/
H A Dinput.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
3 * Copyright (c) 1999-2002 Vojtech Pavlik
15 #include "standard-headers/linux/types.h"
17 #include "standard-headers/linux/input-event-codes.h"
53 * IOCTLs (0x00 - 0x7f)
64 * struct input_absinfo - used by EVIOCGABS/EVIOCSABS ioctls
100 * struct input_keymap_entry - used by EVIOCGKEYCODE/EVIOCSKEYCODE ioctls
101 * @scancode: scancode represented in machine-endian form.
145 * EVIOCGMTSLOTS(len) - get MT slot values
166 * If the request code is not an ABS_MT value, -EINVAL is returned.
[all …]
/openbmc/u-boot/drivers/pci/
H A Dpci-uclass.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <dm/device-internal.h>
28 if (ret == -ENODEV) { in pci_get_bus()
41 dev = dev->parent; in pci_get_controller()
49 struct udevice *bus = dev->parent; in dm_pci_get_bdf()
51 return PCI_ADD_BUS(bus->seq, pplat->devfn); in dm_pci_get_bdf()
55 * pci_get_bus_max() - returns the bus number of the last active bus
57 * @return last bus number, or -1 if no active buses
63 int ret = -1; in pci_get_bus_max()
67 if (bus->seq > ret) in pci_get_bus_max()
[all …]
/openbmc/u-boot/drivers/net/
H A Dmvpp2.c8 * U-Boot version:
9 * Copyright (C) 2016-2017 Stefan Roese <sr@denx.de>
18 #include <dm/device-internal.h>
33 #include <asm-generic/gpio.h>
346 /* Per-port registers */
392 * Per-port XGMAC registers. PPv2.2 only, only for GOP port 0,
393 * relative to port->base.
491 (((index) < (q)->last_desc) ? ((index) + 1) : 0)
493 /* SMI: 0xc0054 -> offset 0x54 to lms_base */
495 /* PP2.2: SMI: 0x12a200 -> offset 0x1200 to iface_base */
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dvf610_nfc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
6 * Ported to U-Boot by Stefan Agner
17 * - Untested on MPC5125 and M54418.
18 * - DMA and pipelining not used.
19 * - 2K pages or less.
20 * - HW ECC: Only 2K page with 64+ OOB.
21 * - HW ECC: Only 24 and 32-bit error correction implemented.
62 * - 31.4.7 Flash Command Code Description, Vybrid manual
63 * - 23.8.6 Flash Command Sequencer, MPC5125 manual
[all …]
/openbmc/qemu/migration/
H A Dram.c4 * Copyright (c) 2003-2008 Fabrice Bellard
5 * Copyright (c) 2011-2015 Red Hat Inc
34 #include "qemu/main-loop.h"
38 #include "migration-stats.h"
41 #include "qemu-file.h"
42 #include "postcopy-ram.h"
44 #include "qemu/error-report.h"
46 #include "qapi/qapi-types-migration.h"
47 #include "qapi/qapi-events-migration.h"
48 #include "qapi/qapi-commands-migration.h"
[all …]

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