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/openbmc/linux/arch/arm/mach-omap2/
H A Dcm_common.c1 // SPDX-License-Identifier: GPL-2.0-only
25 * cm_ll_data: function pointers to SoC-specific implementations of
41 * cm_split_idlest_reg - split CM_IDLEST reg addr into its components
48 * via the @prcm_inst and @idlest_reg_id. Returns -EINVAL upon error,
56 if (!cm_ll_data->split_idlest_reg) { in cm_split_idlest_reg()
57 WARN_ONCE(1, "cm: %s: no low-level function defined\n", in cm_split_idlest_reg()
59 return -EINVAL; in cm_split_idlest_reg()
62 ret = cm_ll_data->split_idlest_reg(idlest_reg, prcm_inst, in cm_split_idlest_reg()
64 *prcm_inst -= cm_base.offset; in cm_split_idlest_reg()
69 * omap_cm_wait_module_ready - wait for a module to leave idle or standby
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H A Dprm_common.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Tero Kristo <t-kristo@ti.com>
24 #include <linux/clk-provider.h>
27 #include "soc.h"
45 * actual amount of memory needed for the SoC
51 * by the PRCM interrupt handler code. There will be one 'chip' per
70 * prm_ll_data: function pointers to SoC-specific implementations of
86 for (i = 0; i < prcm_irq_setup->nr_regs; i++) { in omap_prcm_events_filter_priority()
88 events[i] & prcm_irq_setup->priority_mask[i]; in omap_prcm_events_filter_priority()
99 * done by the SoC specific individual handlers.
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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
14 Apple ARM SoC platforms, including various iPhone and iPad devices and the
19 - Level-triggered hardware IRQs wired to SoC blocks
20 - Single mask bit per IRQ
21 - Per-IRQ affinity setting
22 - Automatic masking on event delivery (auto-ack)
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H A Dapple,aic2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/apple,aic2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hector Martin <marcan@marcan.st>
14 Apple ARM SoC platforms starting with t600x (M1 Pro and Max).
18 - Level-triggered hardware IRQs wired to SoC blocks
19 - Single mask bit per IRQ
20 - Automatic masking on event delivery (auto-ack)
21 - Software triggering (ORed with hw line)
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/openbmc/linux/Documentation/power/
H A Dopp.rst5 (C) 2009-2010 Nishanth Menon <nm@ti.com>, Texas Instruments Incorporated
20 -------------------------------------------------
22 Complex SoCs of today consists of a multiple sub-modules working in conjunction.
23 In an operational system executing varied use cases, not all modules in the SoC
25 facilitate this, sub-modules in a SoC are grouped into domains, allowing some
30 the device will support per domain are called Operating Performance Points or
41 - {300000000, 1000000}
42 - {800000000, 1200000}
43 - {1000000000, 1300000}
46 ----------------------------------------
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/openbmc/linux/Documentation/devicetree/bindings/remoteproc/
H A Dti,keystone-rproc.txt5 sub-systems that are used to offload some of the processor-intensive tasks or
8 These processor sub-systems usually contain additional sub-modules like L1
15 Each DSP Core sub-system is represented as a single DT node, and should also
22 --------------------
25 - compatible: Should be one of the following,
26 "ti,k2hk-dsp" for DSPs on Keystone 2 66AK2H/K SoCs
27 "ti,k2l-dsp" for DSPs on Keystone 2 66AK2L SoCs
28 "ti,k2e-dsp" for DSPs on Keystone 2 66AK2E SoCs
29 "ti,k2g-dsp" for DSPs on Keystone 2 66AK2G SoCs
31 - reg: Should contain an entry for each value in 'reg-names'.
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/openbmc/linux/drivers/crypto/allwinner/
H A DKconfig19 Some Allwinner SoC have a crypto accelerator named
25 will be called sun4i-ss.
32 Select this option if you want to provide kernel-side support for
33 the Pseudo-Random Number Generator found in the Security System.
36 bool "Enable sun4i-ss stats"
40 Say y to enable sun4i-ss debug stats.
41 This will create /sys/kernel/debug/sun4i-ss/stats for displaying
42 the number of requests per algorithm.
56 Allwinner SoC H2+, H3, H5, H6, R40 and A64.
60 will be called sun8i-ce.
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/openbmc/linux/drivers/pinctrl/intel/
H A Dpinctrl-intel.h1 /* SPDX-License-Identifier: GPL-2.0 */
26 * struct intel_pingroup - Description about group of pins
38 * struct intel_function - Description about a function
48 * struct intel_padgroup - Hardware pad group information
67 * enum - Special treatment for GPIO base in pad group
74 INTEL_GPIO_BASE_ZERO = -2,
75 INTEL_GPIO_BASE_NOMAP = -1,
80 * struct intel_community - Intel pin community description
100 * @pad_map: Optional non-linear mapping of the pads
145 #define __INTEL_COMMUNITY(b, s, e, g, n, gs, gn, soc) \ argument
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/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-davinci.txt7 - compatible: "ti,davinci-i2c" or "ti,keystone-i2c";
8 - reg : Offset and length of the register set for the device
9 - clocks: I2C functional clock phandle.
10 For 66AK2G this property should be set per binding,
11 Documentation/devicetree/bindings/clock/ti,sci-clk.yaml
13 SoC-specific Required Properties:
17 - power-domains: Should contain a phandle to a PM domain provider node
19 value. This property is as per the binding,
20 Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml
23 - interrupts : standard interrupt property.
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/openbmc/linux/Documentation/devicetree/bindings/timer/
H A Dnxp,tpm-timer.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/timer/nxp,tpm-timer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
23 - const: fsl,imx7ulp-tpm
24 - items:
25 - const: fsl,imx8ulp-tpm
26 - const: fsl,imx7ulp-tpm
36 - description: SoC TPM ipg clock
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H A Dfsl,imxgpt.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
15 - const: fsl,imx1-gpt
16 - const: fsl,imx21-gpt
17 - items:
18 - const: fsl,imx27-gpt
19 - const: fsl,imx21-gpt
20 - const: fsl,imx31-gpt
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/openbmc/linux/Documentation/devicetree/bindings/pwm/
H A Dimx-pwm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pwm/imx-pwm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Philipp Zabel <p.zabel@pengutronix.de>
13 - $ref: pwm.yaml#
16 "#pwm-cells":
21 - 2
22 - 3
26 - enum:
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-davinci.txt4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
[all …]
H A Dspi-fsl-lpspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - enum:
19 - fsl,imx7ulp-spi
20 - fsl,imx8qxp-spi
21 - items:
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H A Dfsl-imx-cspi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/fsl-imx-cspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - const: fsl,imx1-cspi
19 - const: fsl,imx21-cspi
20 - const: fsl,imx27-cspi
21 - const: fsl,imx31-cspi
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/openbmc/linux/Documentation/admin-guide/perf/
H A Dthunderx2-pmu.rst2 Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE)
5 The ThunderX2 SoC PMU consists of independent, system-wide, per-socket
16 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
17 The CCPI2 counters are 64-bit and assumed not to overflow in normal operation.
21 The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
28 work. Per-task perf sessions are also not supported.
32 # perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1
34 # perf stat -a -e \
40 # perf stat -a -e \
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra234-pinmux-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra234-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - description: pinmux registers
19 "^pinmux(-[a-z0-9-]+)?$":
24 $ref: nvidia,tegra-pinmux-common.yaml
27 # for all chip generations. In this case, however, we want the per-SoC
[all …]
H A Dberlin,pinctrl.txt1 * Pin-controller driver for the Marvell Berlin SoCs
4 controller register sets. Pin controller nodes should be a sub-node of
9 A pin-controller node should contain subnodes representing the pin group
10 configurations, one per function. Each subnode has the group name and
14 is called a 'function' in the pin-controller subsystem.
17 - compatible: should be one of:
18 "marvell,berlin2-soc-pinctrl",
19 "marvell,berlin2-system-pinctrl",
20 "marvell,berlin2cd-soc-pinctrl",
21 "marvell,berlin2cd-system-pinctrl",
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/openbmc/linux/Documentation/devicetree/bindings/cpufreq/
H A Dapple,cluster-cpufreq.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Apple SoC cluster cpufreq device
10 - Hector Martin <marcan@marcan.st>
13 Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
15 operating-points-v2 table to define the CPU performance states, with the
16 opp-level property specifying the hardware p-state index for that level.
21 - items:
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/openbmc/linux/drivers/cpufreq/
H A Dtegra194-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2020 - 2022, NVIDIA CORPORATION. All rights reserved
9 #include <linux/dma-mapping.h>
19 #include <soc/tegra/bpmp.h>
20 #include <soc/tegra/bpmp-abi.h>
32 #define SCRATCH_FREQ_CORE_REG(data, cpu) (data->regs + CMU_CLKS_BASE + CORE_OFFSET(cpu))
36 (data->regs + (MMCRAB_CLUSTER_BASE(cl) + data->soc->actmon_cntr_base))
70 const struct tegra_cpufreq_soc *soc; member
83 dev = get_cpu_device(policy->cpu); in tegra_cpufreq_set_bw()
85 return -ENODEV; in tegra_cpufreq_set_bw()
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/openbmc/qemu/hw/riscv/
H A Dvirt.c2 * QEMU RISC-V VirtIO Board
6 * RISC-V machine with 16550a UART and VirtIO MMIO
23 #include "qemu/error-report.h"
24 #include "qemu/guest-random.h"
29 #include "hw/qdev-properties.h"
30 #include "hw/char/serial-mm.h"
32 #include "hw/core/sysbus-fdt.h"
45 #include "hw/platform-bus.h"
54 #include "hw/pci-host/gpex.h"
56 #include "hw/acpi/aml-build.h"
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/openbmc/linux/Documentation/admin-guide/media/
H A Dfimc.rst1 .. SPDX-License-Identifier: GPL-2.0
8 Copyright |copy| 2012 - 2013 Samsung Electronics Co., Ltd.
11 SoC Application Processors is an integrated camera host interface, color
13 data from LCD controller (FIMD) through the SoC internal writeback data
17 drivers/media/platform/samsung/exynos4-is directory.
20 --------------
22 S5PC100 (mem-to-mem only), S5PV210, Exynos4210
25 ------------------
27 - camera parallel interface capture (ITU-R.BT601/565);
28 - camera serial interface capture (MIPI-CSI2);
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/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dnxp,imx8qxp-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/nxp,imx8qxp-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Cai Huoqing <caihuoqing@baidu.com>
13 Supports the ADC found on the IMX8QXP SoC.
17 const: nxp,imx8qxp-adc
28 clock-names:
30 - const: per
31 - const: ipg
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/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dmxs-lradc.txt4 - compatible: Should be "fsl,imx23-lradc" for i.MX23 SoC and "fsl,imx28-lradc"
5 for i.MX28 SoC
6 - reg: Address and length of the register set for the device
7 - interrupts: Should contain the LRADC interrupts
10 - fsl,lradc-touchscreen-wires: Number of wires used to connect the touchscreen
13 disabled. 5 wires is valid for i.MX28 SoC only.
14 - fsl,ave-ctrl: number of samples per direction to calculate an average value.
16 - fsl,ave-delay: delay between consecutive samples. Allowed value is
17 2 ... 2048. It is used if 'fsl,ave-ctrl' > 1, counts at
19 - fsl,settling: delay between plate switch to next sample. Allowed value is
[all …]
/openbmc/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-moore.c1 // SPDX-License-Identifier: GPL-2.0
3 * MediaTek Pinctrl Moore Driver, which implement the generic dt-binding
4 * pinctrl-bindings.txt for MediaTek SoC.
6 * Copyright (C) 2017-2018 MediaTek Inc.
11 #include <dt-bindings/pinctrl/mt65xx.h>
16 #include "pinctrl-moore.h"
29 {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
30 {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
37 PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
38 PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
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