1be8faebcSAnson Huang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2be8faebcSAnson Huang%YAML 1.2
3be8faebcSAnson Huang---
4be8faebcSAnson Huang$id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5be8faebcSAnson Huang$schema: http://devicetree.org/meta-schemas/core.yaml#
6be8faebcSAnson Huang
7be8faebcSAnson Huangtitle: Freescale Low Power SPI (LPSPI) for i.MX
8be8faebcSAnson Huang
9be8faebcSAnson Huangmaintainers:
10be8faebcSAnson Huang  - Anson Huang <Anson.Huang@nxp.com>
11be8faebcSAnson Huang
12be8faebcSAnson HuangallOf:
1399a7fa0eSKrzysztof Kozlowski  - $ref: /schemas/spi/spi-controller.yaml#
14be8faebcSAnson Huang
15be8faebcSAnson Huangproperties:
16be8faebcSAnson Huang  compatible:
1749cd1eb3SJacky Bai    oneOf:
1849cd1eb3SJacky Bai      - enum:
19be8faebcSAnson Huang          - fsl,imx7ulp-spi
20be8faebcSAnson Huang          - fsl,imx8qxp-spi
2149cd1eb3SJacky Bai      - items:
22d9c6a706SPeng Fan          - enum:
23d9c6a706SPeng Fan              - fsl,imx8ulp-spi
24d9c6a706SPeng Fan              - fsl,imx93-spi
2549cd1eb3SJacky Bai          - const: fsl,imx7ulp-spi
26be8faebcSAnson Huang  reg:
27be8faebcSAnson Huang    maxItems: 1
28be8faebcSAnson Huang
29be8faebcSAnson Huang  interrupts:
30be8faebcSAnson Huang    maxItems: 1
31be8faebcSAnson Huang
32be8faebcSAnson Huang  clocks:
33be8faebcSAnson Huang    items:
34be8faebcSAnson Huang      - description: SoC SPI per clock
35be8faebcSAnson Huang      - description: SoC SPI ipg clock
36be8faebcSAnson Huang
37be8faebcSAnson Huang  clock-names:
38be8faebcSAnson Huang    items:
39be8faebcSAnson Huang      - const: per
40be8faebcSAnson Huang      - const: ipg
41be8faebcSAnson Huang
42fba933c2SPeng Fan  dmas:
43fba933c2SPeng Fan    items:
44fba933c2SPeng Fan      - description: TX DMA Channel
45fba933c2SPeng Fan      - description: RX DMA Channel
46fba933c2SPeng Fan
47fba933c2SPeng Fan  dma-names:
48fba933c2SPeng Fan    items:
49fba933c2SPeng Fan      - const: tx
50fba933c2SPeng Fan      - const: rx
51fba933c2SPeng Fan
527ac9bbf6SClark Wang  fsl,spi-only-use-cs1-sel:
537ac9bbf6SClark Wang    description:
547ac9bbf6SClark Wang      spi common code does not support use of CS signals discontinuously.
557ac9bbf6SClark Wang      i.MX8DXL-EVK board only uses CS1 without using CS0. Therefore, add
567ac9bbf6SClark Wang      this property to re-config the chipselect value in the LPSPI driver.
570454357fSGeert Uytterhoeven    type: boolean
587ac9bbf6SClark Wang
59bc9ab1b7SHan Xu  num-cs:
60bc9ab1b7SHan Xu    description:
61bc9ab1b7SHan Xu      number of chip selects.
62bc9ab1b7SHan Xu    minimum: 1
63bc9ab1b7SHan Xu    maximum: 2
64bc9ab1b7SHan Xu    default: 1
65bc9ab1b7SHan Xu
66*49aa7716SAlexander Stein  power-domains:
67*49aa7716SAlexander Stein    maxItems: 1
68*49aa7716SAlexander Stein
69be8faebcSAnson Huangrequired:
70be8faebcSAnson Huang  - compatible
71be8faebcSAnson Huang  - reg
72be8faebcSAnson Huang  - interrupts
73be8faebcSAnson Huang  - clocks
74be8faebcSAnson Huang  - clock-names
75be8faebcSAnson Huang
76be8faebcSAnson HuangunevaluatedProperties: false
77be8faebcSAnson Huang
78be8faebcSAnson Huangexamples:
79be8faebcSAnson Huang  - |
80be8faebcSAnson Huang    #include <dt-bindings/clock/imx7ulp-clock.h>
81be8faebcSAnson Huang    #include <dt-bindings/interrupt-controller/arm-gic.h>
82be8faebcSAnson Huang
83be8faebcSAnson Huang    spi@40290000 {
84be8faebcSAnson Huang        compatible = "fsl,imx7ulp-spi";
85be8faebcSAnson Huang        reg = <0x40290000 0x10000>;
86be8faebcSAnson Huang        interrupt-parent = <&intc>;
87be8faebcSAnson Huang        interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
88be8faebcSAnson Huang        clocks = <&clks IMX7ULP_CLK_LPSPI2>,
89be8faebcSAnson Huang                 <&clks IMX7ULP_CLK_DUMMY>;
90be8faebcSAnson Huang        clock-names = "per", "ipg";
91be8faebcSAnson Huang        spi-slave;
927ac9bbf6SClark Wang        fsl,spi-only-use-cs1-sel;
93bc9ab1b7SHan Xu        num-cs = <2>;
94be8faebcSAnson Huang    };
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