1*d1a8368dSHector Martin# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2*d1a8368dSHector Martin%YAML 1.2
3*d1a8368dSHector Martin---
4*d1a8368dSHector Martin$id: http://devicetree.org/schemas/cpufreq/apple,cluster-cpufreq.yaml#
5*d1a8368dSHector Martin$schema: http://devicetree.org/meta-schemas/core.yaml#
6*d1a8368dSHector Martin
7*d1a8368dSHector Martintitle: Apple SoC cluster cpufreq device
8*d1a8368dSHector Martin
9*d1a8368dSHector Martinmaintainers:
10*d1a8368dSHector Martin  - Hector Martin <marcan@marcan.st>
11*d1a8368dSHector Martin
12*d1a8368dSHector Martindescription: |
13*d1a8368dSHector Martin  Apple SoCs (e.g. M1) have a per-cpu-cluster DVFS controller that is part of
14*d1a8368dSHector Martin  the cluster management register block. This binding uses the standard
15*d1a8368dSHector Martin  operating-points-v2 table to define the CPU performance states, with the
16*d1a8368dSHector Martin  opp-level property specifying the hardware p-state index for that level.
17*d1a8368dSHector Martin
18*d1a8368dSHector Martinproperties:
19*d1a8368dSHector Martin  compatible:
20*d1a8368dSHector Martin    oneOf:
21*d1a8368dSHector Martin      - items:
22*d1a8368dSHector Martin          - enum:
23*d1a8368dSHector Martin              - apple,t8103-cluster-cpufreq
24*d1a8368dSHector Martin              - apple,t8112-cluster-cpufreq
25*d1a8368dSHector Martin          - const: apple,cluster-cpufreq
26*d1a8368dSHector Martin      - items:
27*d1a8368dSHector Martin          - const: apple,t6000-cluster-cpufreq
28*d1a8368dSHector Martin          - const: apple,t8103-cluster-cpufreq
29*d1a8368dSHector Martin          - const: apple,cluster-cpufreq
30*d1a8368dSHector Martin
31*d1a8368dSHector Martin  reg:
32*d1a8368dSHector Martin    maxItems: 1
33*d1a8368dSHector Martin
34*d1a8368dSHector Martin  '#performance-domain-cells':
35*d1a8368dSHector Martin    const: 0
36*d1a8368dSHector Martin
37*d1a8368dSHector Martinrequired:
38*d1a8368dSHector Martin  - compatible
39*d1a8368dSHector Martin  - reg
40*d1a8368dSHector Martin  - '#performance-domain-cells'
41*d1a8368dSHector Martin
42*d1a8368dSHector MartinadditionalProperties: false
43*d1a8368dSHector Martin
44*d1a8368dSHector Martinexamples:
45*d1a8368dSHector Martin  - |
46*d1a8368dSHector Martin    // This example shows a single CPU per domain and 2 domains,
47*d1a8368dSHector Martin    // with two p-states per domain.
48*d1a8368dSHector Martin    // Shipping hardware has 2-4 CPUs per domain and 2-6 domains.
49*d1a8368dSHector Martin    cpus {
50*d1a8368dSHector Martin      #address-cells = <2>;
51*d1a8368dSHector Martin      #size-cells = <0>;
52*d1a8368dSHector Martin
53*d1a8368dSHector Martin      cpu@0 {
54*d1a8368dSHector Martin        compatible = "apple,icestorm";
55*d1a8368dSHector Martin        device_type = "cpu";
56*d1a8368dSHector Martin        reg = <0x0 0x0>;
57*d1a8368dSHector Martin        operating-points-v2 = <&ecluster_opp>;
58*d1a8368dSHector Martin        performance-domains = <&cpufreq_e>;
59*d1a8368dSHector Martin      };
60*d1a8368dSHector Martin
61*d1a8368dSHector Martin      cpu@10100 {
62*d1a8368dSHector Martin        compatible = "apple,firestorm";
63*d1a8368dSHector Martin        device_type = "cpu";
64*d1a8368dSHector Martin        reg = <0x0 0x10100>;
65*d1a8368dSHector Martin        operating-points-v2 = <&pcluster_opp>;
66*d1a8368dSHector Martin        performance-domains = <&cpufreq_p>;
67*d1a8368dSHector Martin      };
68*d1a8368dSHector Martin    };
69*d1a8368dSHector Martin
70*d1a8368dSHector Martin    ecluster_opp: opp-table-0 {
71*d1a8368dSHector Martin      compatible = "operating-points-v2";
72*d1a8368dSHector Martin      opp-shared;
73*d1a8368dSHector Martin
74*d1a8368dSHector Martin      opp01 {
75*d1a8368dSHector Martin        opp-hz = /bits/ 64 <600000000>;
76*d1a8368dSHector Martin        opp-level = <1>;
77*d1a8368dSHector Martin        clock-latency-ns = <7500>;
78*d1a8368dSHector Martin      };
79*d1a8368dSHector Martin      opp02 {
80*d1a8368dSHector Martin        opp-hz = /bits/ 64 <972000000>;
81*d1a8368dSHector Martin        opp-level = <2>;
82*d1a8368dSHector Martin        clock-latency-ns = <22000>;
83*d1a8368dSHector Martin      };
84*d1a8368dSHector Martin    };
85*d1a8368dSHector Martin
86*d1a8368dSHector Martin    pcluster_opp: opp-table-1 {
87*d1a8368dSHector Martin      compatible = "operating-points-v2";
88*d1a8368dSHector Martin      opp-shared;
89*d1a8368dSHector Martin
90*d1a8368dSHector Martin      opp01 {
91*d1a8368dSHector Martin        opp-hz = /bits/ 64 <600000000>;
92*d1a8368dSHector Martin        opp-level = <1>;
93*d1a8368dSHector Martin        clock-latency-ns = <8000>;
94*d1a8368dSHector Martin      };
95*d1a8368dSHector Martin      opp02 {
96*d1a8368dSHector Martin        opp-hz = /bits/ 64 <828000000>;
97*d1a8368dSHector Martin        opp-level = <2>;
98*d1a8368dSHector Martin        clock-latency-ns = <19000>;
99*d1a8368dSHector Martin      };
100*d1a8368dSHector Martin    };
101*d1a8368dSHector Martin
102*d1a8368dSHector Martin    soc {
103*d1a8368dSHector Martin      #address-cells = <2>;
104*d1a8368dSHector Martin      #size-cells = <2>;
105*d1a8368dSHector Martin
106*d1a8368dSHector Martin      cpufreq_e: performance-controller@210e20000 {
107*d1a8368dSHector Martin        compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
108*d1a8368dSHector Martin        reg = <0x2 0x10e20000 0 0x1000>;
109*d1a8368dSHector Martin        #performance-domain-cells = <0>;
110*d1a8368dSHector Martin      };
111*d1a8368dSHector Martin
112*d1a8368dSHector Martin      cpufreq_p: performance-controller@211e20000 {
113*d1a8368dSHector Martin        compatible = "apple,t8103-cluster-cpufreq", "apple,cluster-cpufreq";
114*d1a8368dSHector Martin        reg = <0x2 0x11e20000 0 0x1000>;
115*d1a8368dSHector Martin        #performance-domain-cells = <0>;
116*d1a8368dSHector Martin      };
117*d1a8368dSHector Martin    };
118