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/openbmc/linux/Documentation/devicetree/bindings/pci/
H A Daxis,artpec6-pcie.txt1 * Axis ARTPEC-6 PCIe interface
3 This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4 and thus inherits all the common properties defined in snps,dw-pcie.yaml.
7 - compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode;
8 "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode;
9 "axis,artpec7-pcie", "snps,dw-pcie" for ARTPEC-7 in RC mode;
10 "axis,artpec7-pcie-ep", "snps,dw-pcie" for ARTPEC-7 in EP mode;
11 - reg: base addresses and lengths of the PCIe controller (DBI),
13 - reg-names: Must include the following entries:
14 - "dbi"
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H A Dqcom,pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/qcom,pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Qualcomm PCIe root complex controller is based on the Synopsys DesignWare
15 PCIe IP.
20 - enum:
21 - qcom,pcie-apq8064
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H A Dmediatek-pcie-gen3.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Gen3 PCIe controller on MediaTek SoCs
10 - Jianjun Wang <jianjun.wang@mediatek.com>
13 PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
16 This PCIe controller supports up to 256 MSI vectors, the MSI hardware
19 +-----+
21 +-----+
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H A Dfsl,imx6q-pcie-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX6 PCIe RC/EP controller
10 - Lucas Stach <l.stach@pengutronix.de>
11 - Richard Zhu <hongxing.zhu@nxp.com>
14 Generic Freescale i.MX PCIe Root Port and Endpoint controller
22 clock-names:
26 num-lanes:
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H A Dnvidia,tegra194-pcie-ep.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based)
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Vidya Sagar <vidyas@nvidia.com>
15 This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16 inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some
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H A Dhisilicon,kirin-pcie.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/hisilicon,kirin-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: HiSilicon Kirin SoCs PCIe host DT description
10 - Xiaowei Song <songxiaowei@hisilicon.com>
11 - Binghui Wang <wangbinghui@hisilicon.com>
14 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
15 It shares common functions with the PCIe DesignWare core driver and
17 Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
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H A Dbaikal,bt1-pcie.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pci/baikal,bt1-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 PCIe Root Port Controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 Embedded into Baikal-T1 SoC Root Complex controller with a single port
14 activated. It's based on the DWC RC PCIe v4.60a IP-core, which is configured
18 performed by software. There four in- and four outbound iATU regions
19 which can be used to emit all required TLP types on the PCIe bus.
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/openbmc/linux/drivers/phy/broadcom/
H A Dphy-bcm-sr-pcie.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Broadcom
18 #define SR_PAXC_PHY_IDX (SR_NR_PCIE_PHYS - 1)
40 * struct sr_pcie_phy - Stingray PCIe PHY
42 * @core: pointer to the Stingray PCIe PHY core control
53 * struct sr_pcie_phy_core - Stingray PCIe PHY core control
56 * @base: base register of PCIe SS
60 * @phys: array of PCIe PHYs
72 * PCIe PIPEMUX lookup table
75 * The array element represents a bitmap where a set bit means the PCIe
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/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dmvebu-gated-clock.txt12 -----------------------------------
14 1 pex0_en PCIe 0 Clock out
15 2 pex1_en PCIe 1 Clock out
18 5 pex0 PCIe Cntrl 0
19 9 pex1 PCIe Cntrl 1
29 -----------------------------------
33 5 pex0 PCIe 0 Clock out
34 6 pex1 PCIe 1 Clock out
56 -----------------------------------
61 5 pex1 PCIe 1
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/openbmc/linux/drivers/pci/controller/cadence/
H A Dpcie-cadence.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
11 #include <linux/pci-epf.h>
79 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)
81 (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
105 (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6))
107 (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6))
109 (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6))
111 (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6))
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/openbmc/qemu/docs/config/
H A Dq35-virtio-serial.cfg1 # q35 - VirtIO guest (serial console)
6 # $ qemu-system-x86_64 \
7 # -nodefaults \
8 # -readconfig q35-virtio-serial.cfg \
9 # -display none -serial mon:stdio
18 # ---------------------------------------------------------
20 # Using -nodefaults is required to have full control over
43 # We use '-display none' to prevent QEMU from creating a
45 # this specific configuration, and '-serial mon:stdio' to
79 [device "pcie.1"]
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H A Dq35-virtio-graphical.cfg1 # q35 - VirtIO guest (graphical console)
6 # $ qemu-system-x86_64 \
7 # -nodefaults \
8 # -readconfig q35-virtio-graphical.cfg
17 # ---------------------------------------------------------
19 # Using -nodefaults is required to have full control over
74 [device "pcie.1"]
75 driver = "pcie-root-port"
76 bus = "pcie.0"
82 [device "pcie.2"]
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H A Dmach-virt-serial.cfg1 # mach-virt - VirtIO guest (serial console)
6 # $ qemu-system-aarch64 \
7 # -nodefaults \
8 # -readconfig mach-virt-serial.cfg \
9 # -display none -serial mon:stdio \
10 # -cpu host
19 # ---------------------------------------------------------
21 # Using -nodefaults is required to have full control over
40 # We use '-display none' to prevent QEMU from creating a
42 # this specific configuration, and '-serial mon:stdio' to
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H A Dmach-virt-graphical.cfg1 # mach-virt - VirtIO guest (graphical console)
6 # $ qemu-system-aarch64 \
7 # -nodefaults \
8 # -readconfig mach-virt-graphical.cfg \
9 # -cpu host
18 # ---------------------------------------------------------
20 # Using -nodefaults is required to have full control over
59 gic-version = "host"
71 # There are two parts to the firmware: a read-only image
87 # edk2-aarch64 (pkg)
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/openbmc/linux/drivers/pci/controller/dwc/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
3 menu "DesignWare-based PCIe controllers"
18 bool "Amazon Annapurna Labs PCIe controller"
24 Say Y here to enable support of the Amazon's Annapurna Labs PCIe
25 controller IP on Amazon SoCs. The PCIe controller uses the DesignWare
27 required only for DT-based platforms. ACPI platforms with the
28 Annapurna Labs PCIe controller don't need to enable this.
31 tristate "Amlogic Meson PCIe controller"
38 and therefore the driver re-uses the DesignWare core functions to
45 bool "Axis ARTPEC-6 PCIe controller (host mode)"
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H A Dpcie-qcom.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm PCIe root complex driver
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
27 #include <linux/phy/pcie.h>
35 #include "pcie-designware.h"
78 #define CORE_CLK_CGC_DIS BIT(6)
93 #define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x)
162 #define QCOM_PCIE_2_1_0_MAX_RESETS 6
222 int (*get_resources)(struct qcom_pcie *pcie);
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/openbmc/linux/drivers/net/wireless/realtek/rtw89/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
6 This module adds support for mac80211-based wireless drivers that
32 tristate "Realtek 8851BE PCI wireless network (Wi-Fi 6) adapter"
40 802.11ax PCIe wireless network (Wi-Fi 6) adapter
43 tristate "Realtek 8852AE PCI wireless network (Wi-Fi 6) adapter"
51 802.11ax PCIe wireless network (Wi-Fi 6) adapter
54 tristate "Realtek 8852BE PCI wireless network (Wi-Fi 6) adapter"
62 802.11ax PCIe wireless network (Wi-Fi 6) adapter
65 tristate "Realtek 8852CE PCI wireless network (Wi-Fi 6E) adapter"
73 802.11ax PCIe wireless network (Wi-Fi 6E) adapter
/openbmc/linux/arch/arm/mach-mv78xx0/
H A Dmv78xx0.h1 /* SPDX-License-Identifier: GPL-2.0-only */
16 * c0000000 PCIe Memory space
17 * f0800000 PCIe #0 I/O space
18 * f0900000 PCIe #1 I/O space
19 * f0a00000 PCIe #2 I/O space
20 * f0b00000 PCIe #3 I/O space
21 * f0c00000 PCIe #4 I/O space
22 * f0d00000 PCIe #5 I/O space
23 * f0e00000 PCIe #6 I/O space
24 * f0f00000 PCIe #7 I/O space
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-hsio-blk-ctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8MP HSIO blk-ctrl
10 - Lucas Stach <l.stach@pengutronix.de>
13 The i.MX8MP HSIO blk-ctrl is a top-level peripheral providing access to
14 the NoC and ensuring proper power sequencing of the high-speed IO
15 (USB an PCIe) peripherals located in the HSIO domain of the SoC.
20 - const: fsl,imx8mp-hsio-blk-ctrl
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,sc8280xp-qmp-pcie-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-pcie-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm QMP PHY controller (PCIe, SC8280XP)
10 - Vinod Koul <vkoul@kernel.org>
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
19 - qcom,sa8775p-qmp-gen4x2-pcie-phy
20 - qcom,sa8775p-qmp-gen4x4-pcie-phy
21 - qcom,sc8180x-qmp-pcie-phy
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dturris1x.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013 - 2022 CZ.NIC z.s.p.o. (http://www.nic.cz/)
8 * and available at: https://docs.turris.cz/hw/turris-1x/turris-1x/
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/irq.h>
13 #include <dt-bindings/leds/common.h>
14 /include/ "fsl/p2020si-pre.dtsi"
41 gpio-controller@18 {
45 #gpio-cells = <2>;
46 gpio-controller;
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/openbmc/qemu/tests/qtest/
H A Dreadconfig-test.c2 * Validate -readconfig
7 * See the COPYING file in the top-level directory.
13 #include "qapi/qapi-visit-machine.h"
14 #include "qapi/qapi-visit-qom.h"
15 #include "qapi/qapi-visit-ui.h"
18 #include "qapi/qobject-input-visitor.h"
26 int cfgfd = -1; in qtest_init_with_config()
31 cfgfd = g_file_open_tmp("readconfig-test-XXXXXX", &cfgpath, &error); in qtest_init_with_config()
42 args = g_strdup_printf("-nodefaults -machine none -readconfig %s", cfgpath); in qtest_init_with_config()
62 g_assert(memdevs->value); in test_x86_memdev_resp()
[all …]
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dconfig_mpc85xx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
56 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
93 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
127 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
144 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
165 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
182 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
202 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
229 #define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra72x.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2014 Texas Instruments Incorporated - https://www.ti.com/
20 compatible = "arm,cortex-a15-pmu";
21 interrupt-parent = <&wakeupgen>;
27 target-module@5b000 { /* 0x4845b000, ap 59 46.0 */
28 compatible = "ti,sysc-omap4", "ti,sysc";
31 reg-names = "rev", "sysc";
32 ti,sysc-midle = <SYSC_IDLE_FORCE>,
34 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
37 clock-names = "fck";
[all …]
/openbmc/u-boot/drivers/pci/
H A Dpci-aardvark.c20 * Ported from Linux driver - driver/pci/host/pci-aardvark.c
31 #include <asm-generic/gpio.h>
34 /* PCIe core registers */
46 #define PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN BIT(6)
88 #define LINK_TRAINING_EN BIT(6)
93 #define PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE BIT(6)
102 /* PCIe core controller registers */
126 /* PCIe Retries & Timeout definitions */
135 * struct pcie_advk - Advk PCIe controller state
138 * @first_busno: This driver supports multiple PCIe controllers.
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