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/openbmc/linux/drivers/nvmem/
H A Dlpc18xx_otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * NXP LPC18xx/43xx OTP memory NVMEM driver
10 * TODO: add support for writing OTP register via API in boot ROM.
15 #include <linux/nvmem-provider.h>
21 * LPC18xx OTP memory contains 4 banks with 4 32-bit words. Bank 0 starts
26 * Bank 1/2 is generale purpose or AES key storage for secure devices.
43 struct lpc18xx_otp *otp = context; in lpc18xx_otp_read() local
44 unsigned int count = bytes >> 2; in lpc18xx_otp_read()
45 u32 index = offset >> 2; in lpc18xx_otp_read()
49 if (count > (LPC18XX_OTP_SIZE - index)) in lpc18xx_otp_read()
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H A Drockchip-otp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Rockchip OTP Driver
6 * Author: Finley Xiao <finley.xiao@rock-chips.com>
15 #include <linux/nvmem-provider.h>
22 /* OTP Register Offsets */
35 /* OTP Register bits and masks */
42 #define OTPC_USER_DONE BIT(2)
85 static int rockchip_otp_reset(struct rockchip_otp *otp) in rockchip_otp_reset() argument
89 ret = reset_control_assert(otp->rst); in rockchip_otp_reset()
91 dev_err(otp->dev, "failed to assert otp phy %d\n", ret); in rockchip_otp_reset()
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H A Dsunplus-ocotp.c1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/nvmem-provider.h>
21 * OTP memory
47 #define OTP_READ BIT(2)
55 #define OTP_LOAD_SECURE_DONE_MASK ~BIT(2)
78 static int sp_otp_read_real(struct sp_ocotp_priv *otp, int addr, char *value) in sp_otp_read_real() argument
94 writel(readl(otp->base[OTPRX] + OTP_STATUS) & OTP_READ_DONE_MASK & in sp_otp_read_real()
95 OTP_LOAD_SECURE_DONE_MASK, otp->base[OTPRX] + OTP_STATUS); in sp_otp_read_real()
96 writel(addr, otp->base[OTPRX] + OTP_READ_ADDRESS); in sp_otp_read_real()
97 writel(readl(otp->base[OTPRX] + OTP_CONTROL_2) | OTP_READ, in sp_otp_read_real()
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H A Dlan9662-otpc.c1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/nvmem-provider.h>
24 #define OTP_OTP_PASS_FAIL_OTP_WRITE_PROHIBITED BIT(2)
47 static int lan9662_otp_power(struct lan9662_otp *otp, bool up) in lan9662_otp_power() argument
49 void __iomem *pwrdn = OTP_OTP_PWR_DN(otp->base); in lan9662_otp_power()
53 if (lan9662_otp_wait_flag_clear(OTP_OTP_STATUS(otp->base), in lan9662_otp_power()
55 return -ETIMEDOUT; in lan9662_otp_power()
63 static int lan9662_otp_execute(struct lan9662_otp *otp) in lan9662_otp_execute() argument
65 if (lan9662_otp_wait_flag_clear(OTP_OTP_CMD_GO(otp->base), in lan9662_otp_execute()
67 return -ETIMEDOUT; in lan9662_otp_execute()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
37 calibration data required for the PCIe or the USB-C PHY.
40 be called nvmem-apple-efuses.
43 tristate "Broadcom On-Chip OTP Controller support"
48 Say y here to enable read/write access to the Broadcom OTP
52 will be called nvmem-bcm-ocotp.
72 will be called nvmem-imx-iim.
75 tristate "i.MX 6/7/8 On-Chip OTP Controller support"
79 This is a driver for the On-Chip OTP Controller (OCOTP) available on
80 i.MX6 SoCs, providing access to 4 Kbits of one-time programmable
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H A Dimx-ocotp.c1 // SPDX-License-Identifier: GPL-2.0-only
14 * Copyright (C) 2010-2013 Freescale Semiconductor, Inc
21 #include <linux/nvmem-provider.h>
28 * OTP Bank0 Word0
31 * of two consecutive OTP words.
106 void __iomem *base = priv->base; in imx_ocotp_wait_for_busy()
108 bm_ctrl_busy = priv->params->ctrl.bm_busy; in imx_ocotp_wait_for_busy()
109 bm_ctrl_error = priv->params->ctrl.bm_error; in imx_ocotp_wait_for_busy()
113 for (count = 10000; count >= 0; count--) { in imx_ocotp_wait_for_busy()
123 * - A write is performed to a shadow register during a shadow in imx_ocotp_wait_for_busy()
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H A Dstm32-romem.c1 // SPDX-License-Identifier: GPL-2.0
3 * STM32 Factory-programmed memory read access driver
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
9 #include <linux/arm-smccc.h>
12 #include <linux/nvmem-provider.h>
16 #include "stm32-bsec-optee-ta.h"
18 /* BSEC secure service access from non-secure */
49 *buf8++ = readb_relaxed(priv->base + i); in stm32_romem_read()
54 static int stm32_bsec_smc(u8 op, u32 otp, u32 data, u32 *result) in stm32_bsec_smc() argument
59 arm_smccc_smc(STM32_SMC_BSEC, op, otp, data, 0, 0, 0, 0, &res); in stm32_bsec_smc()
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/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Drockchip,otp.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/rockchip,otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip internal OTP (One Time Programmable) memory
10 - Heiko Stuebner <heiko@sntech.de>
15 - rockchip,px30-otp
16 - rockchip,rk3308-otp
17 - rockchip,rk3588-otp
26 clock-names:
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H A Dnintendo-otp.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/nvmem/nintendo-otp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nintendo Wii and Wii U OTP
10 This binding represents the OTP memory as found on a Nintendo Wii or Wii U,
11 which contains common and per-console keys, signatures and related data
14 See https://wiiubrew.org/wiki/Hardware/OTP
17 - Emmanuel Gil Peyrot <linkmauve@linkmauve.fr>
20 - $ref: nvmem.yaml#
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H A Dst,stm32-romem.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/nvmem/st,stm32-romem.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 Factory-programmed data
10 This represents STM32 Factory-programmed read only non-volatile area: locked
11 flash, OTP, read-only HW regs... This contains various information such as:
16 - Fabrice Gasnier <fabrice.gasnier@foss.st.com>
19 - $ref: nvmem.yaml#
24 - st,stm32f4-otp
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/
H A Diwl-eeprom-read.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2005-2014, 2018-2019, 2021 Intel Corporation
9 #include "iwl-drv.h"
10 #include "iwl-debug.h"
11 #include "iwl-eeprom-read.h"
12 #include "iwl-io.h"
13 #include "iwl-prph.h"
14 #include "iwl-csr.h"
22 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG.
52 IWL_DEBUG_EEPROM(trans->dev, in iwl_eeprom_acquire_semaphore()
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/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/
H A Deeprom.c1 // SPDX-License-Identifier: ISC
25 return -ETIMEDOUT; in mt7615_efuse_read()
27 udelay(2); in mt7615_efuse_read()
50 if (is_mt7663(&dev->mt76)) in mt7615_efuse_init()
57 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7615_efuse_init()
58 dev->mt76.otp.size = len; in mt7615_efuse_init()
59 if (!dev->mt76.otp.data) in mt7615_efuse_init()
60 return -ENOMEM; in mt7615_efuse_init()
62 buf = dev->mt76.otp.data; in mt7615_efuse_init()
80 ret = mt76_eeprom_init(&dev->mt76, MT7615_EEPROM_FULL_SIZE); in mt7615_eeprom_load()
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/openbmc/qemu/include/hw/nvram/
H A Dnpcm7xx_otp.h2 * Nuvoton NPCM7xx OTP (Fuse Array) Interface
8 * Free Software Foundation; either version 2 of the License, or
22 /* Each OTP module holds 8192 bits of one-time programmable storage */
44 * struct NPCM7xxOTPState - Device state for one OTP module.
48 * @array: OTP storage array.
58 #define TYPE_NPCM7XX_OTP "npcm7xx-otp"
61 #define TYPE_NPCM7XX_KEY_STORAGE "npcm7xx-key-storage"
62 #define TYPE_NPCM7XX_FUSE_ARRAY "npcm7xx-fuse-array"
67 * npcm7xx_otp_array_write - ECC encode and write data to OTP array.
68 * @s: OTP module.
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/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dmtd.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
19 User-defined MTD device name. Can be used to assign user friendly
24 '#address-cells':
27 '#size-cells':
34 - compatible
37 "@[0-9a-f]+$":
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/openbmc/u-boot/board/imgtec/ci20/
H A Dci20.c1 // SPDX-License-Identifier: GPL-2.0+
22 u8 manufacturer[2];
116 /* UART 1 and 2 */ in ci20_mux_uart()
118 jz4780_clk_ungate_uart(2); in ci20_mux_uart()
135 writel(0x100400, gpio_regs + GPIO_PXINTC(2)); in ci20_mux_uart()
136 writel(0x100400, gpio_regs + GPIO_PXMASKC(2)); in ci20_mux_uart()
137 writel(0x100400, gpio_regs + GPIO_PXPAT1S(2)); in ci20_mux_uart()
138 writel(0x100400, gpio_regs + GPIO_PXPAT0C(2)); in ci20_mux_uart()
139 writel(0x100400, gpio_regs + GPIO_PXPENC(2)); in ci20_mux_uart()
156 jz47xx_gpio_direction_output(JZ_GPIO(2, 0), 0); in board_early_init_f()
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/openbmc/linux/drivers/mtd/spi-nor/
H A Dotp.c1 // SPDX-License-Identifier: GPL-2.0
3 * OTP support for SPI NOR flashes
10 #include <linux/mtd/spi-nor.h>
14 #define spi_nor_otp_region_len(nor) ((nor)->params->otp.org->len)
15 #define spi_nor_otp_n_regions(nor) ((nor)->params->otp.org->n_regions)
18 * spi_nor_otp_read_secr() - read security register
27 * an one-time-programmable memory area, consisting of multiple bytes (usually
28 * 256). Thus one "security register" maps to one OTP region.
34 * Return: number of bytes read successfully, -errno otherwise
43 read_opcode = nor->read_opcode; in spi_nor_otp_read_secr()
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H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0 */
97 SPI_MEM_OP_DATA_IN(2, NULL, 0))
103 SPI_MEM_OP_DATA_OUT(2, NULL, 0))
121 SNOR_F_BROKEN_RESET = BIT(2),
195 * struct spi_nor_erase_type - Structure to describe a SPI NOR erase type
197 * JEDEC JESD216B imposes erase sizes to be a power of 2.
198 * @size_shift: @size is a power of 2, the shift is stored in
216 * struct spi_nor_erase_command - Used for non-uniform erases
219 * are run-length encoded.
234 * struct spi_nor_erase_region - Structure to describe a SPI NOR erase region
[all …]
/openbmc/qemu/hw/nvram/
H A Dnpcm7xx_otp.c2 * Nuvoton NPCM7xx OTP (Fuse Array) Interface
8 * Free Software Foundation; either version 2 of the License, or
30 /* 32-bit register indices. */
44 #define FST_RIEN BIT(2)
62 * struct NPCM7xxOTPClass - OTP module class.
66 * The two OTP modules (key-storage and fuse-array) have slightly different
85 result |= (((n >> 2) & 1) ^ ((n >> 3) & 1)) << 5; in ecc_encode_nibble()
86 result |= (((n >> 0) & 1) ^ ((n >> 2) & 1)) << 6; in ecc_encode_nibble()
96 uint8_t *dst = &s->array[offset]; in npcm7xx_otp_array_write()
98 while (len-- > 0) { in npcm7xx_otp_array_write()
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/openbmc/u-boot/arch/arm/mach-stm32mp/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
41 #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
48 * - boot instance = bit 31:16
49 * - boot device = bit 15:0
57 /* BSEC OTP index */
125 /* Freeze IWDG2 if Cortex-A7 is in debug mode */ in dbgmcu_init()
178 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE; in arch_cpu_init()
190 /* Enable D-cache. I-cache is already enabled in start.S */ in enable_caches()
249 int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1; in setup_boot_mode()
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/openbmc/linux/include/linux/mfd/wm831x/
H A Dotp.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * include/linux/mfd/wm831x/otp.h -- OTP interface for WM831x
17 * R30720 (0x7800) - Unique ID 1
19 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
20 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
21 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
24 * R30721 (0x7801) - Unique ID 2
26 #define WM831X_UNIQUE_ID_MASK 0xFFFF /* UNIQUE_ID - [15:0] */
27 #define WM831X_UNIQUE_ID_SHIFT 0 /* UNIQUE_ID - [15:0] */
28 #define WM831X_UNIQUE_ID_WIDTH 16 /* UNIQUE_ID - [15:0] */
[all …]
/openbmc/u-boot/cmd/
H A Dotp.c1 // SPDX-License-Identifier: GPL-2.0+
19 #include <u-boot/sha256.h>
20 #include <u-boot/sha512.h>
21 #include <u-boot/rsa.h>
22 #include <u-boot/rsa-mod-exp.h>
34 #define OTP_REGION_DATA BIT(2)
36 #define OTP_USAGE -1
37 #define OTP_FAILURE -2
43 #define OTP_KEY_TYPE_RSA_PRIV 2
78 #define OTP_A2 2
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H A Dotp_info.h7 #define OTP_REG_RESERVED -1
8 #define OTP_REG_VALUE -2
9 #define OTP_REG_VALID_BIT -3
37 { 2, 1, 0, "Disable Boot from debug SPI" },
38 { 2, 1, 1, "Enable Boot from debug SPI" },
45 { 6, 1, 0, "MAC 2 : RMII/NCSI" },
46 { 6, 1, 1, "MAC 2 : RGMII" },
47 { 7, 2, 0, "CPU Frequency : 1GHz" },
48 { 7, 2, 1, "CPU Frequency : 800MHz" },
49 { 7, 2, 2, "CPU Frequency : 1.2GHz" },
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/openbmc/linux/drivers/mtd/nand/onenand/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
45 bool "OneNAND OTP Support"
48 a One-Time Programmable Block memory area.
49 Also, 1st Block of NAND Flash Array can be used as OTP.
51 The OTP block can be read, programmed and locked using the same
53 OTP block cannot be erased.
55 OTP block is fully-guaranteed to be a valid block.
58 bool "OneNAND 2X program support"
60 The 2X Program is an extension of Program Operation.
61 Since the device is equipped with two DataRAMs, and two-plane NAND
/openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7603/
H A Deeprom.c1 // SPDX-License-Identifier: ISC
21 return -ETIMEDOUT; in mt7603_efuse_read()
23 udelay(2); in mt7603_efuse_read()
51 dev->mt76.otp.data = devm_kzalloc(dev->mt76.dev, len, GFP_KERNEL); in mt7603_efuse_init()
52 dev->mt76.otp.size = len; in mt7603_efuse_init()
53 if (!dev->mt76.otp.data) in mt7603_efuse_init()
54 return -ENOMEM; in mt7603_efuse_init()
56 buf = dev->mt76.otp.data; in mt7603_efuse_init()
104 struct device_node *np = dev->mt76.dev->of_node; in mt7603_apply_cal_free_data()
105 u8 *eeprom = dev->mt76.eeprom.data; in mt7603_apply_cal_free_data()
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/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dpcie.c1 // SPDX-License-Identifier: ISC
52 BRCMF_FW_DEF(43602, "brcmfmac43602-pcie");
53 BRCMF_FW_DEF(4350, "brcmfmac4350-pcie");
54 BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie");
55 BRCMF_FW_CLM_DEF(4355, "brcmfmac4355-pcie");
56 BRCMF_FW_CLM_DEF(4355C1, "brcmfmac4355c1-pcie");
57 BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie");
58 BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie");
59 BRCMF_FW_DEF(4358, "brcmfmac4358-pcie");
60 BRCMF_FW_DEF(4359, "brcmfmac4359-pcie");
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