| /openbmc/qemu/include/gdbstub/ |
| H A D | user.h | 2 * gdbstub user-mode only APIs
6 * SPDX-License-Identifier: LGPL-2.0-or-later
15 * gdb_handlesig() - yield control to gdb
17 * @sig: if non-zero, the signal number which caused us to stop
19 * @siginfo: target-specific siginfo struct
20 * @siginfo_len: target-specific siginfo struct length
22 * This function yields control to gdb, when a user-mode-only target
23 * needs to stop execution. If @sig is non-zero, then we will send a
35 * gdb_signalled() - inform remote gdb of sig exit
42 * gdbserver_fork_start() - inform gdb of the upcoming fork()
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| /openbmc/linux/Documentation/devicetree/bindings/spi/ |
| H A D | spi-fsl-dspi.txt | 4 - compatible : must be one of:
5 "fsl,vf610-dspi",
6 "fsl,ls1021a-v1.0-dspi",
7 "fsl,ls1012a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
8 "fsl,ls1028a-dspi",
9 "fsl,ls1043a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
10 "fsl,ls1046a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
11 "fsl,ls1088a-dspi" (optionally followed by "fsl,ls1021a-v1.0-dspi"),
12 "fsl,ls2080a-dspi" (optionally followed by "fsl,ls2085a-dspi"),
13 "fsl,ls2085a-dspi",
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| H A D | spi-lantiq-ssc.txt | 4 - compatible: "lantiq,ase-spi", "lantiq,falcon-spi", "lantiq,xrx100-spi",
5 "intel,lgm-spi"
6 - #address-cells: see spi-bus.txt
7 - #size-cells: see spi-bus.txt
8 - reg: address and length of the spi master registers
9 - interrupts:
10 For compatible "intel,lgm-ssc" - the common interrupt number for
18 - clocks: spi clock phandle
19 - num-cs: see spi-bus.txt, set to 8 if unset
20 - base-cs: the number of the first chip select, set to 1 if unset.
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| H A D | spi-cadence.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-cadence.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Michal Simek <michal.simek@amd.com>
13 - $ref: spi-controller.yaml#
18 - cdns,spi-r1p6
19 - xlnx,zynq-spi-r1p6
27 clock-names:
29 - const: ref_clk
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| H A D | spi-gpio.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI-GPIO
10 - Rob Herring <robh@kernel.org>
13 This represents a group of 3-n GPIO lines used for bit-banged SPI on
17 - $ref: /schemas/spi/spi-controller.yaml#
21 const: spi-gpio
23 sck-gpios:
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| H A D | spi-davinci.txt | 4 Keystone 2 - https://www.ti.com/lit/ug/sprugp2a/sprugp2a.pdf
5 dm644x - https://www.ti.com/lit/ug/sprue32a/sprue32a.pdf
6 OMAP-L138/da830 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
9 - #address-cells: number of cells required to define a chip select
11 - #size-cells: should be zero.
12 - compatible:
13 - "ti,dm6441-spi" for SPI used similar to that on DM644x SoC family
14 - "ti,da830-spi" for SPI used similar to that on DA8xx SoC family
15 - "ti,keystone-spi" for SPI used similar to that on Keystone2 SoC
17 - reg: Offset and length of SPI controller register space
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| H A D | spi-armada-3700.txt | 5 - compatible: should be "marvell,armada-3700-spi"
6 - reg: physical base address of the controller and length of memory mapped
8 - interrupts: The interrupt number. The interrupt specifier format depends on
10 - clocks: Must contain the clock source, usually from the North Bridge clocks.
11 - num-cs: The number of chip selects that is supported by this SPI Controller
12 - #address-cells: should be 1.
13 - #size-cells: should be 0.
18 compatible = "marvell,armada-3700-spi";
19 #address-cells = <1>;
20 #size-cells = <0>;
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| H A D | spi-fsl-lpspi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-fsl-lpspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Anson Huang <Anson.Huang@nxp.com>
13 - $ref: /schemas/spi/spi-controller.yaml#
18 - enum:
19 - fsl,imx7ulp-spi
20 - fsl,imx8qxp-spi
21 - items:
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| H A D | fsl-spi.txt | 4 - cell-index : QE SPI subblock index.
7 - compatible : should be "fsl,spi" or "aeroflexgaisler,spictrl".
8 - mode : the SPI operation mode, it can be "cpu" or "cpu-qe".
9 - reg : Offset and length of the register set for the device
10 - interrupts : <a b> where a is the interrupt number and b is a
15 - clock-frequency : input clock frequency to non FSL_SOC cores
18 - cs-gpios : specifies the gpio pins to be used for chipselects.
21 - fsl,spisel_boot : for the MPC8306 and MPC8309, specifies that the
24 the cs-gpios property is not present.
28 cell-index = <0>;
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| H A D | samsung,spi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
19 - enum:
20 - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450
21 - samsung,s3c6410-spi
22 - samsung,s5pv210-spi # for S5PV210 and S5PC110
23 - samsung,exynos4210-spi
24 - samsung,exynos5433-spi
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| H A D | socionext,f-ospi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/socionext,f-ospi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
17 - $ref: spi-controller.yaml#
21 const: socionext,f-ospi
29 num-cs:
34 - compatible
35 - reg
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| /openbmc/qemu/target/m68k/ |
| H A D | op_helper.c | 22 #include "exec/helper-proto.h"
23 #include "exec/exec-all.h"
34 sp = env->aregs[7]; in cf_rte()
36 env->pc = cpu_ldl_mmuidx_ra(env, sp + 4, MMU_KERNEL_IDX, 0); in cf_rte()
38 env->aregs[7] = sp + 8; in cf_rte()
49 sp = env->aregs[7]; in m68k_rte()
53 env->pc = cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0); in m68k_rte()
63 env->aregs[7] = sp; in m68k_rte()
78 env->aregs[7] = sp; in m68k_rte()
102 return "A-Line"; in m68k_exception_name()
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | ti,gpmc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
11 - Roger Quadros <rogerq@kernel.org>
16 - Asynchronous SRAM-like memories and ASICs
17 - Asynchronous, synchronous, and page mode burst NOR flash
18 - NAND flash
19 - Pseudo-SRAM devices
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| /openbmc/qemu/include/hw/xen/interface/arch-x86/ |
| H A D | xen-x86_64.h | 1 /* SPDX-License-Identifier: MIT */
3 * xen-x86_64.h
5 * Guest OS interface to x86 64-bit Xen.
7 * Copyright (c) 2004-2006, K A Fraser
15 * Input: %rdi, %rsi, %rdx, %r10, %r8, %r9 (arguments 1-6)
18 * call hypercall_page + hypercall-number * 32
19 * Clobbered: argument registers (e.g., 2-arg hypercall clobbers %rdi,%rsi)
23 * 64-bit segment selectors
24 * These flat segments are in the Xen-private section of every GDT. Since these
68 #define MACH2PHYS_NR_ENTRIES ((MACH2PHYS_VIRT_END-MACH2PHYS_VIRT_START)>>3)
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| /openbmc/linux/drivers/net/ethernet/pasemi/ |
| H A D | pasemi_mac.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Driver for the PA6T-1682M onchip 1G/10G Ethernet MACs, soft state and
78 struct pasemi_mac_csring *cs[MAX_CS]; member
94 #define TX_DESC(tx, num) ((tx)->chan.ring_virt[(num) & (TX_RING_SIZE-1)]) argument
95 #define TX_DESC_INFO(tx, num) ((tx)->ring_info[(num) & (TX_RING_SIZE-1)]) argument
96 #define RX_DESC(rx, num) ((rx)->chan.ring_virt[(num) & (RX_RING_SIZE-1)]) argument
97 #define RX_DESC_INFO(rx, num) ((rx)->ring_info[(num) & (RX_RING_SIZE-1)]) argument
98 #define RX_BUFF(rx, num) ((rx)->buffers[(num) & (RX_RING_SIZE-1)]) argument
99 #define CS_DESC(cs, num) ((cs)->chan.ring_virt[(num) & (CS_RING_SIZE-1)]) argument
101 #define RING_USED(ring) (((ring)->next_to_fill - (ring)->next_to_clean) \
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| /openbmc/u-boot/doc/device-tree-bindings/spi/ |
| H A D | spi-zynq.txt | 2 -------------------------------------------
5 - compatible : Should be "cdns,spi-r1p6" or "xlnx,zynq-spi-r1p6".
6 - reg : Physical base address and size of SPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - interrupt-parent : Must be core interrupt controller
10 - clock-names : List of input clock names - "ref_clk", "pclk"
12 - clocks : Clock phandles (see clock bindings for details).
13 - spi-max-frequency : Maximum SPI clocking speed of device in Hz
16 - num-cs : Number of chip selects used.
19 - is-decoded-cs : Flag to indicate whether decoder is used or not.
[all …]
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| H A D | spi-zynq-qspi.txt | 2 -------------------------------------------------
5 - compatible : Should be "xlnx,zynq-qspi-1.0".
6 - reg : Physical base address and size of QSPI registers map.
7 - interrupts : Property with a value describing the interrupt
9 - interrupt-parent : Must be core interrupt controller
10 - clock-names : List of input clock names - "ref_clk", "pclk"
12 - clocks : Clock phandles (see clock bindings for details).
15 - num-cs : Number of chip selects used.
19 compatible = "xlnx,zynq-qspi-1.0";
20 clock-names = "ref_clk", "pclk";
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| /openbmc/linux/fs/fuse/ |
| H A D | dev.c | 3 Copyright (C) 2001-2008 Miklos Szeredi <miklos@szeredi.hu>
37 * Lockless access is OK, because file->private data is set in fuse_get_dev()
40 return READ_ONCE(file->private_data); in fuse_get_dev()
45 INIT_LIST_HEAD(&req->list); in fuse_request_init()
46 INIT_LIST_HEAD(&req->intr_entry); in fuse_request_init()
47 init_waitqueue_head(&req->waitq); in fuse_request_init()
48 refcount_set(&req->count, 1); in fuse_request_init()
49 __set_bit(FR_PENDING, &req->flags); in fuse_request_init()
50 req->fm = fm; in fuse_request_init()
69 refcount_inc(&req->count); in __fuse_get_request()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | keystone-k2g.dtsi | 11 #include <dt-bindings/interrupt-controller/arm-gic.h>
15 #address-cells = <1>;
16 #size-cells = <1>;
17 interrupt-parent = <&gic>;
34 #address-cells = <1>;
35 #size-cells = <0>;
37 interrupt-parent = <&gic>;
40 compatible = "arm,cortex-a15";
46 gic: interrupt-controller {
47 compatible = "arm,cortex-a15-gic";
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| H A D | keystone-k2l.dtsi | 13 #address-cells = <1>;
14 #size-cells = <0>;
16 interrupt-parent = <&gic>;
19 compatible = "arm,cortex-a15";
25 compatible = "arm,cortex-a15";
32 /include/ "keystone-k2l-clocks.dtsi"
36 current-speed = <115200>;
37 reg-shift = <2>;
38 reg-io-width = <4>;
46 current-speed = <115200>;
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| /openbmc/qemu/gdbstub/ |
| H A D | user.c | 2 * gdbstub user-mode helper routines.
4 * We know for user-mode we are using TCG so we can call stuff directly.
6 * Copyright (c) 2003-2005 Fabrice Bellard
9 * SPDX-License-Identifier: LGPL-2.0-or-later
17 #include "exec/tb-flush.h"
32 * follow-fork-mode. This happens inside a start_exclusive() section, so that
35 * either from the parent (follow-fork-mode child) or from the child
36 * (follow-fork-mode parent).
48 * ACTIVE -> DEACTIVATING: On $Hg.
49 * ACTIVE -> ENABLING : On $D.
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| /openbmc/linux/drivers/i2c/busses/ |
| H A D | i2c-synquacer.c | 1 // SPDX-License-Identifier: GPL-2.0
31 #define SYNQUACER_I2C_REG_CSR (0x05 << 2) // Expansion CS
70 DIV_ROUND_UP(DIV_ROUND_UP((rate), I2C_MAX_STANDARD_MODE_FREQ) - 2, 2)
73 DIV_ROUND_UP((DIV_ROUND_UP((rate), I2C_MAX_FAST_MODE_FREQ) - 2) * 2, 3)
76 /* calculate the value of CS bits in CCR register on standard mode */
78 ((SYNQUACER_I2C_CLK_MASTER_STD(rate) - 65) \
81 /* calculate the value of CS bits in CSR register on standard mode */
84 /* calculate the value of CS bits in CCR register on fast mode */
86 ((SYNQUACER_I2C_CLK_MASTER_FAST(rate) - 1) \
89 /* calculate the value of CS bits in CSR register on fast mode */
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| /openbmc/linux/arch/riscv/boot/dts/canaan/ |
| H A D | canaan_kd233.dts | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
7 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
16 compatible = "canaan,kendryte-kd233", "canaan,kendryte-k210";
20 stdout-path = "serial0:115200n8";
23 gpio-leds {
24 compatible = "gpio-leds";
35 gpio-keys {
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| /openbmc/qemu/hw/ssi/ |
| H A D | xilinx_spips.c | 29 #include "hw/qdev-properties.h"
59 #define CS (0xF << 10) macro
89 #define IXR_ALL ((1 << 13) - 1)
218 return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && in num_effective_busses()
219 s->regs[R_LQSPI_CFG] & LQSPI_CFG_TWO_MEM) ? s->num_busses : 1; in num_effective_busses()
226 for (i = 0; i < s->num_cs * s->num_busses; i++) { in xilinx_spips_update_cs()
227 bool old_state = s->cs_lines_state[i]; in xilinx_spips_update_cs()
231 s->cs_lines_state[i] = new_state; in xilinx_spips_update_cs()
232 s->rx_discard = ARRAY_FIELD_EX32(s->regs, CMND, RX_DISCARD); in xilinx_spips_update_cs()
236 qemu_set_irq(s->cs_lines[i], !new_state); in xilinx_spips_update_cs()
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| /openbmc/linux/arch/arm64/boot/dts/toshiba/ |
| H A D | tmpv7708.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * (C) Copyright 2018 - 2020, Toshiba Corporation.
10 #include <dt-bindings/clock/toshiba,tmpv770x.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 /memreserve/ 0x81000000 0x00300000; /* cpu-release-addr */
18 #address-cells = <2>;
19 #size-cells = <2>;
22 #address-cells = <1>;
23 #size-cells = <0>;
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