| /openbmc/u-boot/drivers/mtd/spi/ |
| H A D | spi-nor-core.c | 20 #include <linux/mtd/spi-nor.h>
39 * @nor: pointer to a 'struct spi_nor'
44 void spi_nor_setup_op(const struct spi_nor *nor, in spi_nor_setup_op() argument
60 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op in spi_nor_read_write_reg() argument
67 return spi_mem_exec_op(nor->spi, op); in spi_nor_read_write_reg()
70 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) in spi_nor_read_reg() argument
78 ret = spi_nor_read_write_reg(nor, &op, val); in spi_nor_read_reg()
86 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) in spi_nor_write_reg() argument
93 return spi_nor_read_write_reg(nor, &op, buf); in spi_nor_write_reg()
97 static int spansion_read_any_reg(struct spi_nor *nor, u32 addr, u8 dummy, in spansion_read_any_reg() argument
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| H A D | spi-nor-tiny.c | 20 #include <linux/mtd/spi-nor.h>
37 static int spi_nor_read_write_reg(struct spi_nor *nor, struct spi_mem_op in spi_nor_read_write_reg() argument
44 return spi_mem_exec_op(nor->spi, op); in spi_nor_read_write_reg()
47 static int spi_nor_read_reg(struct spi_nor *nor, u8 code, u8 *val, int len) in spi_nor_read_reg() argument
55 ret = spi_nor_read_write_reg(nor, &op, val); in spi_nor_read_reg()
63 static int spi_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len) in spi_nor_write_reg() argument
70 return spi_nor_read_write_reg(nor, &op, buf); in spi_nor_write_reg()
73 static ssize_t spi_nor_read_data(struct spi_nor *nor, loff_t from, size_t len, in spi_nor_read_data() argument
77 SPI_MEM_OP(SPI_MEM_OP_CMD(nor->read_opcode, 1), in spi_nor_read_data()
78 SPI_MEM_OP_ADDR(nor->addr_width, from, 1), in spi_nor_read_data()
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| H A D | Makefile | 7 spi-nor-y := sf_probe.o spi-nor-ids.o
12 spi-nor-y += spi-nor-tiny.o
14 spi-nor-y += spi-nor-core.o
17 spi-nor-y += spi-nor-core.o
20 obj-$(CONFIG_SPI_FLASH) += spi-nor.o
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| /openbmc/u-boot/configs/ |
| H A D | mccmon6_sd_defconfig | 27 CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor"
28 …nor:32m@0x0(mccmon6-image.nor),256k@0x40000(u-boot-env.nor),1m@0x80000(u-boot.nor),8m@0x180000(ker…
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| H A D | mccmon6_nor_defconfig | 26 CONFIG_MTDIDS_DEFAULT="nor0=8000000.nor"
27 …nor:32m@0x0(mccmon6-image.nor),256k@0x40000(u-boot-env.nor),1m@0x80000(u-boot.nor),8m@0x180000(ker…
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| /openbmc/u-boot/drivers/spi/ |
| H A D | Kconfig | 32 access the SPI NOR flash on platforms embedding this Altera
41 used to access the SPI NOR flash on boards using the Aspeed
63 to access SPI NOR flash and other SPI peripherals. This driver
80 access the SPI NOR flash on platforms embedding this Broadcom
88 access the SPI NOR flash on platforms embedding these Broadcom
102 used to access the SPI NOR flash on platforms embedding this
109 access the SPI NOR flash on platforms embedding this Designware
116 access the SPI NOR flash on platforms embedding this Samsung
123 access the SPI NOR flash and SPI Data flash on platforms embedding
132 access the SPI NOR flash on platforms embedding this Intel
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| /openbmc/u-boot/include/linux/mtd/ |
| H A D | spi-nor.h | 269 * struct spi_nor - Structure for defining a the SPI NOR layer
272 * @dev: point to a spi device, or a spi nor controller device.
273 * @info: spi-nor part JDEC MFR id and other info
274 * @page_size: the page size of the SPI NOR
284 * @flags: flag options for the current SPI-NOR (SNOR_F_*)
295 * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
296 * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
297 * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
299 * spi-nor will send the erase opcode via write_reg()
300 * @flash_lock: [FLASH-SPECIFIC] lock a region of the SPI NOR
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| /openbmc/u-boot/board/freescale/mx35pdk/ |
| H A D | README | 43 and for NOR:
54 0x00080000-0x00480000 : "nor.Kernel"
55 0x00480000-0x02280000 : "nor.userfs"
56 0x02280000-0x03e80000 : "nor.rootfs"
74 U-Boot should be stored on the NOR flash.
82 Saving U-Boot in the NOR flash
85 Check the partition for boot in the NOR flash. Setting the mtdparts as reported,
90 0x00080000-0x00480000 : "nor.Kernel"
91 0x00480000-0x02280000 : "nor.userfs"
92 0x02280000-0x03e80000 : "nor.rootfs"
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| /openbmc/u-boot/board/ti/am335x/ |
| H A D | Kconfig | 15 config NOR config
16 bool "Support for NOR flash"
18 The AM335x SoC supports having a NOR flash connected to the GPMC.
19 In practice this is seen as a NOR flash module connected to the
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| /openbmc/openbmc/meta-ampere/meta-jefferson/recipes-ampere/platform/ampere-utils/ |
| H A D | ampere_flash_bios.sh | 8 # $device_sellect : 1 - Host Main SPI Nor
9 # 2 - Host Second SPI Nor
17 # BMC_GPIOW7_SPI0_BACKUP_SEL (GPIO 183) : 0 => to switch SPI0_CS0_FL1_L to secondary SPI Nor d…
18 # 1 => to switch SPI0_CS0_FL0_L to primary SPI Nor dev…
37 echo "Fail to probe the Host SPI-NOR device"
94 echo "Run update Primary Host SPI-NOR"
97 echo "Run update Second Host SPI-NOR"
108 echo "Switch to the Primary Host SPI-NOR"
110 echo "ERROR: Switch to the Primary Host SPI-NOR. Please check gpio state"
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| /openbmc/openbmc/meta-ampere/meta-mitchell/recipes-ampere/platform/ampere-utils/ |
| H A D | ampere_flash_bios.sh | 8 # $device_sellect : 1 - Host Main SPI Nor
9 # 2 - Host Second SPI Nor
17 # BMC_GPIOW7_SPI0_BACKUP_SEL (GPIO 183) : 1 => to switch SPI_CS0_L to primary SPI Nor device
18 # 0 => to switch SPI_CS0_L to second SPI Nor device
38 echo "Fail to probe the Host SPI-NOR device"
100 echo "Run update Primary Host SPI-NOR"
103 echo "Run update Secondary Host SPI-NOR"
110 # Restrict to flash Secondary Host SPI-NOR in case of SPECIAL_BOOT
112 echo "Flashing 2nd Host SPI NOR image with SECProv image is not allowed"
129 echo "Switch to the Primary Host SPI-NOR"
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| /openbmc/u-boot/arch/arm/cpu/arm926ejs/orion5x/ |
| H A D | u-boot-spl.lds | 19 MEMORY { .nor : ORIGIN = IMAGE_TEXT_BASE,\
35 } > .nor
38 .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.nor
41 .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.nor
46 } > .nor
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| /openbmc/u-boot/board/freescale/c29xpcie/ |
| H A D | README | 13 - 64 Mbyte NOR flash single-chip memory
35 0xf_ec00_0000 - 0xf_efff_ffff 64MB NOR flash
52 SW5[1:4]= 1111 and SW5[6]=0 for boot from 16bit NOR flash
56 Build and program U-Boot to NOR flash
63 2. Program u-boot.bin into NOR flash
71 Alternate NOR bank
74 1. Program u-boot.bin into alternate NOR bank
80 2. Switch to alternate NOR bank
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| /openbmc/u-boot/doc/ |
| H A D | README.spear | 19 6. Serial NOR ctrl
30 4. EMI (Parallel NOR interface)
37 location i.e. Serial NOR device
40 for CFI compliant parallel NOR flash. Environment variables are
41 placed in Parallel NOR device
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| /openbmc/u-boot/board/boundary/nitrogen6x/ |
| H A D | README.mx6qsabrelite | 20 The SabreLite boards boot from the SPI NOR flash. These boards need their SPI
22 board will still boot from SPI NOR, but the loader will in turn request the
31 To following procedure can be used to update the SPI-NOR on the SabreLite
47 (the default one the board is shipped with, starting from the SPI NOR) and
74 3. Boot from SPI NOR
77 The SabreLite board can also boot U-Boot directly from the SPI NOR flash:
94 4. Recovering SPI-NOR
116 5. Use one of previous descriptions to re-flash the SPI-NOR as required.
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| /openbmc/u-boot/board/Arcturus/ucp1020/ |
| H A D | README | 3 DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
15 SPI Flash or NOR flash
19 NOR boot image:
47 NOR Flash Partition declarations and scripts
50 into defined NOR flash partitions. Examples:
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| /openbmc/openbmc/poky/meta/files/common-licenses/ |
| H A D | TU-Berlin-2.0 | 4 …thors nor the Technische Universitaet Berlin are deemed to have made any representations as to the…
16 …thors nor the Technische Universitaet Berlin are deemed to have made any representations as to the…
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| /openbmc/u-boot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PA | 15 - 32 Mbyte NOR flash single-chip memory
62 0xee00_0000 0xefff_ffff NOR Flash 32M non-cacheable
82 SW4[1:4]= 1111 and SW6[4]=0 for boot from 16bit NOR flash
98 Build and burn U-Boot to NOR flash
105 2. Burn u-boot.bin into NOR flash
114 Alternate NOR bank
116 1. Burn u-boot.bin into alternate NOR bank
122 2. Switch to alternate NOR bank
129 CPLD NOR bank selection register address 0xFFB00009 Bit[0]:
173 If change boot ROM location to NOR or NAND flash, need write the IFC_CS0
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| /openbmc/u-boot/board/freescale/mpc8313erdb/ |
| H A D | README | 8 To boot the image at 0xFE000000 in NOR flash, use these DIP
42 0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
44 When booting from NAND, NAND flash is CS0 and NOR flash
65 33 - 33 MHz oscillator, boot from NOR flash
66 66 - 66 MHz oscillator, boot from NOR flash
75 NOR flash:
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| /openbmc/u-boot/arch/arm/include/asm/arch-mxs/ |
| H A D | sys_proto.h | 41 { 0x02, 0x1f, "SSP SPI #1, master, NOR" },
42 { 0x03, 0x1f, "SSP SPI #2, master, NOR" },
53 { 0x02, 0x1f, "SSP SPI #2, master, 3V3 NOR" },
54 { 0x12, 0x1f, "SSP SPI #2, master, 1V8 NOR" },
55 { 0x03, 0x1f, "SSP SPI #3, master, 3V3 NOR" },
56 { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" },
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| /openbmc/u-boot/common/spl/ |
| H A D | spl_nor.c | 30 * the mkimage header in this SPL NOR driver in spl_nor_load_image()
37 * Load Linux from its location in NOR flash to its defined in spl_nor_load_image()
72 "Please check your NOR configuration.\n" in spl_nor_load_image()
79 * Load real U-Boot from its location in NOR flash to its in spl_nor_load_image()
106 SPL_LOAD_IMAGE_METHOD("NOR", 0, BOOT_DEVICE_NOR, spl_nor_load_image);
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| /openbmc/u-boot/drivers/ram/ |
| H A D | stm32_sdram.c | 20 u32 bcr1; /* NOR/PSRAM Chip select control register 1 */
21 u32 btr1; /* SRAM/NOR-Flash Chip select timing register 1 */
22 u32 bcr2; /* NOR/PSRAM Chip select Control register 2 */
23 u32 btr2; /* SRAM/NOR-Flash Chip select timing register 2 */
24 u32 bcr3; /* NOR/PSRAMChip select Control register 3 */
25 u32 btr3; /* SRAM/NOR-Flash Chip select timing register 3 */
26 u32 bcr4; /* NOR/PSRAM Chip select Control register 4 */
27 u32 btr4; /* SRAM/NOR-Flash Chip select timing register 4 */
40 u32 bwtr1; /* SRAM/NOR-Flash write timing register 1 */
42 u32 bwtr2; /* SRAM/NOR-Flash write timing register 2 */
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| /openbmc/u-boot/board/freescale/p1_p2_rdb_pc/ |
| H A D | README | 18 * NOR flash
41 pins multiplexing. QE function needs to be disabled to access Nor Flash and
46 'setenv hwconfig qe' to enable QE UEC/UART and disable Nor-Flash/CPLD.
47 'setenv hwconfig 'qe;tdm'' to enalbe QE TDM and disable Nor-Flash/CPLD.
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| /openbmc/u-boot/include/configs/ |
| H A D | mccmon6.h | 57 /* NOR 16-bit mode */
63 /* NOR Flash MTD */
92 "setenv boot_medium nor;" \
171 "nor_img_file=core-image-lwn-mccmon6.nor\0" \
204 "echo 'Update mccmon6 NOR image'; " \
215 "echo 'Update mccmon6 NOR U-BOOT via TFTP'; " \
223 "echo 'Update mccmon6 NOR uImage via TFTP'; " \
231 "echo 'Update mccmon6 NOR DTB via TFTP'; " \
239 "echo 'Update mccmon6 NOR image via TFTP'; " \
280 /* Envs are stored in NOR flash */
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| /openbmc/openbmc/meta-fii/meta-mori/recipes-bsp/u-boot/u-boot-fw-utils-nuvoton/ |
| H A D | fw_env.config | 4 # Notice, that the "Number of sectors" is not required on NOR and SPI-dataflash.
6 # be the same as the Environment size, which is valid for NOR and SPI-dataflash
8 # NOR example
|