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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dsunxi_nand.c1 // SPDX-License-Identifier: GPL-2.0+
7 * https://github.com/yuq/sunxi-nfc-mtd
10 * https://github.com/hno/Allwinner-Info
30 #include <nand.h>
78 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
114 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
171 * @RB_NATIVE: use sunxi NAND controller Ready/Busy support. The Ready/Busy
172 * pin of the NAND flash chip must be connected to one of the
173 * native NAND R/B pins (those which can be muxed to the NAND
176 * pin of the NAND flash chip must be connected to a GPIO capable
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H A Dkb9202_nand.c1 // SPDX-License-Identifier: GPL-2.0+
15 #include <nand.h>
18 * hardware specific access to control-lines
25 #define KB9202_NAND_BUSY (1 << 29) /* RB* on D29 */
33 * Board-specific function to access device control signals
40 ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; in kb9202_nand_hwcontrol()
51 this->IO_ADDR_W = (void *) IO_ADDR_W; in kb9202_nand_hwcontrol()
60 writeb(cmd, this->IO_ADDR_W); in kb9202_nand_hwcontrol()
65 * Board-specific function to access the device ready signal.
74 * Board-specific NAND init. Copied from include/linux/mtd/nand.h for reference.
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H A Dvf610_nfc.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
5 * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
6 * Ported to U-Boot by Stefan Agner
17 * - Untested on MPC5125 and M54418.
18 * - DMA and pipelining not used.
19 * - 2K pages or less.
20 * - HW ECC: Only 2K page with 64+ OOB.
21 * - HW ECC: Only 24 and 32-bit error correction implemented.
31 #include <nand.h>
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/openbmc/u-boot/arch/arm/dts/
H A Dsun8i-r16-nintendo-nes-classic-edition.dts4 * This file is dual-licensed: you can use it either under the terms
43 /dts-v1/;
44 #include "sun8i-a33.dtsi"
48 compatible = "nintendo,nes-classic-edition", "allwinner,sun8i-a33";
55 stdout-path = "serial0:115200n8";
60 pinctrl-names = "default";
61 pinctrl-0 = <&uart0_pins_a>;
68 nand@0 {
69 #address-cells = <1>;
70 #size-cells = <1>;
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H A Dam335x-chilisom.dtsi2 * Copyright (C) 2015 Jablotron s.r.o. -- http://www.jablotron.com/
10 #include <dt-bindings/interrupt-controller/irq.h>
14 compatible = "grinn,am335x-chilisom", "ti,am33xx";
18 cpu0-supply = <&dcdc2_reg>;
29 pinctrl-names = "default";
32 pinctrl-single,pins = <
39 pinctrl-single,pins = <
60 pinctrl-names = "default";
61 pinctrl-0 = <&i2c0_pins>;
64 clock-frequency = <400000>;
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H A Dlogicpd-torpedo-som.dtsi7 #include <dt-bindings/input/input.h>
11 stdout-path = &uart1;
16 cpu0-supply = <&vcc>;
26 compatible = "gpio-leds";
30 linux,default-trigger = "none";
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <26000000>;
43 ranges = <0 0 0x30000000 0x1000000>; /* CS0: 16MB for NAND */
45 nand@0,0 {
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H A Dam335x-brppt1-nand.dts1 // SPDX-License-Identifier: GPL-2.0+
4 * http://www.br-automation.com
7 /dts-v1/;
12 model = "BRPPT1 (NAND) Panel";
15 fset: factory-settings {
16 bl-version = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
18 order-no = "6PPT30 (NAND)";
19 hw-revision = "ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456890";
20 serial-no = "0";
21 device-id = <0x0>;
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H A Dam335x-igep0033.dtsi2 * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x
4 * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
11 /dts-v1/;
14 #include <dt-bindings/interrupt-controller/irq.h>
19 cpu0-supply = <&vdd1_reg>;
29 pinctrl-names = "default";
30 pinctrl-0 = <&leds_pins>;
32 compatible = "gpio-leds";
37 default-state = "on";
42 compatible = "regulator-fixed";
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H A Ddra7-evm.dts2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
11 #include "dra7-evm-common.dtsi"
12 #include "dra74x-mmc-iodelay.dtsi"
16 compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
23 evm_1v8_sw: fixedregulator-evm_1v8 {
24 compatible = "regulator-fixed";
25 regulator-name = "evm_1v8";
26 vin-supply = <&smps9_reg>;
27 regulator-min-microvolt = <1800000>;
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H A Dlogicpd-som-lv.dtsi7 #include <dt-bindings/input/input.h>
12 cpu0-supply = <&vcc>;
22 compatible = "regulator-fixed";
23 regulator-name = "vwl1271";
24 regulator-min-microvolt = <1800000>;
25 regulator-max-microvolt = <1800000>;
27 startup-delay-us = <70000>;
28 enable-active-high;
29 vin-supply = <&vaux3>;
34 compatible = "usb-nop-xceiv";
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H A Ddra72-evm-common.dtsi2 * Copyright (C) 2014-2016 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/clk/ti-dra7-atl.h>
15 compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
22 stdout-path = &uart1;
25 evm_12v0: fixedregulator-evm12v0 {
27 compatible = "regulator-fixed";
28 regulator-name = "evm_12v0";
29 regulator-min-microvolt = <12000000>;
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H A Dsun5i-gr8-chip-pro.dts5 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 * This file is dual-licensed: you can use it either under the terms
46 /dts-v1/;
47 #include "sun5i-gr8.dtsi"
48 #include "sunxi-common-regulators.dtsi"
50 #include <dt-bindings/gpio/gpio.h>
51 #include <dt-bindings/input/input.h>
52 #include <dt-bindings/interrupt-controller/irq.h>
56 compatible = "nextthing,chip-pro", "nextthing,gr8";
67 stdout-path = "serial0:115200n8";
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H A Domap3-beagle.dts2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
8 /dts-v1/;
14 compatible = "ti,omap3-beagle", "ti,omap3";
18 cpu0-supply = <&vcc>;
33 compatible = "gpio-leds";
41 gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; /* 150 -> D6 LED */
42 linux,default-trigger = "heartbeat";
47 gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; /* 149 -> D7 LED */
48 linux,default-trigger = "mmc0";
54 compatible = "regulator-fixed";
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H A Darmada-38x.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 * Gregory CLEMENT <gregory.clement@free-electrons.com>
9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/interrupt-controller/irq.h>
30 compatible = "arm,cortex-a9-pmu";
31 interrupts-extended = <&mpic 3>;
35 compatible = "marvell,armada380-mbus", "simple-bus";
36 u-boot,dm-pre-reloc;
37 #address-cells = <2>;
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H A Dsun5i.dtsi2 * Copyright 2012-2015 Maxime Ripard
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
6 * This file is dual-licensed: you can use it either under the terms
47 #include <dt-bindings/clock/sun5i-ccu.h>
48 #include <dt-bindings/dma/sun4i-a10.h>
49 #include <dt-bindings/reset/sun5i-ccu.h>
52 interrupt-parent = <&intc>;
55 #address-cells = <1>;
56 #size-cells = <0>;
60 compatible = "arm,cortex-a8";
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/openbmc/u-boot/drivers/mtd/ubi/
H A Dubi.h1 /* SPDX-License-Identifier: GPL-2.0+ */
34 #include "ubi-media.h"
35 #include <mtd/ubi-user.h>
48 ubi->ubi_num, ##__VA_ARGS__)
53 ubi->ubi_num, __func__, ##__VA_ARGS__)
56 ubi->ubi_num, __func__, ##__VA_ARGS__)
62 * This marker in the EBA table means that the LEB is um-mapped.
65 #define UBI_LEB_UNMAPPED -1
69 * returning error. The below constant defines how many times UBI re-tries.
75 * number of (global) erase cycles PEBs are protected from the wear-leveling
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H A Dattach.c1 // SPDX-License-Identifier: GPL-2.0+
9 * UBI attaching sub-system.
11 * This sub-system is responsible for attaching MTD devices and it also
16 * objects which are kept in volume RB-tree with root at the @volumes field.
17 * The RB-tree is indexed by the volume ID.
20 * objects are kept in per-volume RB-trees with the root at the corresponding
21 * &struct ubi_ainf_volume object. To put it differently, we keep an RB-tree of
22 * per-volume objects and each of these objects is the root of RB-tree of
23 * per-LEB objects.
32 * UBI protects EC and VID headers with CRC-32 checksums, so it can detect
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/openbmc/qemu/target/ppc/translate/
H A Dfixedpoint-impl.c.inc2 * Power ISA decode for Fixed-Point Facility instructions
21 * Fixed-Point Load/Store Instructions
36 mop ^= ctx->default_tcg_memop_mask;
38 tcg_gen_qemu_st_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
40 tcg_gen_qemu_ld_tl(cpu_gpr[rt], ea, ctx->mem_idx, mop);
51 return do_ldst(ctx, a->rt, a->ra, tcg_constant_tl(a->si), update, store, mop);
67 return do_ldst(ctx, a->rt, a->ra, cpu_gpr[a->rb], update, store, mop);
79 if (!prefixed && !(ctx->insns_flags2 & PPC2_LSQ_ISA207)) {
83 if (ctx->le_mode) {
89 if (!store && unlikely(a->ra == a->rt)) {
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H A Dvsx-impl.c.inc45 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
47 set_cpu_vsr(a->rt, t0, true);
69 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
71 set_cpu_vsr(a->rt, t0, true);
74 set_cpu_vsr(a->rt, t0, false);
89 EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
90 if (ctx->le_mode) {
94 tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEUQ);
98 tcg_gen_qemu_ld_i64(t0, EA, ctx->mem_idx, MO_LEUQ);
102 tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEUQ);
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/openbmc/u-boot/post/lib_powerpc/
H A Dthreex.c1 // SPDX-License-Identifier: GPL-2.0+
11 * Ternary instructions instr rA,rS,rB
13 * Logic instructions: or, orc, xor, nand, nor, eqv
16 * The test contains a pre-built table of instructions, operands and
131 ASM_STW(stk, 1, -4), in cpu_post_test_threex()
132 ASM_ADDI(stk, 1, -24), in cpu_post_test_threex()
140 ASM_12X(test->cmd, reg2, reg1, reg0), in cpu_post_test_threex()
147 ASM_LWZ(stk, 1, -4), in cpu_post_test_threex()
152 ASM_STW(stk, 1, -4), in cpu_post_test_threex()
153 ASM_ADDI(stk, 1, -24), in cpu_post_test_threex()
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/openbmc/qemu/target/ppc/
H A Dinsn32.decode2 # Power ISA decode for 32-bit insns (opcode space 0)
32 &A_tab_bc rt ra rb bc
33 @A_tab_bc ...... rt:5 ra:5 rb:5 bc:5 ..... . &A_tab_bc
99 &X rt ra rb
100 @X ...... rt:5 ra:5 rb:5 .......... . &X
102 &X_rc rt ra rb rc:bool
103 @X_rc ...... rt:5 ra:5 rb:5 .......... rc:1 &X_rc
114 @X_tp_ap_bp_rc ...... ....0 ....0 ....0 .......... rc:1 &X_rc rt=%x_frtp ra=%x_frap rb=%x_f…
116 @X_tp_a_bp_rc ...... ....0 ra:5 ....0 .......... rc:1 &X_rc rt=%x_frtp rb=%x_frbp
121 &X_tb rt rb
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/openbmc/qemu/tcg/ppc/
H A Dtcg-target.c.inc30 * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV or _CALL_AIX.
70 calling convention, we can re-use the TOC register since we'll be reloading
71 it at every call. Otherwise R12 will do nicely as neither a call-saved
145 TCG_REG_R12, /* call clobbered, non-arguments */
158 /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */
224 return tcg_tbrel_diff(s, target) - 4;
346 if ((ct & TCG_CT_CONST_N16) && -sval == (int16_t)-sval) {
358 if ((ct & TCG_CT_CONST_MONE) && sval == -1) {
491 #define NAND XO31(476)
686 #define RB(r) ((r)<<11)
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/openbmc/openbmc/poky/meta/lib/oeqa/utils/
H A Dqemurunner.py4 # SPDX-License-Identifier: MIT
34 re_vt100 = re.compile(r'(\x1b\[|\x9b)[^@-_a-z]*[@-_a-z]|\x1b[@-_a-z]')
41 return os.read(o.fileno(), 1000000).decode("utf-8")
55 # target ip - from the command line or runqemu output
57 # host ip - where qemu is running
101 default_boot_patterns['search_login_succeeded'] = r"root@[a-zA-Z0-9\-]+:~#"
102 default_boot_patterns['search_cmd_finished'] = r"[a-zA-Z0-9]+@[a-zA-Z0-9\-]+:~#"
126 msg = todecode.decode("utf-8", errors='backslashreplace')
189 # use logfile to determine the recipe-sysroot-native path and
190 # then add in the site-packages path components and add that
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/openbmc/
Dopengrok1.0.log1 2025-12-15 03:01:05.452-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-12-15 03:01:05.518-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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Dopengrok2.0.log1 2025-12-14 03:01:07.427-0600 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-12-14 03:01:07.482-0600 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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