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/openbmc/u-boot/arch/arm/mach-imx/mx7ulp/
H A Diomux.c25 u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; in mx7ulp_iomux_setup_pad() local
34 pad, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input, in mx7ulp_iomux_setup_pad()
37 if (mux_mode & IOMUX_CONFIG_MPORTS) { in mx7ulp_iomux_setup_pad()
38 mux_mode &= ~IOMUX_CONFIG_MPORTS; in mx7ulp_iomux_setup_pad()
44 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & in mx7ulp_iomux_setup_pad()
52 __raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) & in mx7ulp_iomux_setup_pad()
/openbmc/u-boot/drivers/pinctrl/nxp/
H A Dpinctrl-imx.c26 u32 input_val, mux_mode, config_val; in imx_pinctrl_set_state() local
93 mux_mode = pin_data[j++]; in imx_pinctrl_set_state()
98 "input_reg 0x%x, mux_mode 0x%x, " in imx_pinctrl_set_state()
100 mux_reg, conf_reg, input_reg, mux_mode, in imx_pinctrl_set_state()
104 mux_mode |= IOMUXC_CONFIG_SION; in imx_pinctrl_set_state()
112 mux_mode << mux_shift); in imx_pinctrl_set_state()
114 writel(mux_mode, info->base + mux_reg); in imx_pinctrl_set_state()
118 mux_reg, mux_mode); in imx_pinctrl_set_state()
/openbmc/u-boot/arch/arm/mach-imx/
H A Diomux-v3.c24 u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT; in imx_iomux_v3_setup_pad() local
47 mux_mode &= ~IOMUX_CONFIG_LPSR; in imx_iomux_v3_setup_pad()
56 mux_mode &= ~IOMUX_CONFIG_LPSR; in imx_iomux_v3_setup_pad()
63 __raw_writel(mux_mode, base + mux_ctrl_ofs); in imx_iomux_v3_setup_pad()
70 __raw_writel((mux_mode << PAD_MUX_MODE_SHIFT) | pad_ctrl, in imx_iomux_v3_setup_pad()
/openbmc/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx.h23 * @mux_mode: the mux mode for this pin.
30 unsigned int mux_mode; member
42 unsigned int mux_mode; member
90 /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
H A Dpinctrl-imx.c187 reg |= (pin_mmio->mux_mode << info->mux_shift); in imx_pmx_set_one_pin_mmio()
192 writel(pin_mmio->mux_mode, ipctl->base + pin_reg->mux_reg); in imx_pmx_set_one_pin_mmio()
194 pin_reg->mux_reg, pin_mmio->mux_mode); in imx_pmx_set_one_pin_mmio()
450 * <mux_reg conf_reg input_reg mux_mode input_val>
452 * <mux_conf_reg input_reg mux_mode input_val>
454 * <pin_id mux_mode>
491 pin_mmio->mux_mode = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_mmio()
498 pin_mmio->mux_mode |= IOMUXC_CONFIG_SION; in imx_pinctrl_parse_pin_mmio()
504 pin_mmio->mux_mode, pin_mmio->config); in imx_pinctrl_parse_pin_mmio()
H A Dpinctrl-scu.c150 pin_scu->mux_mode = be32_to_cpu(*list++); in imx_pinctrl_parse_pin_scu()
155 pin_scu->mux_mode, pin_scu->config); in imx_pinctrl_parse_pin_scu()
/openbmc/linux/arch/arm/mach-davinci/
H A Dmux.h668 #define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\ argument
676 .mode = mux_mode, \
679 #define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \ argument
687 .mode = mux_mode, \
690 #define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \ argument
698 .mode = mux_mode, \
/openbmc/u-boot/arch/arm/include/asm/arch-mx7ulp/
H A Diomux.h38 * MUX_MODE: 32..37 (6)
61 #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ argument
64 ((iomux_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx8ulp-pinctrl.yaml36 mux_mode input_val> are specified using a PIN_FUNC_ID macro, which can
48 "mux_mode" indicates the mux value to be applied.
H A Dfsl,imx7ulp-pinctrl.txt17 <mux_conf_reg input_reg mux_mode input_val> are specified
H A Dfsl,imx-pinctrl.txt36 Force the selected mux mode input path no matter of MUX_MODE functionality.
/openbmc/u-boot/arch/arm/include/asm/mach-imx/
H A Diomux-v3.h41 * MUX_MODE + SION + LPSR: 36..41 (6)
68 #define IOMUX_PAD(pad_ctrl_ofs, mux_ctrl_ofs, mux_mode, sel_input_ofs, \ argument
71 ((iomux_v3_cfg_t)(mux_mode) << MUX_MODE_SHIFT) | \
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-pinfunc-snvs.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx6ull-pinfunc.h12 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx7ulp-pinfunc.h12 * <mux_conf_reg input_reg mux_mode input_val>
H A Dimx25-pinfunc.h13 * <mux_reg conf_reg input_reg mux_mode input_val>
/openbmc/u-boot/arch/arm/dts/
H A Dimx6ull-pinfunc-snvs.h13 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx6ull-pinfunc.h15 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dvf610-pinfunc.h15 * <mux_reg input_reg mux_mode input_val>
/openbmc/linux/include/dt-bindings/pinctrl/
H A Dpads-imx8dxl.h147 /* format: <pin_id mux_mode> */
H A Dpads-imx8qxp.h187 * format: <pin_id mux_mode>
H A Dpads-imx8qm.h282 * format: <pin_id mux_mode>
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-pinfunc.h11 * <mux_reg conf_reg input_reg mux_mode input_val>
H A Dimx8mq-pinfunc.h12 * <mux_reg conf_reg input_reg mux_mode input_val>
/openbmc/u-boot/include/dt-bindings/pinctrl/
H A Dpins-imx8mq.h21 * <mux_reg conf_reg input_reg mux_mode input_val>

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