183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2745df68dSPeng Fan /*
3745df68dSPeng Fan * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
4745df68dSPeng Fan */
5745df68dSPeng Fan
6745df68dSPeng Fan #include <common.h>
7745df68dSPeng Fan #include <mapmem.h>
8745df68dSPeng Fan #include <linux/io.h>
9745df68dSPeng Fan #include <linux/err.h>
109d922450SSimon Glass #include <dm.h>
11745df68dSPeng Fan #include <dm/pinctrl.h>
12745df68dSPeng Fan
13745df68dSPeng Fan #include "pinctrl-imx.h"
14745df68dSPeng Fan
15745df68dSPeng Fan DECLARE_GLOBAL_DATA_PTR;
16745df68dSPeng Fan
imx_pinctrl_set_state(struct udevice * dev,struct udevice * config)17745df68dSPeng Fan static int imx_pinctrl_set_state(struct udevice *dev, struct udevice *config)
18745df68dSPeng Fan {
19745df68dSPeng Fan struct imx_pinctrl_priv *priv = dev_get_priv(dev);
20745df68dSPeng Fan struct imx_pinctrl_soc_info *info = priv->info;
21e160f7d4SSimon Glass int node = dev_of_offset(config);
22745df68dSPeng Fan const struct fdt_property *prop;
23745df68dSPeng Fan u32 *pin_data;
24745df68dSPeng Fan int npins, size, pin_size;
25*11a1c27eSYe Li int mux_reg, conf_reg, input_reg;
26*11a1c27eSYe Li u32 input_val, mux_mode, config_val;
274aa9d4d0SPeng Fan u32 mux_shift = info->mux_mask ? ffs(info->mux_mask) - 1 : 0;
28745df68dSPeng Fan int i, j = 0;
29745df68dSPeng Fan
30745df68dSPeng Fan dev_dbg(dev, "%s: %s\n", __func__, config->name);
31745df68dSPeng Fan
3238b6686fSPeng Fan if (info->flags & IMX8_USE_SCU)
3338b6686fSPeng Fan pin_size = SHARE_IMX8_PIN_SIZE;
3438b6686fSPeng Fan else if (info->flags & SHARE_MUX_CONF_REG)
35745df68dSPeng Fan pin_size = SHARE_FSL_PIN_SIZE;
36745df68dSPeng Fan else
37745df68dSPeng Fan pin_size = FSL_PIN_SIZE;
38745df68dSPeng Fan
39745df68dSPeng Fan prop = fdt_getprop(gd->fdt_blob, node, "fsl,pins", &size);
40745df68dSPeng Fan if (!prop) {
41745df68dSPeng Fan dev_err(dev, "No fsl,pins property in node %s\n", config->name);
42745df68dSPeng Fan return -EINVAL;
43745df68dSPeng Fan }
44745df68dSPeng Fan
45745df68dSPeng Fan if (!size || size % pin_size) {
46745df68dSPeng Fan dev_err(dev, "Invalid fsl,pins property in node %s\n",
47745df68dSPeng Fan config->name);
48745df68dSPeng Fan return -EINVAL;
49745df68dSPeng Fan }
50745df68dSPeng Fan
51745df68dSPeng Fan pin_data = devm_kzalloc(dev, size, 0);
52745df68dSPeng Fan if (!pin_data)
53745df68dSPeng Fan return -ENOMEM;
54745df68dSPeng Fan
55745df68dSPeng Fan if (fdtdec_get_int_array(gd->fdt_blob, node, "fsl,pins",
56745df68dSPeng Fan pin_data, size >> 2)) {
57745df68dSPeng Fan dev_err(dev, "Error reading pin data.\n");
58c1d1e9d6SPeng Fan devm_kfree(dev, pin_data);
59745df68dSPeng Fan return -EINVAL;
60745df68dSPeng Fan }
61745df68dSPeng Fan
62745df68dSPeng Fan npins = size / pin_size;
63745df68dSPeng Fan
6438b6686fSPeng Fan if (info->flags & IMX8_USE_SCU) {
6538b6686fSPeng Fan imx_pinctrl_scu_conf_pins(info, pin_data, npins);
6638b6686fSPeng Fan } else {
67745df68dSPeng Fan /*
68745df68dSPeng Fan * Refer to linux documentation for details:
69745df68dSPeng Fan * Documentation/devicetree/bindings/pinctrl/fsl,imx-pinctrl.txt
70745df68dSPeng Fan */
71745df68dSPeng Fan for (i = 0; i < npins; i++) {
72745df68dSPeng Fan mux_reg = pin_data[j++];
73745df68dSPeng Fan
74745df68dSPeng Fan if (!(info->flags & ZERO_OFFSET_VALID) && !mux_reg)
75745df68dSPeng Fan mux_reg = -1;
76745df68dSPeng Fan
77745df68dSPeng Fan if (info->flags & SHARE_MUX_CONF_REG) {
78745df68dSPeng Fan conf_reg = mux_reg;
79745df68dSPeng Fan } else {
80745df68dSPeng Fan conf_reg = pin_data[j++];
8138b6686fSPeng Fan if (!(info->flags & ZERO_OFFSET_VALID) &&
8238b6686fSPeng Fan !conf_reg)
83745df68dSPeng Fan conf_reg = -1;
84745df68dSPeng Fan }
85745df68dSPeng Fan
86745df68dSPeng Fan if ((mux_reg == -1) || (conf_reg == -1)) {
87745df68dSPeng Fan dev_err(dev, "Error mux_reg or conf_reg\n");
88c1d1e9d6SPeng Fan devm_kfree(dev, pin_data);
89745df68dSPeng Fan return -EINVAL;
90745df68dSPeng Fan }
91745df68dSPeng Fan
92745df68dSPeng Fan input_reg = pin_data[j++];
93745df68dSPeng Fan mux_mode = pin_data[j++];
94745df68dSPeng Fan input_val = pin_data[j++];
95745df68dSPeng Fan config_val = pin_data[j++];
96745df68dSPeng Fan
9738b6686fSPeng Fan dev_dbg(dev, "mux_reg 0x%x, conf_reg 0x%x, "
9838b6686fSPeng Fan "input_reg 0x%x, mux_mode 0x%x, "
9938b6686fSPeng Fan "input_val 0x%x, config_val 0x%x\n",
10038b6686fSPeng Fan mux_reg, conf_reg, input_reg, mux_mode,
10138b6686fSPeng Fan input_val, config_val);
102745df68dSPeng Fan
103745df68dSPeng Fan if (config_val & IMX_PAD_SION)
104745df68dSPeng Fan mux_mode |= IOMUXC_CONFIG_SION;
105745df68dSPeng Fan
106745df68dSPeng Fan config_val &= ~IMX_PAD_SION;
107745df68dSPeng Fan
108745df68dSPeng Fan /* Set Mux */
109745df68dSPeng Fan if (info->flags & SHARE_MUX_CONF_REG) {
11038b6686fSPeng Fan clrsetbits_le32(info->base + mux_reg,
11138b6686fSPeng Fan info->mux_mask,
1124aa9d4d0SPeng Fan mux_mode << mux_shift);
113745df68dSPeng Fan } else {
114745df68dSPeng Fan writel(mux_mode, info->base + mux_reg);
115745df68dSPeng Fan }
116745df68dSPeng Fan
11738b6686fSPeng Fan dev_dbg(dev, "write mux: offset 0x%x val 0x%x\n",
11838b6686fSPeng Fan mux_reg, mux_mode);
119745df68dSPeng Fan
120745df68dSPeng Fan /*
121745df68dSPeng Fan * Set select input
122745df68dSPeng Fan *
12338b6686fSPeng Fan * If the select input value begins with 0xff,
12438b6686fSPeng Fan * it's a quirky select input and the value should
12538b6686fSPeng Fan * be interpreted as below.
126745df68dSPeng Fan * 31 23 15 7 0
127745df68dSPeng Fan * | 0xff | shift | width | select |
12838b6686fSPeng Fan * It's used to work around the problem that the
12938b6686fSPeng Fan * select input for some pin is not implemented in
13038b6686fSPeng Fan * the select input register but in some general
13138b6686fSPeng Fan * purpose register. We encode the select input
13238b6686fSPeng Fan * value, width and shift of the bit field into
13338b6686fSPeng Fan * input_val cell of pin function ID in device tree,
13438b6686fSPeng Fan * and then decode them here for setting up the select
13538b6686fSPeng Fan * input bits in general purpose register.
136745df68dSPeng Fan */
137745df68dSPeng Fan
138745df68dSPeng Fan if (input_val >> 24 == 0xff) {
139745df68dSPeng Fan u32 val = input_val;
140745df68dSPeng Fan u8 select = val & 0xff;
141745df68dSPeng Fan u8 width = (val >> 8) & 0xff;
142745df68dSPeng Fan u8 shift = (val >> 16) & 0xff;
143745df68dSPeng Fan u32 mask = ((1 << width) - 1) << shift;
144745df68dSPeng Fan /*
14538b6686fSPeng Fan * The input_reg[i] here is actually some
14638b6686fSPeng Fan * IOMUXC general purpose register, not
14738b6686fSPeng Fan * regular select input register.
148745df68dSPeng Fan */
149745df68dSPeng Fan val = readl(info->base + input_reg);
150745df68dSPeng Fan val &= ~mask;
151745df68dSPeng Fan val |= select << shift;
152745df68dSPeng Fan writel(val, info->base + input_reg);
153745df68dSPeng Fan } else if (input_reg) {
154745df68dSPeng Fan /*
15538b6686fSPeng Fan * Regular select input register can never be
15638b6686fSPeng Fan * at offset 0, and we only print register
15738b6686fSPeng Fan * value for regular case.
158745df68dSPeng Fan */
159745df68dSPeng Fan if (info->input_sel_base)
16038b6686fSPeng Fan writel(input_val,
16138b6686fSPeng Fan info->input_sel_base +
162745df68dSPeng Fan input_reg);
163745df68dSPeng Fan else
16438b6686fSPeng Fan writel(input_val,
16538b6686fSPeng Fan info->base + input_reg);
166745df68dSPeng Fan
16738b6686fSPeng Fan dev_dbg(dev, "select_input: offset 0x%x val "
16838b6686fSPeng Fan "0x%x\n", input_reg, input_val);
169745df68dSPeng Fan }
170745df68dSPeng Fan
171745df68dSPeng Fan /* Set config */
172745df68dSPeng Fan if (!(config_val & IMX_NO_PAD_CTL)) {
173745df68dSPeng Fan if (info->flags & SHARE_MUX_CONF_REG) {
1744aa9d4d0SPeng Fan clrsetbits_le32(info->base + conf_reg,
17538b6686fSPeng Fan ~info->mux_mask,
17638b6686fSPeng Fan config_val);
177745df68dSPeng Fan } else {
17838b6686fSPeng Fan writel(config_val,
17938b6686fSPeng Fan info->base + conf_reg);
180745df68dSPeng Fan }
181745df68dSPeng Fan
18238b6686fSPeng Fan dev_dbg(dev, "write config: offset 0x%x val "
18338b6686fSPeng Fan "0x%x\n", conf_reg, config_val);
18438b6686fSPeng Fan }
185745df68dSPeng Fan }
186745df68dSPeng Fan }
187745df68dSPeng Fan
188c1d1e9d6SPeng Fan devm_kfree(dev, pin_data);
189c1d1e9d6SPeng Fan
190745df68dSPeng Fan return 0;
191745df68dSPeng Fan }
192745df68dSPeng Fan
193745df68dSPeng Fan const struct pinctrl_ops imx_pinctrl_ops = {
194745df68dSPeng Fan .set_state = imx_pinctrl_set_state,
195745df68dSPeng Fan };
196745df68dSPeng Fan
imx_pinctrl_probe(struct udevice * dev,struct imx_pinctrl_soc_info * info)197745df68dSPeng Fan int imx_pinctrl_probe(struct udevice *dev,
198745df68dSPeng Fan struct imx_pinctrl_soc_info *info)
199745df68dSPeng Fan {
200745df68dSPeng Fan struct imx_pinctrl_priv *priv = dev_get_priv(dev);
201e160f7d4SSimon Glass int node = dev_of_offset(dev), ret;
202745df68dSPeng Fan struct fdtdec_phandle_args arg;
203745df68dSPeng Fan fdt_addr_t addr;
204745df68dSPeng Fan fdt_size_t size;
205745df68dSPeng Fan
206745df68dSPeng Fan if (!info) {
207745df68dSPeng Fan dev_err(dev, "wrong pinctrl info\n");
208745df68dSPeng Fan return -EINVAL;
209745df68dSPeng Fan }
210745df68dSPeng Fan
211745df68dSPeng Fan priv->dev = dev;
212745df68dSPeng Fan priv->info = info;
213745df68dSPeng Fan
21438b6686fSPeng Fan if (info->flags & IMX8_USE_SCU)
21538b6686fSPeng Fan return 0;
21638b6686fSPeng Fan
217e160f7d4SSimon Glass addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
218e160f7d4SSimon Glass &size);
219745df68dSPeng Fan
220745df68dSPeng Fan if (addr == FDT_ADDR_T_NONE)
221745df68dSPeng Fan return -EINVAL;
222745df68dSPeng Fan
223745df68dSPeng Fan info->base = map_sysmem(addr, size);
224745df68dSPeng Fan if (!info->base)
225745df68dSPeng Fan return -ENOMEM;
226745df68dSPeng Fan priv->info = info;
227745df68dSPeng Fan
2284aa9d4d0SPeng Fan info->mux_mask = fdtdec_get_int(gd->fdt_blob, node, "fsl,mux_mask", 0);
229745df68dSPeng Fan /*
230745df68dSPeng Fan * Refer to linux documentation for details:
231745df68dSPeng Fan * Documentation/devicetree/bindings/pinctrl/fsl,imx7d-pinctrl.txt
232745df68dSPeng Fan */
233745df68dSPeng Fan if (fdtdec_get_bool(gd->fdt_blob, node, "fsl,input-sel")) {
234745df68dSPeng Fan ret = fdtdec_parse_phandle_with_args(gd->fdt_blob,
235745df68dSPeng Fan node, "fsl,input-sel",
236745df68dSPeng Fan NULL, 0, 0, &arg);
237745df68dSPeng Fan if (ret) {
238745df68dSPeng Fan dev_err(dev, "iomuxc fsl,input-sel property not found\n");
239745df68dSPeng Fan return -EINVAL;
240745df68dSPeng Fan }
241745df68dSPeng Fan
242745df68dSPeng Fan addr = fdtdec_get_addr_size(gd->fdt_blob, arg.node, "reg",
243745df68dSPeng Fan &size);
244745df68dSPeng Fan if (addr == FDT_ADDR_T_NONE)
245745df68dSPeng Fan return -EINVAL;
246745df68dSPeng Fan
247745df68dSPeng Fan info->input_sel_base = map_sysmem(addr, size);
248745df68dSPeng Fan if (!info->input_sel_base)
249745df68dSPeng Fan return -ENOMEM;
250745df68dSPeng Fan }
251745df68dSPeng Fan
2525a6f8d7bSStefan Agner dev_dbg(dev, "initialized IMX pinctrl driver\n");
253745df68dSPeng Fan
254745df68dSPeng Fan return 0;
255745df68dSPeng Fan }
256745df68dSPeng Fan
imx_pinctrl_remove(struct udevice * dev)257745df68dSPeng Fan int imx_pinctrl_remove(struct udevice *dev)
258745df68dSPeng Fan {
259745df68dSPeng Fan struct imx_pinctrl_priv *priv = dev_get_priv(dev);
260745df68dSPeng Fan struct imx_pinctrl_soc_info *info = priv->info;
261745df68dSPeng Fan
26238b6686fSPeng Fan if (info->flags & IMX8_USE_SCU)
26338b6686fSPeng Fan return 0;
26438b6686fSPeng Fan
265745df68dSPeng Fan if (info->input_sel_base)
266745df68dSPeng Fan unmap_sysmem(info->input_sel_base);
267745df68dSPeng Fan if (info->base)
268745df68dSPeng Fan unmap_sysmem(info->base);
269745df68dSPeng Fan
270745df68dSPeng Fan return 0;
271745df68dSPeng Fan }
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