xref: /openbmc/u-boot/arch/arm/mach-imx/mx7ulp/iomux.c (revision e8f80a5a)
1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2552a848eSStefano Babic /*
3552a848eSStefano Babic  * Copyright (C) 2016 Freescale Semiconductor, Inc.
4552a848eSStefano Babic  */
5552a848eSStefano Babic #include <common.h>
6552a848eSStefano Babic #include <asm/io.h>
7552a848eSStefano Babic #include <asm/arch/imx-regs.h>
8552a848eSStefano Babic #include <asm/arch/iomux.h>
9552a848eSStefano Babic 
10552a848eSStefano Babic static void *base = (void *)IOMUXC_BASE_ADDR;
11552a848eSStefano Babic 
12552a848eSStefano Babic /*
13552a848eSStefano Babic  * iomuxc0 base address. In imx7ulp-pins.h,
14552a848eSStefano Babic  * the offsets of pins in iomuxc0 are from 0xD000,
15552a848eSStefano Babic  * so we set the base address to (0x4103D000 - 0xD000 = 0x41030000)
16552a848eSStefano Babic  */
17552a848eSStefano Babic static void *base_mports = (void *)(AIPS0_BASE + 0x30000);
18552a848eSStefano Babic 
19552a848eSStefano Babic /*
20552a848eSStefano Babic  * configures a single pad in the iomuxer
21552a848eSStefano Babic  */
mx7ulp_iomux_setup_pad(iomux_cfg_t pad)22552a848eSStefano Babic void mx7ulp_iomux_setup_pad(iomux_cfg_t pad)
23552a848eSStefano Babic {
24552a848eSStefano Babic 	u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
25552a848eSStefano Babic 	u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
26552a848eSStefano Babic 	u32 sel_input_ofs =
27552a848eSStefano Babic 		(pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
28552a848eSStefano Babic 	u32 sel_input =
29552a848eSStefano Babic 		(pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
30552a848eSStefano Babic 	u32 pad_ctrl_ofs = mux_ctrl_ofs;
31552a848eSStefano Babic 	u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
32552a848eSStefano Babic 
33552a848eSStefano Babic 	debug("[PAD CFG] = 0x%16llX \r\n\tmux_ctl = 0x%X(0x%X) sel_input = 0x%X(0x%X) pad_ctrl = 0x%X(0x%X)\r\n",
34552a848eSStefano Babic 	      pad, mux_ctrl_ofs, mux_mode, sel_input_ofs, sel_input,
35552a848eSStefano Babic 	      pad_ctrl_ofs, pad_ctrl);
36552a848eSStefano Babic 
37552a848eSStefano Babic 	if (mux_mode & IOMUX_CONFIG_MPORTS) {
38552a848eSStefano Babic 		mux_mode &= ~IOMUX_CONFIG_MPORTS;
39552a848eSStefano Babic 		base = base_mports;
40552a848eSStefano Babic 	} else {
41552a848eSStefano Babic 		base = (void *)IOMUXC_BASE_ADDR;
42552a848eSStefano Babic 	}
43552a848eSStefano Babic 
44552a848eSStefano Babic 	__raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
45552a848eSStefano Babic 		     IOMUXC_PCR_MUX_ALT_MASK), base + mux_ctrl_ofs);
46552a848eSStefano Babic 
47552a848eSStefano Babic 	if (sel_input_ofs)
48552a848eSStefano Babic 		__raw_writel((sel_input << IOMUXC_PSMI_IMUX_ALT_SHIFT),
49552a848eSStefano Babic 			base + sel_input_ofs);
50552a848eSStefano Babic 
51552a848eSStefano Babic 	if (!(pad_ctrl & NO_PAD_CTRL))
52552a848eSStefano Babic 		__raw_writel(((mux_mode << IOMUXC_PCR_MUX_ALT_SHIFT) &
53552a848eSStefano Babic 			     IOMUXC_PCR_MUX_ALT_MASK) |
54552a848eSStefano Babic 			     (pad_ctrl & (~IOMUXC_PCR_MUX_ALT_MASK)),
55552a848eSStefano Babic 			     base + pad_ctrl_ofs);
56552a848eSStefano Babic }
57552a848eSStefano Babic 
58552a848eSStefano Babic /* configures a list of pads within declared with IOMUX_PADS macro */
mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const * pad_list,unsigned count)59552a848eSStefano Babic void mx7ulp_iomux_setup_multiple_pads(iomux_cfg_t const *pad_list,
60552a848eSStefano Babic 				      unsigned count)
61552a848eSStefano Babic {
62552a848eSStefano Babic 	iomux_cfg_t const *p = pad_list;
63552a848eSStefano Babic 	int i;
64552a848eSStefano Babic 
65552a848eSStefano Babic 	for (i = 0; i < count; i++) {
66552a848eSStefano Babic 		mx7ulp_iomux_setup_pad(*p);
67552a848eSStefano Babic 		p++;
68552a848eSStefano Babic 	}
69552a848eSStefano Babic }
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