/openbmc/linux/drivers/clk/ti/ |
H A D | mux.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 * Tero Kristo <t-kristo@ti.com> 10 #include <linux/clk-provider.h> 23 struct clk_omap_mux *mux = to_clk_omap_mux(hw); in ti_clk_mux_get_parent() local 28 * FIXME need a mux-specific flag to determine if val is bitwise or in ti_clk_mux_get_parent() 34 val = ti_clk_ll_ops->clk_readl(&mux->reg) >> mux->shift; in ti_clk_mux_get_parent() 35 val &= mux->mask; in ti_clk_mux_get_parent() 37 if (mux->table) { in ti_clk_mux_get_parent() 41 if (mux->table[i] == val) in ti_clk_mux_get_parent() 43 return -EINVAL; in ti_clk_mux_get_parent() [all …]
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/openbmc/u-boot/drivers/pinctrl/ |
H A D | pinctrl-at91.c | 1 // SPDX-License-Identifier: GPL-2.0+ 67 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group 68 * on new IP with support for periph C and D the way to mux in 82 void (*mux_A_periph)(struct at91_port *pio, u32 mask); 83 void (*mux_B_periph)(struct at91_port *pio, u32 mask); 84 void (*mux_C_periph)(struct at91_port *pio, u32 mask); 85 void (*mux_D_periph)(struct at91_port *pio, u32 mask); 86 void (*set_deglitch)(struct at91_port *pio, u32 mask, bool is_on); 87 void (*set_debounce)(struct at91_port *pio, u32 mask, bool is_on, 89 void (*set_pulldown)(struct at91_port *pio, u32 mask, bool is_on); [all …]
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/openbmc/linux/drivers/clk/qcom/ |
H A D | clk-krait.c | 1 // SPDX-License-Identifier: GPL-2.0 10 #include <linux/clk-provider.h> 13 #include <asm/krait-l2-accessors.h> 15 #include "clk-krait.h" 23 static void __krait_mux_set_sel(struct krait_mux_clk *mux, int sel) in __krait_mux_set_sel() argument 30 regval = krait_get_l2_indirect_reg(mux->offset); in __krait_mux_set_sel() 33 if (mux->disable_sec_src_gating) { in __krait_mux_set_sel() 35 krait_set_l2_indirect_reg(mux->offset, regval); in __krait_mux_set_sel() 38 regval &= ~(mux->mask << mux->shift); in __krait_mux_set_sel() 39 regval |= (sel & mux->mask) << mux->shift; in __krait_mux_set_sel() [all …]
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H A D | clk-regmap-mux.c | 1 // SPDX-License-Identifier: GPL-2.0-only 11 #include "clk-regmap-mux.h" 20 struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); in mux_get_parent() local 22 unsigned int mask = GENMASK(mux->width - 1, 0); in mux_get_parent() local 25 regmap_read(clkr->regmap, mux->reg, &val); in mux_get_parent() 27 val >>= mux->shift; in mux_get_parent() 28 val &= mask; in mux_get_parent() 30 if (mux->parent_map) in mux_get_parent() 31 return qcom_find_cfg_index(hw, mux->parent_map, val); in mux_get_parent() 38 struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); in mux_set_parent() local [all …]
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/openbmc/u-boot/drivers/gpio/ |
H A D | at91_gpio.c | 1 // SPDX-License-Identifier: GPL-2.0+ 48 u32 mask; in at91_set_port_pullup() local 50 mask = 1 << offset; in at91_set_port_pullup() 52 writel(mask, &at91_port->puer); in at91_set_port_pullup() 54 writel(mask, &at91_port->pudr); in at91_set_port_pullup() 55 writel(mask, &at91_port->per); in at91_set_port_pullup() 69 * mux the pin to the "GPIO" peripheral role. 74 u32 mask; in at91_set_pio_periph() local 77 mask = 1 << pin; in at91_set_pio_periph() 78 writel(mask, &at91_port->idr); in at91_set_pio_periph() [all …]
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/openbmc/linux/drivers/clk/ |
H A D | clk-mux.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org> 10 #include <linux/clk-provider.h> 21 * prepare - clk_prepare only ensures that parents are prepared 22 * enable - clk_enable only ensures that parents are enabled 23 * rate - rate is only affected by parent switching. No clk_set_rate support 24 * parent - parent is adjustable through clk_set_parent 27 static inline u32 clk_mux_readl(struct clk_mux *mux) in clk_mux_readl() argument 29 if (mux->flags & CLK_MUX_BIG_ENDIAN) in clk_mux_readl() 30 return ioread32be(mux->reg); in clk_mux_readl() [all …]
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/openbmc/linux/drivers/clk/mediatek/ |
H A D | clk-cpumux.c | 1 // SPDX-License-Identifier: GPL-2.0-only 4 * Author: Pi-Cheng Chen <pi-cheng.chen@linaro.org> 7 #include <linux/clk-provider.h> 15 #include "clk-mtk.h" 16 #include "clk-cpumux.h" 22 u32 mask; member 33 struct mtk_clk_cpumux *mux = to_mtk_clk_cpumux(hw); in clk_cpumux_get_parent() local 36 regmap_read(mux->regmap, mux->reg, &val); in clk_cpumux_get_parent() 38 val >>= mux->shift; in clk_cpumux_get_parent() 39 val &= mux->mask; in clk_cpumux_get_parent() [all …]
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H A D | clk-mux.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <linux/clk-provider.h> 18 #include "clk-mux.h" 35 struct mtk_clk_mux *mux = to_mtk_clk_mux(hw); in mtk_clk_mux_enable_setclr() local 38 if (mux->lock) in mtk_clk_mux_enable_setclr() 39 spin_lock_irqsave(mux->lock, flags); in mtk_clk_mux_enable_setclr() 41 __acquire(mux->lock); in mtk_clk_mux_enable_setclr() 43 regmap_write(mux->regmap, mux->data->clr_ofs, in mtk_clk_mux_enable_setclr() 44 BIT(mux->data->gate_shift)); in mtk_clk_mux_enable_setclr() 48 * not be effective yet. Set the update bit to ensure the mux gets in mtk_clk_mux_enable_setclr() [all …]
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/openbmc/linux/drivers/mux/ |
H A D | mmio.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * MMIO register bitfield-controlled multiplexer driver 12 #include <linux/mux/driver.h> 18 static int mux_mmio_set(struct mux_control *mux, int state) in mux_mmio_set() argument 20 struct regmap_field **fields = mux_chip_priv(mux->chip); in mux_mmio_set() 22 return regmap_field_write(fields[mux_control_get_index(mux)], state); in mux_mmio_set() 30 { .compatible = "mmio-mux", }, 31 { .compatible = "reg-mux", }, 38 struct device *dev = &pdev->dev; in mux_mmio_probe() 39 struct device_node *np = dev->of_node; in mux_mmio_probe() [all …]
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/openbmc/linux/drivers/net/mdio/ |
H A D | mdio-mux-mmioreg.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Simple memory-mapped device MDIO MUX driver 11 #include <linux/mdio-mux.h> 22 unsigned int mask; member 28 * This function is called by the mdio-mux layer when it thinks the mdio bus 31 * 'current_child' is the current value of the mux register (masked via 32 * s->mask). 37 * The first time this function is called, current_child == -1. 39 * If current_child == desired_child, then the mux is already set to the 48 void __iomem *p = ioremap(s->phys, s->iosize); in mdio_mux_mmioreg_switch_fn() [all …]
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/openbmc/linux/drivers/clk/rockchip/ |
H A D | clk-muxgrf.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <linux/clk-provider.h> 23 struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw); in rockchip_muxgrf_get_parent() local 24 unsigned int mask = GENMASK(mux->width - 1, 0); in rockchip_muxgrf_get_parent() local 27 regmap_read(mux->regmap, mux->reg, &val); in rockchip_muxgrf_get_parent() 29 val >>= mux->shift; in rockchip_muxgrf_get_parent() 30 val &= mask; in rockchip_muxgrf_get_parent() 37 struct rockchip_muxgrf_clock *mux = to_muxgrf_clock(hw); in rockchip_muxgrf_set_parent() local 38 unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); in rockchip_muxgrf_set_parent() local 42 val <<= mux->shift; in rockchip_muxgrf_set_parent() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | mdio-mux-mmioreg.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device 10 - Andrew Lunn <andrew@lunn.ch> 13 This is a special case of a MDIO bus multiplexer. A memory-mapped device, 14 like an FPGA, is used to control which child bus is connected. The mdio-mux 15 node must be a child of the memory-mapped device. The driver currently only 16 supports devices with 8, 16 or 32-bit registers. [all …]
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/openbmc/linux/drivers/iio/multiplexer/ |
H A D | iio-mux.c | 1 // SPDX-License-Identifier: GPL-2.0 16 #include <linux/mux/consumer.h> 29 struct mux { struct 40 static int iio_mux_select(struct mux *mux, int idx) in iio_mux_select() argument 42 struct mux_child *child = &mux->child[idx]; in iio_mux_select() 43 struct iio_chan_spec const *chan = &mux->chan[idx]; in iio_mux_select() 47 ret = mux_control_select_delay(mux->control, chan->channel, in iio_mux_select() 48 mux->delay_us); in iio_mux_select() 50 mux->cached_state = -1; in iio_mux_select() 54 if (mux->cached_state == chan->channel) in iio_mux_select() [all …]
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/openbmc/linux/arch/arm/boot/dts/marvell/ |
H A D | mmp3.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 6 #include <dt-bindings/clock/marvell,mmp2.h> 7 #include <dt-bindings/power/marvell,mmp2.h> 8 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #address-cells = <1>; 12 #size-cells = <1>; 15 #address-cells = <1>; 16 #size-cells = <0>; 17 enable-method = "marvell,mmp3-smp"; 22 next-level-cache = <&l2>; [all …]
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/openbmc/linux/arch/arm/mach-davinci/ |
H A D | mux.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Utility to set the DAVINCI MUX register from a table in mux.h 7 * Based on linux/arch/arm/plat-omap/mux.c: 8 * Copyright (C) 2003 - 2005 Nokia Corporation 23 #include "mux.h" 29 * Sets the DAVINCI MUX register based on the table 38 unsigned int mask, warn = 0; in davinci_cfg_reg() local 40 if (WARN_ON(!soc_info->pinmux_pins)) in davinci_cfg_reg() 41 return -ENODEV; in davinci_cfg_reg() 44 pinmux_base = ioremap(soc_info->pinmux_base, SZ_4K); in davinci_cfg_reg() [all …]
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/openbmc/linux/drivers/clk/davinci/ |
H A D | da8xx-cfgchip.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x CFGCHIP 8 #include <linux/clk-provider.h> 12 #include <linux/mfd/da8xx-cfgchip.h> 16 #include <linux/platform_data/clk-da8xx-cfgchip.h> 21 /* --- Gate clocks --- */ 36 u32 mask; member 46 return regmap_write_bits(clk->regmap, clk->reg, clk->mask, clk->mask); in da8xx_cfgchip_gate_clk_enable() 53 regmap_write_bits(clk->regmap, clk->reg, clk->mask, 0); in da8xx_cfgchip_gate_clk_disable() 61 regmap_read(clk->regmap, clk->reg, &val); in da8xx_cfgchip_gate_clk_is_enabled() [all …]
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/openbmc/linux/sound/soc/codecs/ |
H A D | 88pm860x-codec.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * 88pm860x-codec.c -- 88PM860x ALSA SoC Audio Driver 26 #include "88pm860x-codec.h" 117 * This widget should be just after DAC & PGA in DAPM power-on sequence and 118 * before DAC & PGA in DAPM power-off sequence. 149 /* -9450dB to 0dB in 150dB steps ( mute instead of -9450dB) */ 150 static const DECLARE_TLV_DB_SCALE(dpga_tlv, -9450, 150, 1); 152 /* -9dB to 0db in 3dB steps */ 153 static const DECLARE_TLV_DB_SCALE(adc_tlv, -900, 300, 0); 155 /* {-23, -17, -13.5, -11, -9, -6, -3, 0}dB */ [all …]
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/openbmc/linux/drivers/pinctrl/ |
H A D | pinctrl-at91.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 29 #include "pinctrl-at91.h" 46 * @ops: at91 pinctrl mux ops 114 * struct at91_pmx_func - describes AT91 pinmux functions 134 * struct at91_pmx_pin - describes an At91 pin mux 137 * @mux: the mux mode : gpio or periph_x of the pin i.e. alternate function. 143 enum at91_mux mux; member 148 * struct at91_pin_group - describes an At91 pin group 150 * @pins_conf: the mux mode for each pin in this group. The size of this [all …]
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/openbmc/linux/sound/soc/tegra/ |
H A D | tegra210_ahub.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 // tegra210_ahub.c - Tegra210 AHUB driver 5 // Copyright (c) 2020-2024, NVIDIA CORPORATION. All rights reserved. 22 struct soc_enum *e = (struct soc_enum *)kctl->private_value; in tegra_ahub_get_value_enum() 26 * Find the bit position of current MUX input. in tegra_ahub_get_value_enum() 29 for (i = 0; i < ahub->soc_data->reg_count; i++) { in tegra_ahub_get_value_enum() 32 reg = e->reg + (TEGRA210_XBAR_PART1_RX * i); in tegra_ahub_get_value_enum() 34 reg_val &= ahub->soc_data->mask[i]; in tegra_ahub_get_value_enum() 38 (8 * cmpnt->val_bytes * i); in tegra_ahub_get_value_enum() 44 for (i = 0; i < e->items; i++) { in tegra_ahub_get_value_enum() [all …]
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/openbmc/u-boot/board/freescale/corenet_ds/ |
H A D | eth_hydra.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2009-2011 Freescale Semiconductor, Inc. 10 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are 11 * provided by the standard Freescale four-port SGMII riser card. The 10Gb 33 * 2) The phy-handle property of each active Ethernet MAC node is set to the 36 * 3) The "mux value" for each virtual MDIO node is set to the correct value, 37 * if necessary. Some virtual MDIO nodes do not have configurable mux 38 * values, so those values are hard-coded in the DTS. On the HYDRA board, 46 * and might need to be enabled, and also might need to have its mux-value 81 * BRDCFG1 mask and value for each MAC [all …]
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | keystone-pll.txt | 1 Status: Unstable - ABI compatibility may be broken in the future 11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt 14 - #clock-cells : from common clock binding; shall be set to 0. 15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock" 16 - clocks : parent clock phandle 17 - reg - pll control0 and pll multiplier registers 18 - reg-names : control, multiplier and post-divider. The multiplier and 19 post-divider registers are applicable only for main pll clock 20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits 25 #clock-cells = <0>; [all …]
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/openbmc/linux/drivers/gpu/drm/radeon/ |
H A D | radeon_atpx_handler.c | 1 // SPDX-License-Identifier: GPL-2.0-only 37 /* handle for device - and atpx */ 61 u16 mux; member 81 * radeon_atpx_call - call an ATPX method 106 atpx_arg_elements[1].buffer.length = params->length; in radeon_atpx_call() 107 atpx_arg_elements[1].buffer.pointer = params->pointer; in radeon_atpx_call() 128 * radeon_atpx_parse_functions - parse supported functions 131 * @mask: supported functions mask from ATPX 133 * Use the supported functions mask from ATPX function 137 static void radeon_atpx_parse_functions(struct radeon_atpx_functions *f, u32 mask) in radeon_atpx_parse_functions() argument [all …]
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/openbmc/u-boot/drivers/pinctrl/rockchip/ |
H A D | pinctrl-rockchip-core.c | 1 // SPDX-License-Identifier: GPL-2.0+ 13 #include "pinctrl-rockchip.h" 22 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_verify_config() 24 if (bank >= ctrl->nr_banks) { in rockchip_verify_config() 25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); in rockchip_verify_config() 26 return -EINVAL; in rockchip_verify_config() 32 return -EINVAL; in rockchip_verify_config() 39 int *reg, u8 *bit, int *mask) in rockchip_get_recalced_mux() argument 41 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_get_recalced_mux() 42 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_recalced_mux() [all …]
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/openbmc/linux/drivers/clk/imx/ |
H A D | clk-fixup-mux.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 7 #include <linux/clk-provider.h> 14 * struct clk_fixup_mux - imx integer fixup multiplexer clock 15 * @mux: the parent class 23 struct clk_mux mux; member 30 struct clk_mux *mux = to_clk_mux(hw); in to_clk_fixup_mux() local 32 return container_of(mux, struct clk_fixup_mux, mux); in to_clk_fixup_mux() 39 return fixup_mux->ops->get_parent(&fixup_mux->mux.hw); in clk_fixup_mux_get_parent() 45 struct clk_mux *mux = to_clk_mux(hw); in clk_fixup_mux_set_parent() local 49 spin_lock_irqsave(mux->lock, flags); in clk_fixup_mux_set_parent() [all …]
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/openbmc/linux/drivers/clk/tegra/ |
H A D | clk-tegra-periph.c | 1 // SPDX-License-Identifier: GPL-2.0-only 7 #include <linux/clk-provider.h> 16 #include "clk-id.h" 130 #define MASK(x) (BIT(x) - 1) macro 132 #define MUX(_name, _parents, _offset, \ macro 135 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \ 142 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 149 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 155 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ 161 29, MASK(3), 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP,\ [all …]
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