1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2cba46148STimur Tabi /*
3cba46148STimur Tabi * Copyright 2009-2011 Freescale Semiconductor, Inc.
4cba46148STimur Tabi * Author: Timur Tabi <timur@freescale.com>
5cba46148STimur Tabi */
6cba46148STimur Tabi
7cba46148STimur Tabi /*
8cba46148STimur Tabi * This file handles the board muxing between the Fman Ethernet MACs and
9cba46148STimur Tabi * the RGMII/SGMII/XGMII PHYs on a Freescale P3041/P5020 "Hydra" reference
10cba46148STimur Tabi * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
11cba46148STimur Tabi * provided by the standard Freescale four-port SGMII riser card. The 10Gb
12cba46148STimur Tabi * XGMII PHY is provided via the XAUI riser card. Since there is only one
13cba46148STimur Tabi * Fman device on a P3041 and P5020, we only support one SGMII card and one
14cba46148STimur Tabi * RGMII card.
15cba46148STimur Tabi *
16cba46148STimur Tabi * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control
17cba46148STimur Tabi * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is
18cba46148STimur Tabi * always the same (0). The value for SGMII depends on which slot the riser is
19cba46148STimur Tabi * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII,
20cba46148STimur Tabi * the value is based on which slot the XAUI is inserted in.
21cba46148STimur Tabi *
22cba46148STimur Tabi * The SERDES configuration is used to determine where the SGMII and XAUI cards
23cba46148STimur Tabi * exist, and also which Fman MACs are routed to which PHYs. So for a given
24cba46148STimur Tabi * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed
25cba46148STimur Tabi * to PHYs dynamically.
26cba46148STimur Tabi *
27cba46148STimur Tabi *
28cba46148STimur Tabi * This file also updates the device tree in three ways:
29cba46148STimur Tabi *
30cba46148STimur Tabi * 1) The status of each virtual MDIO node that is referenced by an Ethernet
31cba46148STimur Tabi * node is set to "okay".
32cba46148STimur Tabi *
33cba46148STimur Tabi * 2) The phy-handle property of each active Ethernet MAC node is set to the
34cba46148STimur Tabi * appropriate PHY node.
35cba46148STimur Tabi *
36cba46148STimur Tabi * 3) The "mux value" for each virtual MDIO node is set to the correct value,
37cba46148STimur Tabi * if necessary. Some virtual MDIO nodes do not have configurable mux
38cba46148STimur Tabi * values, so those values are hard-coded in the DTS. On the HYDRA board,
39cba46148STimur Tabi * the virtual MDIO node for the SGMII card needs to be updated.
40cba46148STimur Tabi *
41cba46148STimur Tabi * For all this to work, the device tree needs to have the following:
42cba46148STimur Tabi *
43cba46148STimur Tabi * 1) An alias for each PHY node that an Ethernet node could be routed to.
44cba46148STimur Tabi *
45cba46148STimur Tabi * 2) An alias for each real and virtual MDIO node that is disabled by default
46cba46148STimur Tabi * and might need to be enabled, and also might need to have its mux-value
47cba46148STimur Tabi * updated.
48cba46148STimur Tabi */
49cba46148STimur Tabi
50cba46148STimur Tabi #include <common.h>
51cba46148STimur Tabi #include <netdev.h>
52cba46148STimur Tabi #include <asm/fsl_serdes.h>
53cba46148STimur Tabi #include <fm_eth.h>
54cba46148STimur Tabi #include <fsl_mdio.h>
55cba46148STimur Tabi #include <malloc.h>
562a523f52SShengzhou Liu #include <fdt_support.h>
578225b2fdSShaohui Xie #include <fsl_dtsec.h>
58cba46148STimur Tabi
59cba46148STimur Tabi #include "../common/ngpixis.h"
60cba46148STimur Tabi #include "../common/fman.h"
61cba46148STimur Tabi
62cba46148STimur Tabi #ifdef CONFIG_FMAN_ENET
63cba46148STimur Tabi
64b41f1263SChunhe Lan #define BRDCFG1_EMI1_SEL_MASK 0x78
65cba46148STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT1 0x10
66cba46148STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT2 0x20
67cba46148STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT5 0x30
68cba46148STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT6 0x40
69cba46148STimur Tabi #define BRDCFG1_EMI1_SEL_SLOT7 0x50
70cba46148STimur Tabi #define BRDCFG1_EMI1_SEL_RGMII 0x00
71cba46148STimur Tabi #define BRDCFG1_EMI1_EN 0x08
72cba46148STimur Tabi #define BRDCFG1_EMI2_SEL_MASK 0x06
73cba46148STimur Tabi #define BRDCFG1_EMI2_SEL_SLOT1 0x00
74cba46148STimur Tabi #define BRDCFG1_EMI2_SEL_SLOT2 0x02
75cba46148STimur Tabi
76cba46148STimur Tabi #define BRDCFG2_REG_GPIO_SEL 0x20
77cba46148STimur Tabi
78ffee1ddeSZhao Qiang #define PHY_BASE_ADDR 0x00
79ffee1ddeSZhao Qiang
80cba46148STimur Tabi /*
81cba46148STimur Tabi * BRDCFG1 mask and value for each MAC
82cba46148STimur Tabi *
83cba46148STimur Tabi * This array contains the BRDCFG1 values (in mask/val format) that route the
84cba46148STimur Tabi * MDIO bus to a particular RGMII or SGMII PHY.
85cba46148STimur Tabi */
86cba46148STimur Tabi struct {
87cba46148STimur Tabi u8 mask;
88cba46148STimur Tabi u8 val;
89cba46148STimur Tabi } mdio_mux[NUM_FM_PORTS];
90cba46148STimur Tabi
91cba46148STimur Tabi /*
92cba46148STimur Tabi * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means
93cba46148STimur Tabi * that the mapping must be determined dynamically, or that the lane maps to
94cba46148STimur Tabi * something other than a board slot
95cba46148STimur Tabi */
96cba46148STimur Tabi static u8 lane_to_slot[] = {
97cba46148STimur Tabi 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0
98cba46148STimur Tabi };
99cba46148STimur Tabi
100cba46148STimur Tabi /*
101cba46148STimur Tabi * Set the board muxing for a given MAC
102cba46148STimur Tabi *
103cba46148STimur Tabi * The MDIO layer calls this function every time it wants to talk to a PHY.
104cba46148STimur Tabi */
hydra_mux_mdio(u8 mask,u8 val)105cba46148STimur Tabi void hydra_mux_mdio(u8 mask, u8 val)
106cba46148STimur Tabi {
107cba46148STimur Tabi clrsetbits_8(&pixis->brdcfg1, mask, val);
108cba46148STimur Tabi }
109cba46148STimur Tabi
110cba46148STimur Tabi struct hydra_mdio {
111cba46148STimur Tabi u8 mask;
112cba46148STimur Tabi u8 val;
113cba46148STimur Tabi struct mii_dev *realbus;
114cba46148STimur Tabi };
115cba46148STimur Tabi
hydra_mdio_read(struct mii_dev * bus,int addr,int devad,int regnum)116cba46148STimur Tabi static int hydra_mdio_read(struct mii_dev *bus, int addr, int devad,
117cba46148STimur Tabi int regnum)
118cba46148STimur Tabi {
119cba46148STimur Tabi struct hydra_mdio *priv = bus->priv;
120cba46148STimur Tabi
121cba46148STimur Tabi hydra_mux_mdio(priv->mask, priv->val);
122cba46148STimur Tabi
123cba46148STimur Tabi return priv->realbus->read(priv->realbus, addr, devad, regnum);
124cba46148STimur Tabi }
125cba46148STimur Tabi
hydra_mdio_write(struct mii_dev * bus,int addr,int devad,int regnum,u16 value)126cba46148STimur Tabi static int hydra_mdio_write(struct mii_dev *bus, int addr, int devad,
127cba46148STimur Tabi int regnum, u16 value)
128cba46148STimur Tabi {
129cba46148STimur Tabi struct hydra_mdio *priv = bus->priv;
130cba46148STimur Tabi
131cba46148STimur Tabi hydra_mux_mdio(priv->mask, priv->val);
132cba46148STimur Tabi
133cba46148STimur Tabi return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
134cba46148STimur Tabi }
135cba46148STimur Tabi
hydra_mdio_reset(struct mii_dev * bus)136cba46148STimur Tabi static int hydra_mdio_reset(struct mii_dev *bus)
137cba46148STimur Tabi {
138cba46148STimur Tabi struct hydra_mdio *priv = bus->priv;
139cba46148STimur Tabi
140cba46148STimur Tabi return priv->realbus->reset(priv->realbus);
141cba46148STimur Tabi }
142cba46148STimur Tabi
hydra_mdio_set_mux(char * name,u8 mask,u8 val)143cba46148STimur Tabi static void hydra_mdio_set_mux(char *name, u8 mask, u8 val)
144cba46148STimur Tabi {
145cba46148STimur Tabi struct mii_dev *bus = miiphy_get_dev_by_name(name);
146cba46148STimur Tabi struct hydra_mdio *priv = bus->priv;
147cba46148STimur Tabi
148cba46148STimur Tabi priv->mask = mask;
149cba46148STimur Tabi priv->val = val;
150cba46148STimur Tabi }
151cba46148STimur Tabi
hydra_mdio_init(char * realbusname,char * fakebusname)152cba46148STimur Tabi static int hydra_mdio_init(char *realbusname, char *fakebusname)
153cba46148STimur Tabi {
154cba46148STimur Tabi struct hydra_mdio *hmdio;
155cba46148STimur Tabi struct mii_dev *bus = mdio_alloc();
156cba46148STimur Tabi
157cba46148STimur Tabi if (!bus) {
158cba46148STimur Tabi printf("Failed to allocate Hydra MDIO bus\n");
159cba46148STimur Tabi return -1;
160cba46148STimur Tabi }
161cba46148STimur Tabi
162cba46148STimur Tabi hmdio = malloc(sizeof(*hmdio));
163cba46148STimur Tabi if (!hmdio) {
164cba46148STimur Tabi printf("Failed to allocate Hydra private data\n");
165cba46148STimur Tabi free(bus);
166cba46148STimur Tabi return -1;
167cba46148STimur Tabi }
168cba46148STimur Tabi
169cba46148STimur Tabi bus->read = hydra_mdio_read;
170cba46148STimur Tabi bus->write = hydra_mdio_write;
171cba46148STimur Tabi bus->reset = hydra_mdio_reset;
172192bc694SBen Whitten strcpy(bus->name, fakebusname);
173cba46148STimur Tabi
174cba46148STimur Tabi hmdio->realbus = miiphy_get_dev_by_name(realbusname);
175cba46148STimur Tabi
176cba46148STimur Tabi if (!hmdio->realbus) {
177cba46148STimur Tabi printf("No bus with name %s\n", realbusname);
178cba46148STimur Tabi free(bus);
179cba46148STimur Tabi free(hmdio);
180cba46148STimur Tabi return -1;
181cba46148STimur Tabi }
182cba46148STimur Tabi
183cba46148STimur Tabi bus->priv = hmdio;
184cba46148STimur Tabi
185cba46148STimur Tabi return mdio_register(bus);
186cba46148STimur Tabi }
187cba46148STimur Tabi
188cba46148STimur Tabi /*
189cba46148STimur Tabi * Given an alias or a path for a node, set the mux value of that node.
190cba46148STimur Tabi *
191cba46148STimur Tabi * If 'alias' is not a valid alias, then it is treated as a full path to the
192cba46148STimur Tabi * node. No error checking is performed.
193cba46148STimur Tabi *
194cba46148STimur Tabi * This function is normally called to set the fsl,hydra-mdio-muxval property
195cba46148STimur Tabi * of a virtual MDIO node.
196cba46148STimur Tabi */
fdt_set_mdio_mux(void * fdt,const char * alias,u32 mux)197cba46148STimur Tabi static void fdt_set_mdio_mux(void *fdt, const char *alias, u32 mux)
198cba46148STimur Tabi {
199cba46148STimur Tabi const char *path = fdt_get_alias(fdt, alias);
200cba46148STimur Tabi
201cba46148STimur Tabi if (!path)
202cba46148STimur Tabi path = alias;
203cba46148STimur Tabi
204b41f1263SChunhe Lan do_fixup_by_path(fdt, path, "reg",
205b41f1263SChunhe Lan &mux, sizeof(mux), 1);
206cba46148STimur Tabi do_fixup_by_path(fdt, path, "fsl,hydra-mdio-muxval",
207cba46148STimur Tabi &mux, sizeof(mux), 1);
208cba46148STimur Tabi }
209cba46148STimur Tabi
210cba46148STimur Tabi /*
211cba46148STimur Tabi * Given the following ...
212cba46148STimur Tabi *
213cba46148STimur Tabi * 1) A pointer to an Fman Ethernet node (as identified by the 'compat'
214cba46148STimur Tabi * compatible string and 'addr' physical address)
215cba46148STimur Tabi *
216cba46148STimur Tabi * 2) An Fman port
217cba46148STimur Tabi *
218cba46148STimur Tabi * ... update the phy-handle property of the Ethernet node to point to the
219cba46148STimur Tabi * right PHY. This assumes that we already know the PHY for each port. That
220cba46148STimur Tabi * information is stored in mdio_mux[].
221cba46148STimur Tabi *
222cba46148STimur Tabi * The offset of the Fman Ethernet node is also passed in for convenience, but
223cba46148STimur Tabi * it is not used, and we recalculate the offset anyway.
224cba46148STimur Tabi *
225cba46148STimur Tabi * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC.
226cba46148STimur Tabi * Inside the Fman, "ports" are things that connect to MACs. We only call them
227cba46148STimur Tabi * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs
228cba46148STimur Tabi * and ports are the same thing.
229cba46148STimur Tabi *
230cba46148STimur Tabi * Note that this code would be cleaner if had a function called
231cba46148STimur Tabi * fm_info_get_phy_address(), which returns a value from the fm1_dtsec_info[]
232cba46148STimur Tabi * array. That's because all we're doing is figuring out the PHY address for
233cba46148STimur Tabi * a given Fman MAC and writing it to the device tree. Well, we already did
234cba46148STimur Tabi * the hard work to figure that out in board_eth_init(), so it's silly to
235cba46148STimur Tabi * repeat that here.
236cba46148STimur Tabi */
board_ft_fman_fixup_port(void * fdt,char * compat,phys_addr_t addr,enum fm_port port,int offset)237cba46148STimur Tabi void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
238cba46148STimur Tabi enum fm_port port, int offset)
239cba46148STimur Tabi {
240cba46148STimur Tabi unsigned int mux = mdio_mux[port].val & mdio_mux[port].mask;
241cba46148STimur Tabi char phy[16];
242cba46148STimur Tabi
243cba46148STimur Tabi if (port == FM1_10GEC1) {
244cba46148STimur Tabi /* XAUI */
245cba46148STimur Tabi int lane = serdes_get_first_lane(XAUI_FM1);
246cba46148STimur Tabi if (lane >= 0) {
247cba46148STimur Tabi /* The XAUI PHY is identified by the slot */
248cba46148STimur Tabi sprintf(phy, "phy_xgmii_%u", lane_to_slot[lane]);
249cba46148STimur Tabi fdt_set_phy_handle(fdt, compat, addr, phy);
250cba46148STimur Tabi }
251cba46148STimur Tabi return;
252cba46148STimur Tabi }
253cba46148STimur Tabi
254af7219deSMinghuan Lian if (mux == (BRDCFG1_EMI1_SEL_RGMII | BRDCFG1_EMI1_EN)) {
255cba46148STimur Tabi /* RGMII */
256cba46148STimur Tabi /* The RGMII PHY is identified by the MAC connected to it */
257cba46148STimur Tabi sprintf(phy, "phy_rgmii_%u", port == FM1_DTSEC4 ? 0 : 1);
258cba46148STimur Tabi fdt_set_phy_handle(fdt, compat, addr, phy);
259af7219deSMinghuan Lian return;
260cba46148STimur Tabi }
261cba46148STimur Tabi
262cba46148STimur Tabi /* If it's not RGMII or XGMII, it must be SGMII */
263cba46148STimur Tabi if (mux) {
264cba46148STimur Tabi /* The SGMII PHY is identified by the MAC connected to it */
265cba46148STimur Tabi sprintf(phy, "phy_sgmii_%x",
266cba46148STimur Tabi CONFIG_SYS_FM1_DTSEC1_PHY_ADDR + (port - FM1_DTSEC1));
267cba46148STimur Tabi fdt_set_phy_handle(fdt, compat, addr, phy);
268cba46148STimur Tabi }
269cba46148STimur Tabi }
270cba46148STimur Tabi
271cba46148STimur Tabi #define PIXIS_SW2_LANE_23_SEL 0x80
272cba46148STimur Tabi #define PIXIS_SW2_LANE_45_SEL 0x40
273cba46148STimur Tabi #define PIXIS_SW2_LANE_67_SEL_MASK 0x30
274cba46148STimur Tabi #define PIXIS_SW2_LANE_67_SEL_5 0x00
275cba46148STimur Tabi #define PIXIS_SW2_LANE_67_SEL_6 0x20
276cba46148STimur Tabi #define PIXIS_SW2_LANE_67_SEL_7 0x10
277cba46148STimur Tabi #define PIXIS_SW2_LANE_8_SEL 0x08
278cba46148STimur Tabi #define PIXIS_SW2_LANE_1617_SEL 0x04
279cba46148STimur Tabi
280cba46148STimur Tabi /*
281cba46148STimur Tabi * Initialize the lane_to_slot[] array.
282cba46148STimur Tabi *
283cba46148STimur Tabi * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board
284cba46148STimur Tabi * slots is hard-coded. On the Hydra board, however, the mapping is controlled
285cba46148STimur Tabi * by board switch SW2, so the lane_to_slot[] array needs to be dynamically
286cba46148STimur Tabi * initialized.
287cba46148STimur Tabi */
initialize_lane_to_slot(void)288cba46148STimur Tabi static void initialize_lane_to_slot(void)
289cba46148STimur Tabi {
290cba46148STimur Tabi u8 sw2 = in_8(&PIXIS_SW(2));
291cba46148STimur Tabi
292cba46148STimur Tabi lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4;
293cba46148STimur Tabi lane_to_slot[3] = lane_to_slot[2];
294cba46148STimur Tabi
295cba46148STimur Tabi lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6;
296cba46148STimur Tabi lane_to_slot[5] = lane_to_slot[4];
297cba46148STimur Tabi
298cba46148STimur Tabi switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) {
299cba46148STimur Tabi case PIXIS_SW2_LANE_67_SEL_5:
300cba46148STimur Tabi lane_to_slot[6] = 5;
301cba46148STimur Tabi break;
302cba46148STimur Tabi case PIXIS_SW2_LANE_67_SEL_6:
303cba46148STimur Tabi lane_to_slot[6] = 6;
304cba46148STimur Tabi break;
305cba46148STimur Tabi case PIXIS_SW2_LANE_67_SEL_7:
306cba46148STimur Tabi lane_to_slot[6] = 7;
307cba46148STimur Tabi break;
308cba46148STimur Tabi }
309cba46148STimur Tabi lane_to_slot[7] = lane_to_slot[6];
310cba46148STimur Tabi
311cba46148STimur Tabi lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0;
312cba46148STimur Tabi
313cba46148STimur Tabi lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0;
314cba46148STimur Tabi lane_to_slot[17] = lane_to_slot[16];
315cba46148STimur Tabi }
316cba46148STimur Tabi
317cba46148STimur Tabi #endif /* #ifdef CONFIG_FMAN_ENET */
318cba46148STimur Tabi
319cba46148STimur Tabi /*
320cba46148STimur Tabi * Configure the status for the virtual MDIO nodes
321cba46148STimur Tabi *
322cba46148STimur Tabi * Rather than create the virtual MDIO nodes from scratch for each active
323cba46148STimur Tabi * virtual MDIO, we expect the DTS to have the nodes defined already, and we
324cba46148STimur Tabi * only enable the ones that are actually active.
325cba46148STimur Tabi *
326cba46148STimur Tabi * We assume that the DTS already hard-codes the status for all the
327cba46148STimur Tabi * virtual MDIO nodes to "disabled", so all we need to do is enable the
328cba46148STimur Tabi * active ones.
329cba46148STimur Tabi *
330cba46148STimur Tabi * For SGMII, we also need to set the mux value in the node.
331cba46148STimur Tabi */
fdt_fixup_board_enet(void * fdt)332cba46148STimur Tabi void fdt_fixup_board_enet(void *fdt)
333cba46148STimur Tabi {
334cba46148STimur Tabi #ifdef CONFIG_FMAN_ENET
335cba46148STimur Tabi unsigned int i;
336cba46148STimur Tabi int lane;
337cba46148STimur Tabi
338cba46148STimur Tabi for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
339cba46148STimur Tabi int idx = i - FM1_DTSEC1;
340cba46148STimur Tabi
341cba46148STimur Tabi switch (fm_info_get_enet_if(i)) {
342cba46148STimur Tabi case PHY_INTERFACE_MODE_SGMII:
343cba46148STimur Tabi lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
344cba46148STimur Tabi if (lane >= 0) {
3452a523f52SShengzhou Liu fdt_status_okay_by_alias(fdt, "emi1_sgmii");
346cba46148STimur Tabi /* Also set the MUX value */
347cba46148STimur Tabi fdt_set_mdio_mux(fdt, "emi1_sgmii",
348cba46148STimur Tabi mdio_mux[i].val);
349cba46148STimur Tabi }
350cba46148STimur Tabi break;
351cba46148STimur Tabi case PHY_INTERFACE_MODE_RGMII:
3522a523f52SShengzhou Liu fdt_status_okay_by_alias(fdt, "emi1_rgmii");
353cba46148STimur Tabi break;
354cba46148STimur Tabi default:
355cba46148STimur Tabi break;
356cba46148STimur Tabi }
357cba46148STimur Tabi }
358cba46148STimur Tabi
359cba46148STimur Tabi lane = serdes_get_first_lane(XAUI_FM1);
360cba46148STimur Tabi if (lane >= 0)
3612a523f52SShengzhou Liu fdt_status_okay_by_alias(fdt, "emi2_xgmii");
362cba46148STimur Tabi #endif
363cba46148STimur Tabi }
364cba46148STimur Tabi
board_eth_init(bd_t * bis)365cba46148STimur Tabi int board_eth_init(bd_t *bis)
366cba46148STimur Tabi {
367cba46148STimur Tabi #ifdef CONFIG_FMAN_ENET
368cba46148STimur Tabi struct fsl_pq_mdio_info dtsec_mdio_info;
369cba46148STimur Tabi struct tgec_mdio_info tgec_mdio_info;
370cba46148STimur Tabi unsigned int i, slot;
371cba46148STimur Tabi int lane;
372ffee1ddeSZhao Qiang struct mii_dev *bus;
373cba46148STimur Tabi
374cba46148STimur Tabi printf("Initializing Fman\n");
375cba46148STimur Tabi
376cba46148STimur Tabi initialize_lane_to_slot();
377cba46148STimur Tabi
378cba46148STimur Tabi /* We want to use the PIXIS to configure MUX routing, not GPIOs. */
379cba46148STimur Tabi setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL);
380cba46148STimur Tabi
381cba46148STimur Tabi memset(mdio_mux, 0, sizeof(mdio_mux));
382cba46148STimur Tabi
383cba46148STimur Tabi dtsec_mdio_info.regs =
384cba46148STimur Tabi (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
385cba46148STimur Tabi dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
386cba46148STimur Tabi
387cba46148STimur Tabi /* Register the real 1G MDIO bus */
388cba46148STimur Tabi fsl_pq_mdio_init(bis, &dtsec_mdio_info);
389cba46148STimur Tabi
390cba46148STimur Tabi tgec_mdio_info.regs =
391cba46148STimur Tabi (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
392cba46148STimur Tabi tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
393cba46148STimur Tabi
394cba46148STimur Tabi /* Register the real 10G MDIO bus */
395cba46148STimur Tabi fm_tgec_mdio_init(bis, &tgec_mdio_info);
396cba46148STimur Tabi
397cba46148STimur Tabi /* Register the three virtual MDIO front-ends */
398cba46148STimur Tabi hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_RGMII_MDIO");
399cba46148STimur Tabi hydra_mdio_init(DEFAULT_FM_MDIO_NAME, "HYDRA_SGMII_MDIO");
400cba46148STimur Tabi
401cba46148STimur Tabi /*
402cba46148STimur Tabi * Program the DTSEC PHY addresses assuming that they are all SGMII.
403cba46148STimur Tabi * For any DTSEC that's RGMII, we'll override its PHY address later.
404cba46148STimur Tabi * We assume that DTSEC5 is only used for RGMII.
405cba46148STimur Tabi */
406cba46148STimur Tabi fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
407cba46148STimur Tabi fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
408cba46148STimur Tabi fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
409cba46148STimur Tabi fm_info_set_phy_address(FM1_DTSEC4, CONFIG_SYS_FM1_DTSEC4_PHY_ADDR);
410cba46148STimur Tabi
411cba46148STimur Tabi for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
412cba46148STimur Tabi int idx = i - FM1_DTSEC1;
413cba46148STimur Tabi
414cba46148STimur Tabi switch (fm_info_get_enet_if(i)) {
415cba46148STimur Tabi case PHY_INTERFACE_MODE_SGMII:
416cba46148STimur Tabi lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx);
417cba46148STimur Tabi if (lane < 0)
418cba46148STimur Tabi break;
419cba46148STimur Tabi slot = lane_to_slot[lane];
420cba46148STimur Tabi mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
421cba46148STimur Tabi switch (slot) {
422cba46148STimur Tabi case 1:
423cba46148STimur Tabi /* Always DTSEC5 on Bank 3 */
424cba46148STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 |
425cba46148STimur Tabi BRDCFG1_EMI1_EN;
426cba46148STimur Tabi break;
427cba46148STimur Tabi case 2:
428cba46148STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 |
429cba46148STimur Tabi BRDCFG1_EMI1_EN;
430cba46148STimur Tabi break;
431cba46148STimur Tabi case 5:
432cba46148STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 |
433cba46148STimur Tabi BRDCFG1_EMI1_EN;
434cba46148STimur Tabi break;
435cba46148STimur Tabi case 6:
436cba46148STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 |
437cba46148STimur Tabi BRDCFG1_EMI1_EN;
438cba46148STimur Tabi break;
439cba46148STimur Tabi case 7:
440cba46148STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 |
441cba46148STimur Tabi BRDCFG1_EMI1_EN;
442cba46148STimur Tabi break;
443cba46148STimur Tabi };
444cba46148STimur Tabi
445cba46148STimur Tabi hydra_mdio_set_mux("HYDRA_SGMII_MDIO",
446cba46148STimur Tabi mdio_mux[i].mask, mdio_mux[i].val);
447cba46148STimur Tabi fm_info_set_mdio(i,
448cba46148STimur Tabi miiphy_get_dev_by_name("HYDRA_SGMII_MDIO"));
449cba46148STimur Tabi break;
450cba46148STimur Tabi case PHY_INTERFACE_MODE_RGMII:
451cba46148STimur Tabi /*
452cba46148STimur Tabi * If DTSEC4 is RGMII, then it's routed via via EC1 to
453cba46148STimur Tabi * the first on-board RGMII port. If DTSEC5 is RGMII,
454cba46148STimur Tabi * then it's routed via via EC2 to the second on-board
455cba46148STimur Tabi * RGMII port. The other DTSECs cannot be routed to
456cba46148STimur Tabi * RGMII.
457cba46148STimur Tabi */
458cba46148STimur Tabi fm_info_set_phy_address(i, i == FM1_DTSEC4 ? 0 : 1);
459cba46148STimur Tabi mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK;
460cba46148STimur Tabi mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII |
461cba46148STimur Tabi BRDCFG1_EMI1_EN;
462cba46148STimur Tabi hydra_mdio_set_mux("HYDRA_RGMII_MDIO",
463cba46148STimur Tabi mdio_mux[i].mask, mdio_mux[i].val);
464cba46148STimur Tabi fm_info_set_mdio(i,
465cba46148STimur Tabi miiphy_get_dev_by_name("HYDRA_RGMII_MDIO"));
466cba46148STimur Tabi break;
467cba46148STimur Tabi case PHY_INTERFACE_MODE_NONE:
468cba46148STimur Tabi fm_info_set_phy_address(i, 0);
469cba46148STimur Tabi break;
470cba46148STimur Tabi default:
471cba46148STimur Tabi printf("Fman1: DTSEC%u set to unknown interface %i\n",
472cba46148STimur Tabi idx + 1, fm_info_get_enet_if(i));
473cba46148STimur Tabi fm_info_set_phy_address(i, 0);
474cba46148STimur Tabi break;
475cba46148STimur Tabi }
476cba46148STimur Tabi }
477cba46148STimur Tabi
478ffee1ddeSZhao Qiang bus = miiphy_get_dev_by_name("HYDRA_SGMII_MDIO");
479ffee1ddeSZhao Qiang set_sgmii_phy(bus, FM1_DTSEC1, CONFIG_SYS_NUM_FM1_DTSEC, PHY_BASE_ADDR);
480ffee1ddeSZhao Qiang
481cba46148STimur Tabi /*
482cba46148STimur Tabi * For 10G, we only support one XAUI card per Fman. If present, then we
483cba46148STimur Tabi * force its routing and never touch those bits again, which removes the
484cba46148STimur Tabi * need for Linux to do any muxing. This works because of the way
485cba46148STimur Tabi * BRDCFG1 is defined, but it's a bit hackish.
486cba46148STimur Tabi *
487cba46148STimur Tabi * The PHY address for the XAUI card depends on which slot it's in. The
488cba46148STimur Tabi * macros we use imply that the PHY address is based on which FM, but
489cba46148STimur Tabi * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5,
490cba46148STimur Tabi * and FM2 could only use a XAUI in slot 4. On the Hydra board, we
491cba46148STimur Tabi * check the actual slot and just use the macros as-is, even though
492cba46148STimur Tabi * the P3041 and P5020 only have one Fman.
493cba46148STimur Tabi */
494cba46148STimur Tabi lane = serdes_get_first_lane(XAUI_FM1);
495cba46148STimur Tabi if (lane >= 0) {
496cba46148STimur Tabi slot = lane_to_slot[lane];
497cba46148STimur Tabi if (slot == 1) {
498cba46148STimur Tabi /* XAUI card is in slot 1 */
499cba46148STimur Tabi clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
500cba46148STimur Tabi BRDCFG1_EMI2_SEL_SLOT1);
501cba46148STimur Tabi fm_info_set_phy_address(FM1_10GEC1,
502cba46148STimur Tabi CONFIG_SYS_FM1_10GEC1_PHY_ADDR);
503cba46148STimur Tabi } else {
504cba46148STimur Tabi /* XAUI card is in slot 2 */
505cba46148STimur Tabi clrsetbits_8(&pixis->brdcfg1, BRDCFG1_EMI2_SEL_MASK,
506cba46148STimur Tabi BRDCFG1_EMI2_SEL_SLOT2);
507cba46148STimur Tabi fm_info_set_phy_address(FM1_10GEC1,
508cba46148STimur Tabi CONFIG_SYS_FM2_10GEC1_PHY_ADDR);
509cba46148STimur Tabi }
510cba46148STimur Tabi }
511cba46148STimur Tabi
512cba46148STimur Tabi fm_info_set_mdio(FM1_10GEC1,
513cba46148STimur Tabi miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME));
514cba46148STimur Tabi
515cba46148STimur Tabi cpu_eth_init(bis);
516cba46148STimur Tabi #endif
517cba46148STimur Tabi
518cba46148STimur Tabi return pci_eth_init(bis);
519cba46148STimur Tabi }
520