Home
last modified time | relevance | path

Searched +full:msm +full:- +full:uartdm (Results 1 – 25 of 35) sorted by relevance

12

/openbmc/linux/Documentation/devicetree/bindings/serial/
H A Dqcom,msm-uartdm.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM Serial UARTDM
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
15 The MSM serial UARTDM hardware is designed for high-speed use cases where the
16 transmit and/or receive channels can be offloaded to a dma-engine. From a
[all …]
H A Dqcom,msm-uart.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/serial/qcom,msm-uart.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm MSM SoC Serial UART
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
14 The MSM serial UART hardware is designed for low-speed use cases where a
15 dma-engine isn't needed. From a software perspective it's mostly compatible
16 with the MSM serial UARTDM except that it only supports reading and writing
[all …]
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dipq9574.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&intc>;
17 #address-cells = <2>;
18 #size-cells = <2>;
[all …]
H A Dipq5332.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <dt-bindings/clock/qcom,apss-ipq.h>
9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 sleep_clk: sleep-clk {
19 compatible = "fixed-clock";
[all …]
H A Dipq5018.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-ipq5018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq5018.h>
13 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 sleep_clk: sleep-clk {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
[all …]
H A Dqcs404.dtsi1 // SPDX-License-Identifier: GPL-2.0
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
8 #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/power/qcom-rpmpd.h>
11 #include <dt-bindings/thermal/thermal.h>
14 interrupt-parent = <&intc>;
16 #address-cells = <2>;
17 #size-cells = <2>;
[all …]
H A Dipq8074.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
15 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
20 clock-frequency = <32768>;
21 #clock-cells = <0>;
25 compatible = "fixed-clock";
[all …]
H A Dmsm8976.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
[all …]
H A Dmsm8994.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
14 interrupt-parent = <&intc>;
16 #address-cells = <2>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/qcom/
H A Dqcom,gsbi.yaml1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andy Gross <agross@kernel.org>
11 - Bjorn Andersson <bjorn.andersson@linaro.org>
12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
16 representing a serial sub-node device that is mux'd as part of the GSBI
26 const: qcom,gsbi-v1.0.0
28 '#address-cells':
31 cell-index:
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Ddragonboard820c.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
8 /dts-v1/;
11 #include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
15 compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
16 #address-cells = <2>;
17 #size-cells = <2>;
24 stdout-path = "serial0:115200n8";
32 reserved-memory {
33 #address-cells = <2>;
[all …]
H A Ddragonboard410c.dts1 // SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
11 #include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
15 compatible = "qcom,dragonboard", "qcom,apq8016-sbc";
16 qcom,msm-id = <0xce 0x0 0xf8 0x0 0xf9 0x0 0xfa 0x0 0xf7 0x0>;
17 qcom,board-id = <0x10018 0x0>;
18 #address-cells = <0x2>;
19 #size-cells = <0x2>;
30 reserved-memory {
31 #address-cells = <2>;
[all …]
/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8660.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8660.h>
7 #include <dt-bindings/soc/qcom,gsbi.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 interrupt-parent = <&intc>;
17 #address-cells = <1>;
[all …]
H A Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
[all …]
H A Dqcom-msm8226.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
17 #address-cells = <1>;
[all …]
H A Dqcom-mdm9615.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
9 /dts-v1/;
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h>
13 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
14 #include <dt-bindings/reset/qcom,gcc-mdm9615.h>
15 #include <dt-bindings/mfd/qcom-rpm.h>
16 #include <dt-bindings/soc/qcom,gsbi.h>
19 #address-cells = <1>;
20 #size-cells = <1>;
[all …]
H A Dqcom-apq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
5 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
[all …]
H A Dqcom-ipq4019.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/clock/qcom,gcc-ipq4019.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
13 #address-cells = <1>;
14 #size-cells = <1>;
18 interrupt-parent = <&intc>;
20 reserved-memory {
21 #address-cells = <0x1>;
[all …]
H A Dqcom-msm8974.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interconnect/qcom,msm8974.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
10 #include <dt-bindings/gpio/gpio.h>
13 #address-cells = <1>;
[all …]
H A Dqcom-msm8960.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
7 #include <dt-bindings/clock/qcom,lcc-msm8960.h>
8 #include <dt-bindings/mfd/qcom-rpm.h>
9 #include <dt-bindings/soc/qcom,gsbi.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
[all …]
H A Dqcom-sdx65.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
[all …]
H A Dqcom-apq8084.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&intc>;
15 reserved-memory {
16 #address-cells = <1>;
[all …]
/openbmc/u-boot/doc/device-tree-bindings/serial/
H A Dmsm-serial.txt4 - compatible: must be "qcom,msm-uartdm-v1.4"
5 - reg: start address and size of the registers
6 - clock: interface clock (must accept baudrate as a frequency)
/openbmc/linux/drivers/tty/serial/
H A Dmsm_serial.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/dma-mapping.h>
192 writel_relaxed(val, port->membase + off); in msm_write()
198 return readl_relaxed(port->membase + off); in msm_read()
210 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxo()
222 port->uartclk = 1843200; in msm_serial_set_mnd_regs_tcxoby4()
231 * on uartdm hardware instead in msm_serial_set_mnd_regs()
233 if (msm_port->is_uartdm) in msm_serial_set_mnd_regs()
236 if (port->uartclk == 19200000) in msm_serial_set_mnd_regs()
238 else if (port->uartclk == 4800000) in msm_serial_set_mnd_regs()
[all …]
/openbmc/u-boot/drivers/serial/
H A Dserial_msm.c1 // SPDX-License-Identifier: GPL-2.0+
21 /* Serial registers - this driver works in uartdm mode*/
70 if (priv->chars_cnt) in msm_serial_fetch()
71 return priv->chars_cnt; in msm_serial_fetch()
74 if (readl(priv->base + UARTDM_SR) & UARTDM_SR_UART_OVERRUN) in msm_serial_fetch()
75 writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR); in msm_serial_fetch()
78 sr = readl(priv->base + UARTDM_SR); in msm_serial_fetch()
82 priv->chars_buf = readl(priv->base + UARTDM_RF); in msm_serial_fetch()
83 priv->chars_cnt = 4; in msm_serial_fetch()
86 priv->chars_cnt = readl(priv->base + UARTDM_RXFS); in msm_serial_fetch()
[all …]

12