1*a5b7063fSKrzysztof Kozlowski# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2*a5b7063fSKrzysztof Kozlowski%YAML 1.2 3*a5b7063fSKrzysztof Kozlowski--- 4*a5b7063fSKrzysztof Kozlowski$id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml# 5*a5b7063fSKrzysztof Kozlowski$schema: http://devicetree.org/meta-schemas/core.yaml# 6*a5b7063fSKrzysztof Kozlowski 7*a5b7063fSKrzysztof Kozlowskititle: Qualcomm MSM Serial UARTDM 8*a5b7063fSKrzysztof Kozlowski 9*a5b7063fSKrzysztof Kozlowskimaintainers: 10*a5b7063fSKrzysztof Kozlowski - Andy Gross <agross@kernel.org> 11*a5b7063fSKrzysztof Kozlowski - Bjorn Andersson <bjorn.andersson@linaro.org> 12*a5b7063fSKrzysztof Kozlowski - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 13*a5b7063fSKrzysztof Kozlowski 14*a5b7063fSKrzysztof Kozlowskidescription: | 15*a5b7063fSKrzysztof Kozlowski The MSM serial UARTDM hardware is designed for high-speed use cases where the 16*a5b7063fSKrzysztof Kozlowski transmit and/or receive channels can be offloaded to a dma-engine. From a 17*a5b7063fSKrzysztof Kozlowski software perspective it's mostly compatible with the MSM serial UART except 18*a5b7063fSKrzysztof Kozlowski that it supports reading and writing multiple characters at a time. 19*a5b7063fSKrzysztof Kozlowski 20*a5b7063fSKrzysztof Kozlowski Note:: Aliases may be defined to ensure the correct ordering of the UARTs. 21*a5b7063fSKrzysztof Kozlowski The alias serialN will result in the UART being assigned port N. If any 22*a5b7063fSKrzysztof Kozlowski serialN alias exists, then an alias must exist for each enabled UART. The 23*a5b7063fSKrzysztof Kozlowski serialN aliases should be in a .dts file instead of in a .dtsi file. 24*a5b7063fSKrzysztof Kozlowski 25*a5b7063fSKrzysztof Kozlowskiproperties: 26*a5b7063fSKrzysztof Kozlowski compatible: 27*a5b7063fSKrzysztof Kozlowski items: 28*a5b7063fSKrzysztof Kozlowski - enum: 29*a5b7063fSKrzysztof Kozlowski - qcom,msm-uartdm-v1.1 30*a5b7063fSKrzysztof Kozlowski - qcom,msm-uartdm-v1.2 31*a5b7063fSKrzysztof Kozlowski - qcom,msm-uartdm-v1.3 32*a5b7063fSKrzysztof Kozlowski - qcom,msm-uartdm-v1.4 33*a5b7063fSKrzysztof Kozlowski - const: qcom,msm-uartdm 34*a5b7063fSKrzysztof Kozlowski 35*a5b7063fSKrzysztof Kozlowski clocks: 36*a5b7063fSKrzysztof Kozlowski maxItems: 2 37*a5b7063fSKrzysztof Kozlowski 38*a5b7063fSKrzysztof Kozlowski clock-names: 39*a5b7063fSKrzysztof Kozlowski items: 40*a5b7063fSKrzysztof Kozlowski - const: core 41*a5b7063fSKrzysztof Kozlowski - const: iface 42*a5b7063fSKrzysztof Kozlowski 43*a5b7063fSKrzysztof Kozlowski dmas: 44*a5b7063fSKrzysztof Kozlowski maxItems: 2 45*a5b7063fSKrzysztof Kozlowski 46*a5b7063fSKrzysztof Kozlowski dma-names: 47*a5b7063fSKrzysztof Kozlowski items: 48*a5b7063fSKrzysztof Kozlowski - const: tx 49*a5b7063fSKrzysztof Kozlowski - const: rx 50*a5b7063fSKrzysztof Kozlowski 51*a5b7063fSKrzysztof Kozlowski interrupts: 52*a5b7063fSKrzysztof Kozlowski maxItems: 1 53*a5b7063fSKrzysztof Kozlowski 54*a5b7063fSKrzysztof Kozlowski qcom,rx-crci: 55*a5b7063fSKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 56*a5b7063fSKrzysztof Kozlowski description: 57*a5b7063fSKrzysztof Kozlowski Identificator for Client Rate Control Interface to be used with RX DMA 58*a5b7063fSKrzysztof Kozlowski channel. Required when using DMA for reception with UARTDM v1.3 and 59*a5b7063fSKrzysztof Kozlowski below. 60*a5b7063fSKrzysztof Kozlowski 61*a5b7063fSKrzysztof Kozlowski qcom,tx-crci: 62*a5b7063fSKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 63*a5b7063fSKrzysztof Kozlowski description: 64*a5b7063fSKrzysztof Kozlowski Identificator for Client Rate Control Interface to be used with TX DMA 65*a5b7063fSKrzysztof Kozlowski channel. Required when using DMA for transmission with UARTDM v1.3 and 66*a5b7063fSKrzysztof Kozlowski below. 67*a5b7063fSKrzysztof Kozlowski 68*a5b7063fSKrzysztof Kozlowski reg: 69*a5b7063fSKrzysztof Kozlowski minItems: 1 70*a5b7063fSKrzysztof Kozlowski items: 71*a5b7063fSKrzysztof Kozlowski - description: Main control registers 72*a5b7063fSKrzysztof Kozlowski - description: An optional second register location shall specify the GSBI control region. 73*a5b7063fSKrzysztof Kozlowski 74*a5b7063fSKrzysztof Kozlowskirequired: 75*a5b7063fSKrzysztof Kozlowski - compatible 76*a5b7063fSKrzysztof Kozlowski - clock-names 77*a5b7063fSKrzysztof Kozlowski - clocks 78*a5b7063fSKrzysztof Kozlowski - interrupts 79*a5b7063fSKrzysztof Kozlowski - reg 80*a5b7063fSKrzysztof Kozlowski 81*a5b7063fSKrzysztof KozlowskiunevaluatedProperties: false 82*a5b7063fSKrzysztof Kozlowski 83*a5b7063fSKrzysztof KozlowskiallOf: 84*a5b7063fSKrzysztof Kozlowski - $ref: /schemas/serial/serial.yaml# 85*a5b7063fSKrzysztof Kozlowski 86*a5b7063fSKrzysztof Kozlowski - if: 87*a5b7063fSKrzysztof Kozlowski properties: 88*a5b7063fSKrzysztof Kozlowski compatible: 89*a5b7063fSKrzysztof Kozlowski contains: 90*a5b7063fSKrzysztof Kozlowski const: qcom,msm-uartdm-v1.3 91*a5b7063fSKrzysztof Kozlowski then: 92*a5b7063fSKrzysztof Kozlowski properties: 93*a5b7063fSKrzysztof Kozlowski reg: 94*a5b7063fSKrzysztof Kozlowski minItems: 2 95*a5b7063fSKrzysztof Kozlowski else: 96*a5b7063fSKrzysztof Kozlowski properties: 97*a5b7063fSKrzysztof Kozlowski reg: 98*a5b7063fSKrzysztof Kozlowski maxItems: 1 99*a5b7063fSKrzysztof Kozlowski 100*a5b7063fSKrzysztof Kozlowskiexamples: 101*a5b7063fSKrzysztof Kozlowski - | 102*a5b7063fSKrzysztof Kozlowski #include <dt-bindings/interrupt-controller/arm-gic.h> 103*a5b7063fSKrzysztof Kozlowski 104*a5b7063fSKrzysztof Kozlowski serial@f991e000 { 105*a5b7063fSKrzysztof Kozlowski compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 106*a5b7063fSKrzysztof Kozlowski reg = <0xf991e000 0x1000>; 107*a5b7063fSKrzysztof Kozlowski interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 108*a5b7063fSKrzysztof Kozlowski clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>; 109*a5b7063fSKrzysztof Kozlowski clock-names = "core", "iface"; 110*a5b7063fSKrzysztof Kozlowski dmas = <&dma0 0>, <&dma0 1>; 111*a5b7063fSKrzysztof Kozlowski dma-names = "tx", "rx"; 112*a5b7063fSKrzysztof Kozlowski }; 113