| /openbmc/u-boot/arch/arm/mach-bcm283x/ |
| H A D | Kconfig | 17 bool "Broadcom BCM2837 SoC 32-bit support"
24 bool "Broadcom BCM2837 SoC 64-bit support"
39 Support for all ARM1176-/BCM2835-based Raspberry Pi variants, such as
41 support BCM2836/BCM2837-based Raspberry Pis such as the RPi 2 and
50 Support for all ARM1176-/BCM2835-based Raspberry Pi variants, such as
56 non-default option must be present in config.txt: enable_uart=1.
57 This is required for U-Boot to operate correctly, even if you only
66 Support for all BCM2836-based Raspberry Pi variants, such as
69 This option also supports BCM2837-based variants such as the RPi 3
70 Model B, when run in 32-bit mode, provided you have configured the
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|
| /openbmc/docs/designs/ |
| H A D | thermal-control-modes.md | 7 Created: 2019-02-06
17 optical cables plugged into a card downwind from the GPUs' exhaust, an end-user
31 exists on other system where mathematical calculations are done based on the
35 <https://github.com/openbmc/dbus-sensors/blob/master/src/ExitAirTempSensor.cpp>
39 Create the ability for an end-user to enable the use of a thermal control mode
40 other than the default. In this use-case, the mode is specific to an
42 standardized profile/modes such "Acoustic" and "Performance". Once the end-user
43 selects a documented mode for the platform, the thermal control application
44 alters its control algorithm according to the defined mode, which is
50 available thermal control modes along with what current mode is in use.
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|
| /openbmc/phosphor-settingsd/ |
| H A D | README-settings-manager.md | 7 - Each setting should be a distinct D-Bus object.
9 - The above makes it possible to not even create settings objects that do not
12 - It should be possible, for example, for host0/ and host1/ on a system with two
16 - It should be possible to specify default settings for a system at build-time,
17 based on which the settings manager should at run-time create appropriate
18 D-Bus objects and place them on the bus.
23 in YAML. Based on this policy file, the settings manager code is generated to be
24 able to create only relevant settings D-Bus objects along with specifying their
31 Interface: xyz.openbmc_project.Control.Boot.Mode
33 BootMode: Mode::Modes::Regular
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|
| /openbmc/entity-manager/docs/ |
| H A D | address_size_detection_modes.md | 6 ## MODE-1
8 The existing upstream function isDevice16Bit() bases on sending 1-byte write
9 operation (with a STOP condition) and 8 subsequent 1-byte read operations with
12 ### This MODE-1 expects the following logic
14 - If the device requires 1 address byte, it EXPECTS that the data will be read
16 - If the device requires 2 address bytes, it EXPECTS that the data will be read
20 ### Issue and potential issue with this MODE-1
22 - If any "2 address bytes" EEPROM from any vendor has the same data in all
23 memory locations (0-7) the existing upstream function read, this device will
26 - ONSEMI EEPROM (a 2 address bytes device) return the same data from the same
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|
| /openbmc/u-boot/board/gateworks/gw_ventana/ |
| H A D | README | 1 U-Boot for the Gateworks Ventana Product Family boards
3 This file contains information for the port of U-Boot to the Gateworks
7 is supported by a single bootloader build by using a common SPL and U-Boot
13 ---------------------------------
19 will build the following artifacts from U-Boot source:
20 - SPL - Secondary Program Loader that the i.MX6 BOOT ROM (Primary Program
22 The DRAM controller, loads u-boot.img from the detected boot device,
25 - u-boot.img - The main U-Boot core which is u-boot.bin with a image header.
29 --------
31 To build U-Boot for the Gateworks Ventana product family:
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|
| /openbmc/openbmc/meta-openembedded/meta-oe/recipes-extended/newt/ |
| H A D | libnewt_0.52.25.bb | 1 SUMMARY = "A library for text mode user interfaces"
3 DESCRIPTION = "Newt is a programming library for color text mode, widget based user \
6 etc., to text mode user interfaces. This package also contains the \
8 /usr/bin/dialog replacement called whiptail. Newt is based on the \
14 LICENSE = "LGPL-2.0-only"
20 SRC_URI = "https://releases.pagure.org/newt/newt-${PV}.tar.gz \
22 file://Makefile.in-Add-tinfo-library-to-the-linking-librari.patch \
27 S = "${WORKDIR}/newt-${PV}"
29 inherit autotools-brokensep python3native python3-dir python3targetconfig
31 EXTRA_OECONF = "--without-tcl --with-python"
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|
| /openbmc/u-boot/drivers/mmc/ |
| H A D | mmc_boot.c | 1 // SPDX-License-Identifier: GPL-2.0+
29 /* Only use this command for raw EMMC moviNAND. Enter backdoor mode */ in mmc_boot_partition_size_change()
40 /* Boot partition changing mode */ in mmc_boot_partition_size_change()
80 * based on the passed in values for BOOT_BUS_WIDTH, RESET_BOOT_BUS_WIDTH
85 int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode) in mmc_set_boot_bus_width() argument
88 EXT_CSD_BOOT_BUS_WIDTH_MODE(mode) | in mmc_set_boot_bus_width()
95 * based on the passed in values for BOOT_ACK, BOOT_PARTITION_ENABLE and
112 mmc->part_config = part_conf; in mmc_set_part_conf()
118 * Modify EXT_CSD[162] which is RST_n_FUNCTION based on the given value
119 * for enable. Note that this is a write-once field for non-zero values.
|
| H A D | Kconfig | 31 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
32 and non-removable (e.g. eMMC chip) devices are supported. These
33 appear as block devices in U-Boot and can support filesystems such
42 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
43 and non-removable (e.g. eMMC chip) devices are supported. These
44 appear as block devices in U-Boot and can support filesystems such
118 The HS400 mode is support by some eMMC. The bus frequency is up to
119 200MHz. This mode requires tuning the IO.
124 The HS400 mode is support by some eMMC. The bus frequency is up to
125 200MHz. This mode requires tuning the IO.
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|
| /openbmc/u-boot/doc/device-tree-bindings/net/ |
| H A D | altera_tse.txt | 1 * Altera Triple-Speed Ethernet MAC driver (TSE)
4 - compatible: Should be "altr,tse-1.0" for legacy SGDMA based TSE, and should
5 be "altr,tse-msgdma-1.0" for the preferred MSGDMA based TSE.
6 - reg: Address and length of the register set for the device. It contains
7 the information of registers in the same order as described by reg-names
8 - reg-names: Should contain the reg names
16 - interrupts: Should contain the TSE interrupts and it's mode.
17 - interrupt-names: Should contain the interrupt names
20 - rx-fifo-depth: MAC receive FIFO buffer depth in bytes
21 - tx-fifo-depth: MAC transmit FIFO buffer depth in bytes
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|
| /openbmc/u-boot/drivers/gpio/ |
| H A D | kw_gpio.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * arch/arm/plat-orion/gpio.c
9 * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
12 * Dieter Kiermaier dk-arm-linux@gmx.de
62 int kw_gpio_is_valid(unsigned pin, int mode) in kw_gpio_is_valid() argument
65 if ((mode & GPIO_INPUT_OK) && !test_bit(pin, gpio_valid_input)) in kw_gpio_is_valid()
68 if ((mode & GPIO_OUTPUT_OK) && !test_bit(pin, gpio_valid_output)) in kw_gpio_is_valid()
78 void kw_gpio_set_valid(unsigned pin, int mode) in kw_gpio_set_valid() argument
80 if (mode == 1) in kw_gpio_set_valid()
81 mode = GPIO_INPUT_OK | GPIO_OUTPUT_OK; in kw_gpio_set_valid()
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|
| /openbmc/qemu/docs/ |
| H A D | glossary.rst | 3 --------
5 --------
11 -----------
14 hardware-based, through a virtualization API provided by the host OS (kvm, hvf,
15 whpx, ...), or software-based (tcg). See this description of `supported
19 -----
24 -----
26 Block drivers are the available `disk formats and front-ends
27 <block-drivers>` available, and block devices `(see Block device section on
32 ---
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|
| /openbmc/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | mipi_dsim.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
62 /* MIPI DSI Processor-to-Peripheral transaction types */
111 * struct mipi_dsim_config - interface for configuring mipi-dsi controller.
114 * @eot_disable: enable or disable EoT packet in HS mode.
115 * @auto_vertical_cnt: specifies auto vertical count mode.
116 * in Video mode, the vertical line transition uses line counter
119 * registers.(in command mode, this variable is ignored)
120 * @hse: set horizontal sync event mode.
124 * (in mommand mode, this variable is ignored)
125 * @hfp: specifies HFP disable mode.
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|
| /openbmc/qemu/hw/9pfs/ |
| H A D | 9p-util-darwin.c | 5 * See the COPYING file in the top-level directory.
11 #include "qemu/error-report.h"
12 #include "9p-util.h"
20 if (fd == -1) { in fgetxattrat_nofollow()
21 return -1; in fgetxattrat_nofollow()
34 if (fd == -1) { in flistxattrat_nofollow()
35 return -1; in flistxattrat_nofollow()
47 if (fd == -1) { in fremovexattrat_nofollow()
48 return -1; in fremovexattrat_nofollow()
60 if (fd == -1) { in fsetxattrat_nofollow()
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|
| /openbmc/qemu/target/i386/tcg/ |
| H A D | decode-new.h | 2 * Decode table flags, mostly based on Intel SDM.
35 X86_TYPE_L, /* The upper 4 bits of the immediate select a 128-bit register */
52 X86_TYPE_I_unsigned, /* Immediate, zero-extended */
53 X86_TYPE_nop, /* modrm operand decoded but not loaded into s->T{0,1} */
54 X86_TYPE_2op, /* 2-operand RMW instruction */
55 X86_TYPE_LoBits, /* encoded in bits 0-2 of the operand + REX.B */
56 X86_TYPE_0, /* Hard-coded GPRs (RAX..RDI) */
64 X86_TYPE_ES, /* Hard-coded segment registers */
77 X86_SIZE_d, /* 32-bit */
78 X86_SIZE_dq, /* SSE/AVX 128-bit */
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|
| /openbmc/qemu/docs/system/arm/ |
| H A D | xlnx-zynq.rst | 1 Xilinx Zynq board (``xilinx-zynq-a9``)
3 The Zynq 7000 family is based on the AMD SoC architecture. These products
4 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based
8 https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual
10 QEMU xilinx-zynq-a9 board supports following devices:
11 - A9 MPCORE
12 - cortex-a9
13 - GIC v1
14 - Generic timer
15 - wdt
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|
| /openbmc/openpower-occ-control/ |
| H A D | README.md | 3 This service will handle communications to the On-Chip Controller (OCC) on Power
5 power cap support, system power mode support, and idle power saver support. OCC
7 readings, updating the system power mode, setting power caps, and idle power
15 builddir && ninja -C builddir.
33 IBM EnergyScale for Power10 Processor-Based Systems whitepaper:
37 <https://github.com/open-power/docs/blob/P10/occ/OCC_P10_FW_Interfaces_v1_17.pdf>
39 OCC Firmware: <https://github.com/open-power/occ/tree/master-p10>
43 IBM EnergyScale for POWER9 Processor-Based Systems:
44 <https://www-01.ibm.com/common/ssi/cgi-bin/ssialias?htmlfid=49019149USEN&>
47 <https://github.com/open-power/docs/blob/P9/occ/OCC_P9_FW_Interfaces.pdf>
|
| /openbmc/u-boot/arch/arm/mach-kirkwood/include/mach/ |
| H A D | gpio.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * arch/asm-arm/mach-kirkwood/include/mach/gpio.h
7 * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
11 * Dieter Kiermaier dk-arm-linux@gmx.de
29 * Kirkwood-specific GPIO API
32 void kw_gpio_set_valid(unsigned pin, int mode);
33 int kw_gpio_is_valid(unsigned pin, int mode);
|
| /openbmc/u-boot/arch/arc/ |
| H A D | Kconfig | 23 ISA for the Next Generation ARC-HS cores
37 Choose this option to build an U-Boot for ARC750D CPU.
44 Choose this option to build an U-Boot for ARC770D CPU.
51 Next Generation ARC Core based on ISA-v2 ISA without MMU.
58 Next Generation ARC Core based on ISA-v2 ISA without MMU.
65 Next Generation ARC Core based on ISA-v2 ISA with MMU.
86 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
87 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
94 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
106 bool "Enable Big Endian Mode"
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|
| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Control/Power/ |
| H A D | Mode.interface.yaml | 2 Customer requested system power mode.
5 - name: PowerMode
9 This property shall contain the computer system power mode setting.
10 This defines the processor speed based on the priority of power
13 - xyz.openbmc_project.Common.Error.InvalidArgument
14 - xyz.openbmc_project.Common.Error.NotAllowed
16 - name: SafeMode
19 - readonly
22 This property shall indicate whether the System is in Safe Mode. When
23 this is true, the system power mode is not being used in the system.
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|
| /openbmc/u-boot/drivers/usb/musb-new/ |
| H A D | Kconfig | 7 bool "MUSB host mode support"
11 Enables the MUSB USB dual-role controller in host mode.
14 bool "MUSB gadget mode support"
19 Enables the MUSB USB dual-role controller in gadget mode.
27 speed USB controller based on the Mentor Graphics
53 ---help---
|
| /openbmc/phosphor-dbus-interfaces/yaml/xyz/openbmc_project/Control/Security/ |
| H A D | RestrictionMode.interface.yaml | 2 Implement to specify a restricted mode of operation.
5 - name: RestrictionMode
8 The restriction mode.
11 - name: Modes
15 - name: None
18 - name: Allowlist
21 - name: Blocklist
24 - name: Provisioning
26 Indicate that system is in provisioning mode and all commands
28 - name: ProvisionedHostAllowlist
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|
| /openbmc/qemu/include/exec/ |
| H A D | icount.h | 2 * icount - Instruction Counter API
6 * SPDX-License-Identifier: GPL-2.0-or-later
15 * @ICOUNT_DISABLED: Disabled - Do not count executed instructions.
16 * @ICOUNT_PRECISE: Enabled - Fixed conversion of insn to ns via "shift" option
17 * @ICOUNT_ADAPTATIVE: Enabled - Runtime adaptive algorithm to compute shift
42 * cpus-tcg vCPU thread so the main-loop can see time has moved forward.
49 /* return the virtual CPU time in ns, based on the instruction counter. */
52 * convert an instruction counter value to ns, based on the icount shift.
54 * (precise mode), or it is constantly approximated and corrected at
55 * runtime in adaptive mode.
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|
| /openbmc/u-boot/arch/arm/mach-rockchip/ |
| H A D | Kconfig | 11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
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|
| /openbmc/qemu/scripts/kvm/ |
| H A D | vmxcap | 5 # Copyright 2009-2010 Red Hat, Inc.
11 # the COPYING file in the top-level directory.
74 print(' %-40s %s' % (self.bits[bit], s))
76 # All 64 bits in the tertiary controls MSR are allowed-1
105 v = (value >> lo) & ((1 << (hi - lo + 1)) - 1)
106 print(' %-40s %s' % (self.bits[bits], fmt(v)))
115 49: 'Dual-monitor support',
125 name = 'pin-based controls',
130 6: 'Activate VMX-preemption timer',
138 name = 'primary processor-based controls',
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|
| /openbmc/phosphor-fan-presence/control/ |
| H A D | manager.hpp | 36 * Creates the Zone objects based on the
39 * @param[in] bus - The dbus object
40 * @param[in] event - The event loop
41 * @param[in] mode - The control mode
43 Manager(sdbusplus::bus_t& bus, const sdeventplus::Event& event, Mode mode);
|