Home
last modified time | relevance | path

Searched +full:miso +full:- +full:pins (Results 1 – 25 of 85) sorted by relevance

1234

/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8192-asurada.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/spmi/spmi.h>
25 stdout-path = "serial0:115200n8";
33 backlight_lcd0: backlight-lcd0 {
34 compatible = "pwm-backlight";
36 power-supply = <&ppvar_sys>;
37 enable-gpios = <&pio 152 0>;
38 brightness-levels = <0 1023>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dmarvell,kirkwood-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6180-pinctrl",
8 "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
9 "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl",
10 "marvell,98dx4122-pinctrl", "marvell,98dx1135-pinctrl"
11 - reg: register specifier of MPP registers
14 It also support the 88f6281-based variant in the 98dx412x Bobcat SoCs.
16 Available mpp pins/groups and functions:
22 name pins functions
27 mpp3 3 gpo, nand(io5), spi(miso)
[all …]
H A Dmarvell,dove-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,dove-pinctrl"
8 - clocks: (optional) phandle of pdma clock
9 - reg: register specifiers of MPP, MPP4, and PMU MPP registers
11 Available mpp pins/groups and functions:
16 name pins functions
23 uart1(cts), lcd-spi(cs1), pmu*
24 mpp4 4 gpio, pmu, uart3(rts), sdio1(cd), spi1(miso), pmu*
31 mpp11 11 gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
39 mpp16 16 gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
[all …]
H A Dmarvell,armada-370-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6710-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
14 name pins functions
20 mpp4 4 gpio, vdd(cpu-pd)
35 mpp15 15 gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
47 mpp26 26 gpio, ge0(crs), ge1(rxd1), spi1(miso)
57 mpp36 36 gpo, dev(a1), spi0(miso)
73 mpp50 50 gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
[all …]
H A Dmarvell,armada-375-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6720-pinctrl"
8 - reg: register specifier of MPP registers
10 Available mpp pins/groups and functions:
14 name pins functions
20 mpp4 4 gpio, dev(ad6), spi0(miso), spi1(miso)
49 mpp33 33 gpio, ge1(txd3), spi1(miso)
H A Dmarvell,armada-38x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6810-pinctrl", "marvell,88f6820-pinctrl" or
8 "marvell,88f6828-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
16 name pins functions
34 mpp16 16 gpio, ge0(rxctl), ge(mdio slave), dram(deccerr), spi0(miso), pcie0(clkreq), …
42 mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
76 mpp58 58 gpio, pcie1(clkreq) [1], i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(…
H A Dmarvell,armada-39x-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,88f6920-pinctrl", "marvell,88f6925-pinctrl" or
8 "marvell,88f6928-pinctrl" depending on the specific variant of the
10 - reg: register specifier of MPP registers
12 Available mpp pins/groups and functions:
16 name pins functions
34 mpp16 16 gpio, dram(deccerr), spi0(miso), pcie0(clkreq), i2c1(sda)
43 mpp24 24 gpio, spi0(miso), ua0(cts), ua1(rxd), sd0(d4), dev(ready)
80 mpp58 58 gpio, i2c1(sck), pcie2(clkreq), spi1(miso), sd0(d1), ua1(rxd)
H A Dmarvell,armada-xp-pinctrl.txt3 Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
7 - compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
8 "marvell,mv78460-pinctrl"
9 - reg: register specifier of MPP registers
13 Available mpp pins/groups and functions:
19 name pins functions
38 mpp17 17 gpio, ge0(col), ge1(txctl), spi1(miso), lcd(d17)
50 mpp29 29 gpio, lcd(ref-clk), tdm(int0), ptp(clk)
58 mpp37 37 gpio, spi0(miso)
61 mpp40 40 gpio, spi0(cs1), uart2(cts), lcd(vga-hsync), pcie(clkreq0),
[all …]
H A Dqcom,msm8960-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8960-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18 const: qcom,msm8960-pinctrl
26 interrupt-controller: true
27 "#interrupt-cells": true
28 gpio-controller: true
[all …]
H A Dmediatek,mt8192-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/mediatek,mt8192-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sean Wang <sean.wang@mediatek.com>
13 The MediaTek's MT8192 Pin controller is used to control SoC pins.
17 const: mediatek,mt8192-pinctrl
19 gpio-controller: true
21 '#gpio-cells':
28 gpio-ranges:
[all …]
/openbmc/linux/Documentation/spi/
H A Dbutterfly.rst2 spi_butterfly - parport-to-butterfly adapter driver
9 sensors, LCD, flash, toggle stick, and more. You can use AVR-GCC to
16 signal pins from the printer port. Or for that matter, you can use
27 need to reflash the firmware, and the pins are the standard Atmel "ISP"
28 connector pins (used also on non-Butterfly AVR boards). On the parport
32 Signal Butterfly Parport (DB-25)
38 MISO J403.PB3/MISO pin 11/S7,nBUSY
44 by clearing PORTB.[0-3]); (b) configure the mtd_dataflash driver; and
48 Signal Butterfly Parport (DB-25)
57 the driver for your custom SPI-based protocol.
[all …]
/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dsoft-spi.txt3 The soft SPI bus implementation allows the use of GPIO pins to simulate a
4 SPI bus. No SPI host is required for this to work. The down-side is that the
10 compatible: "spi-gpio"
11 cs-gpios: GPIOs to use for SPI chip select (output)
12 gpio-sck: GPIO to use for SPI clock (output)
14 gpio-mosi: GPIO to use for SPI MOSI line (output)
15 gpio-miso: GPIO to use for SPI MISO line (input)
18 spi-delay-us: Number of microseconds of delay between each CS transition
27 soft-spi {
28 compatible = "spi-gpio";
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-gpio.c1 // SPDX-License-Identifier: GPL-2.0-or-later
22 * its driver isn't yet working or because the I/O pins it requires
25 * platform_device->driver_data ... points to spi_gpio
27 * spi->controller_state ... reserved for bitbang framework code
29 * spi->controller->dev.driver_data ... points to spi_gpio->bitbang
35 struct gpio_desc *miso; member
40 /*----------------------------------------------------------------------*/
47 * - The slow generic way: set up platform_data to hold the GPIO
48 * numbers used for MISO/MOSI/SCK, and issue procedure calls for
51 * - The quicker inlined way: only helps with platform GPIO code
[all …]
/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/
H A Dcp110-system-controller.txt6 giving access to numerous features: clocks, pin-muxing and many other
11 - compatible: must be: "syscon", "simple-mfd";
12 - reg: register area of the CP110 system controller
18 -------
23 - a set of core clocks
24 - a set of gateable clocks
28 - The first cell must be 0 or 1. 0 for the core clocks and 1 for the
30 - The second cell identifies the particular core clock or gateable
34 - Core clocks
35 - 0 0 APLL
[all …]
/openbmc/linux/Documentation/driver-api/
H A Dspi.rst7 often in the range of 1-20 MHz), a "Master Out, Slave In" (MOSI) data
8 line, and a "Master In, Slave Out" (MISO) data line. SPI is a full
10 another is shifted in on the MISO line. Those bits are assembled into
12 additional chipselect line is usually active-low (nCS); four signals are
24 hardware, which may be as simple as a set of GPIO pins or as complex as
33 board-specific initialization code. A :c:type:`struct spi_driver
46 .. kernel-doc:: include/linux/spi/spi.h
49 .. kernel-doc:: drivers/spi/spi.c
52 .. kernel-doc:: drivers/spi/spi.c
/openbmc/u-boot/arch/arm/dts/
H A Darmada-388-clearfog.dts11 * This file is dual-licensed: you can use it either under the terms
49 /dts-v1/;
50 #include <dt-bindings/input/input.h>
51 #include <dt-bindings/gpio/gpio.h>
52 #include "armada-388.dtsi"
53 #include "armada-38x-solidrun-microsom.dtsi"
57 compatible = "solidrun,clearfog-a1", "marvell,armada388",
61 /* So that mvebu u-boot can update the MAC addresses */
71 stdout-path = "serial0:115200n8";
74 reg_3p3v: regulator-3p3v {
[all …]
H A Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: GPL-2.0
6 #include "armada-8040.dtsi"
9 model = "ClearFog-GT-8K";
10 compatible = "solidrun,clearfog-gt-8k",
14 stdout-path = "serial0:115200n8";
28 simple-bus {
29 compatible = "simple-bus";
31 reg_usb3h0_vbus: usb3-vbus0 {
32 compatible = "regulator-fixed";
33 pinctrl-names = "default";
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa300-raumfeld-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 hw-revision = <0>;
14 stdout-path = &ffuart;
22 reg_3v3: regulator-3v3 {
23 compatible = "regulator-fixed";
24 regulator-name = "3v3-fixed-supply";
25 regulator-min-microvolt = <3300000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Drzg2ul-smarc-pinfunction.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
21 can0-stb-hog {
22 gpio-hog;
24 output-low;
25 line-name = "can0_stb";
35 can1-stb-hog {
[all …]
H A Drzg2lc-smarc-pinfunction.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
16 /* SW8 should be at position 2->1 */
24 /* SW8 should be at position 2->3 so that GPIO9_CAN1_STB line is activated */
25 can1-stb-hog {
26 gpio-hog;
28 output-low;
[all …]
H A Drzg2l-smarc-pinfunction.dtsi1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
12 pinctrl-0 = <&sound_clk_pins>;
13 pinctrl-names = "default";
20 /* SW7 should be at position 2->3 so that GPIO8_CAN0_STB line is activated */
21 can0-stb-hog {
22 gpio-hog;
24 output-low;
25 line-name = "can0_stb";
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "dt-bindings/phy/phy-lan966x-serdes.h"
16 stdout-path = "serial0:115200n8";
19 gpio-restart {
20 compatible = "gpio-restart";
21 pinctrl-0 = <&reset_pins>;
22 pinctrl-names = "default";
29 atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
33 pinctrl-0 = <&usart0_pins>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/marvell/
H A Darmada-8040-clearfog-gt-8k.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include "armada-8040.dtsi"
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/gpio/gpio.h>
16 compatible = "solidrun,clearfog-gt-8k", "marvell,armada8040",
17 "marvell,armada-ap806-quad", "marvell,armada-ap806";
20 stdout-path = "serial0:115200n8";
35 compatible = "pwm-fan";
37 cooling-levels = <0 51 102 153 204 255>;
38 #cooling-cells = <2>;
[all …]
/openbmc/linux/arch/arm/boot/dts/gemini/
H A Dgemini-sq201.dts1 // SPDX-License-Identifier: GPL-2.0
6 /dts-v1/;
9 #include <dt-bindings/input/input.h>
14 #address-cells = <1>;
15 #size-cells = <1>;
24 stdout-path = &uart0;
28 compatible = "gpio-keys";
30 button-setup {
31 debounce-interval = <100>;
32 wakeup-source;
[all …]
H A Dgemini-sl93512r.dts1 // SPDX-License-Identifier: GPL-2.0
5 * "Gemini324 EV-Board" before Storm acquired Storlink Semiconductor.
9 /dts-v1/;
12 #include <dt-bindings/input/input.h>
15 model = "Storlink Semiconductor Gemini324 EV-Board / Storm Semiconductor SL93512R_BRD";
17 #address-cells = <1>;
18 #size-cells = <1>;
28 stdout-path = &uart0;
32 compatible = "gpio-keys";
34 button-wps {
[all …]

1234