| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/fsl/ |
| H A D | fsl,ddr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ddr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale DDR memory controller
10 - Borislav Petkov <bp@alien8.de>
11 - York Sun <york.sun@nxp.com>
15 pattern: "^memory-controller@[0-9a-f]+$"
19 - items:
20 - enum:
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| /openbmc/linux/drivers/memory/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 # Memory devices
6 menuconfig MEMORY config
7 bool "Memory Controller drivers"
9 This option allows to enable specific memory controller drivers,
12 vary from memory tuning and frequency scaling to enabling
13 access to attached peripherals through memory bus.
15 if MEMORY
29 This selects the ARM PrimeCell PL172 MultiPort Memory Controller.
31 controller, say Y or M here.
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| /openbmc/linux/drivers/memory/tegra/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "NVIDIA Tegra Memory Controller support"
8 This driver supports the Memory Controller (MC) hardware found on
14 tristate "NVIDIA Tegra20 External Memory Controller driver"
21 This driver is for the External Memory Controller (EMC) found on
23 This driver is required to change memory timings / clock rate for
24 external memory.
27 tristate "NVIDIA Tegra30 External Memory Controller driver"
33 This driver is for the External Memory Controller (EMC) found on
35 This driver is required to change memory timings / clock rate for
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| /openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nuvoton,npcm-memory-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nuvoton,npcm-memory-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Nuvoton NPCM Memory Controller
10 - Marvin Lin <kflin@nuvoton.com>
11 - Stanley Chu <yschu@nuvoton.com>
14 The Nuvoton BMC SoC supports DDR4 memory with or without ECC (error correction
17 The memory controller supports single bit error correction, double bit error
18 detection (in-line ECC in which a section (1/8th) of the memory device used to
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| H A D | nvidia,tegra210-emc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra210-emc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra210 SoC External Memory Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
14 The EMC interfaces with the off-chip SDRAM to service the request stream
15 sent from the memory controller.
19 const: nvidia,tegra210-emc
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| H A D | nvidia,tegra186-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra186-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra186 (and later) SoC Memory Controller
10 - Jon Hunter <jonathanh@nvidia.com>
11 - Thierry Reding <thierry.reding@gmail.com>
14 The NVIDIA Tegra186 SoC features a 128 bit memory controller that is split
16 handles memory requests for 40-bit virtual addresses from internal clients
17 and arbitrates among them to allocate memory bandwidth.
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| H A D | nvidia,tegra20-mc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra20 SoC Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 The Tegra20 Memory Controller merges request streams from various client
16 interfaces into request stream(s) for the various memory target devices,
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| H A D | arm,pl35x-smc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Arm PL35x Series Static Memory Controller (SMC)
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 The PL35x Static Memory Controller is a bus where you can connect two kinds
14 of memory interfaces, which are NAND and memory mapped interfaces (such as
18 https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa
26 - arm,pl353-smc-r2p1
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| H A D | snps,dw-umctl2-ddrc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/snps,dw-umctl2-ddrc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DesignWare Universal Multi-Protocol Memory Controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Michal Simek <michal.simek@amd.com>
14 Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of
15 working with the memory devices supporting up to (LP)DDR4 protocol. It can
17 16-bits or 32-bits or 64-bits wide.
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| /openbmc/linux/drivers/edac/ |
| H A D | Kconfig | 16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
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| H A D | ppc4xx_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
28 * As realized in the 405EX[r], this controller features:
30 * - Support for registered- and non-registered DDR1 and DDR2 memory.
31 * - 32-bit or 16-bit memory interface with optional ECC.
35 * - 4-bit SEC/DED
36 * - Aligned-nibble error detect
37 * - Bypass mode
39 * - Two (2) memory banks/ranks.
40 * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
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| /openbmc/linux/drivers/char/agp/ |
| H A D | frontend.c | 4 * Copyright (C) 2002-2003 Dave Jones
55 curr = agp_fe.current_controller->pool; in agp_find_mem_by_key()
58 if (curr->key == key) in agp_find_mem_by_key()
60 curr = curr->next; in agp_find_mem_by_key()
63 DBG("key=%d -> mem=%p", key, curr); in agp_find_mem_by_key()
72 /* Check to see if this is even in the memory pool */ in agp_remove_from_pool()
75 if (agp_find_mem_by_key(temp->key) != NULL) { in agp_remove_from_pool()
76 next = temp->next; in agp_remove_from_pool()
77 prev = temp->prev; in agp_remove_from_pool()
80 prev->next = next; in agp_remove_from_pool()
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| /openbmc/linux/drivers/dma/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
12 used to offload memory copies in the network stack and
65 Enable support for Altera / Intel mSGDMA controller.
94 Enable support for Audio DMA Controller found on Apple Silicon SoCs.
102 Support the Atmel AHB DMA controller.
109 Support the Atmel XDMA controller.
112 tristate "Analog Devices AXI-DMAC DMA support"
118 Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
119 controller is often used in Analog Devices' reference designs for FPGA
149 This selects support for the DMA controller in Ingenic JZ4780 SoCs.
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| /openbmc/linux/Documentation/admin-guide/cgroup-v1/ |
| H A D | memory.rst | 2 Memory Resource Controller
12 The Memory Resource Controller has generically been referred to as the
13 memory controller in this document. Do not confuse memory controller
14 used here with the memory controller that is used in hardware.
17 When we mention a cgroup (cgroupfs's directory) with memory controller,
18 we call it "memory cgroup". When you see git-log and source code, you'll
22 Benefits and Purpose of the memory controller
25 The memory controller isolates the memory behaviour of a group of tasks
27 uses of the memory controller. The memory controller can be used to
30 Memory-hungry applications can be isolated and limited to a smaller
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| /openbmc/linux/Documentation/devicetree/bindings/ata/ |
| H A D | apm-xgene.txt | 1 * APM X-Gene 6.0 Gb/s SATA host controller nodes
3 SATA host controller nodes are defined to describe on-chip Serial ATA
4 controllers. Each SATA controller (pair of ports) have its own node.
7 - compatible : Shall contain:
8 * "apm,xgene-ahci"
9 - reg : First memory resource shall be the AHCI memory
11 Second memory resource shall be the host controller
12 core memory resource.
13 Third memory resource shall be the host controller
14 diagnostic memory resource.
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| /openbmc/linux/Documentation/devicetree/bindings/edac/ |
| H A D | apm-xgene-edac.txt | 1 * APM X-Gene SoC EDAC node
3 EDAC node is defined to describe on-chip error detection and correction.
6 memory controller - Memory controller
7 PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache
8 L3 - L3 cache controller
9 SoC - SoC IP's such as Ethernet, SATA, and etc
14 - compatible : Shall be "apm,xgene-edac".
15 - regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
16 - regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
17 - regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
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| /openbmc/linux/Documentation/devicetree/bindings/mips/brcm/ |
| H A D | soc.txt | 5 - compatible: "brcm,bcm3368", "brcm,bcm3384", "brcm,bcm33843"
6 "brcm,bcm3384-viper", "brcm,bcm33843-viper"
12 The experimental -viper variants are for running Linux on the 3384's
16 ----------------
21 = Always-On control block (AON CTRL)
23 This hardware provides control registers for the "always-on" (even in low-power
27 - compatible : should be one of
28 "brcm,bcm7425-aon-ctrl"
29 "brcm,bcm7429-aon-ctrl"
30 "brcm,bcm7435-aon-ctrl" and
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | immap_83xx.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004-2011 Freescale Semiconductor, Inc.
5 * MPC83xx Internal Memory Map
35 u32 immrbar; /* Internal memory map base address register */
138 * Integrated Programmable Interrupt Controller
143 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */
144 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */
149 u32 simsr_h; /* System Internal Interrupt Mask Register - High */
150 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */
161 u32 sifcr_h; /* System Internal Interrupt Force Register - High */
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| /openbmc/linux/Documentation/devicetree/bindings/display/tegra/ |
| H A D | nvidia,tegra20-dc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra Display Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pattern: "^dc@[0-9a-f]+$"
19 - enum:
20 - nvidia,tegra20-dc
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| /openbmc/u-boot/drivers/mmc/ |
| H A D | Kconfig | 1 menu "MMC Host controller Support"
12 also to your specific host controller driver.
31 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
32 and non-removable (e.g. eMMC chip) devices are supported. These
33 appear as block devices in U-Boot and can support filesystems such
42 Secure Digital I/O (SDIO) cards. Both removable (SD, micro-SD, etc.)
43 and non-removable (e.g. eMMC chip) devices are supported. These
44 appear as block devices in U-Boot and can support filesystems such
75 bool "Support eMMC replay protected memory block (RPMB)"
79 key for the Replay Protection Memory Block partition in eMMC.
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| /openbmc/linux/Documentation/admin-guide/ |
| H A D | cgroup-v2.rst | 1 .. _cgroup-v2:
11 conventions of cgroup v2. It describes all userland-visible aspects
12 of cgroup including core and specific controller behaviors. All
14 v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgroup-v1>`.
19 1-1. Terminology
20 1-2. What is cgroup?
22 2-1. Mounting
23 2-2. Organizing Processes and Threads
24 2-2-1. Processes
25 2-2-2. Threads
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| /openbmc/linux/Documentation/devicetree/bindings/dma/ |
| H A D | stericsson,dma40.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson DMA40 DMA Engine
10 - Linus Walleij <linus.walleij@linaro.org>
13 - $ref: dma-controller.yaml#
16 "#dma-cells":
22 0: SPI controller 0
23 1: SD/MMC controller 0 (unused)
24 2: SD/MMC controller 1 (unused)
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| /openbmc/linux/drivers/memory/samsung/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
3 bool "Samsung Exynos Memory Controller support" if COMPILE_TEST
5 Support for the Memory Controller (MC) devices found on
11 tristate "Exynos5422 Dynamic Memory Controller driver"
17 This adds driver for Samsung Exynos5422 SoC DMC (Dynamic Memory
18 Controller). The driver provides support for Dynamic Voltage and
21 based on DT memory information.
25 bool "Exynos SROM controller driver" if COMPILE_TEST
28 This adds driver for Samsung Exynos SoC SROM controller. The driver
31 is provided, the driver enables support for external memory
|
| /openbmc/linux/Documentation/gpu/amdgpu/display/ |
| H A D | dc-glossary.rst | 7 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere,
19 Application-Specific Integrated Circuit
39 * DCFCLK: Display Controller Fabric Clock
43 * MCLK: Memory Clock
49 Cathode Ray Tube Controller - commonly called "Controller" - Generates
62 Display Controller
68 Display Controller Engine
71 Display Controller HUB
102 Display Memory Interface
108 Display Micro-Controller Unit
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| /openbmc/linux/drivers/nvmem/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
5 Support for NVMEM(Non Volatile Memory) devices like EEPROM, EFUSES...
37 calibration data required for the PCIe or the USB-C PHY.
40 be called nvmem-apple-efuses.
43 tristate "Broadcom On-Chip OTP Controller support"
49 controller.
52 will be called nvmem-bcm-ocotp.
72 will be called nvmem-imx-iim.
75 tristate "i.MX 6/7/8 On-Chip OTP Controller support"
79 This is a driver for the On-Chip OTP Controller (OCOTP) available on
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