Lines Matching +full:memory +full:- +full:controller
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
19 memory errors, cache errors, PCI errors, thermal throttling, etc..
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
40 levels are 0-4 (from low to high) and by default it is set to 2.
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
49 occurring on your machine in human-readable form.
60 Not all machines support hardware-driven error report. Some of those
61 provide a BIOS-driven error report mechanism via ACPI, using the
65 When this option is enabled, it will disable the hardware-driven
69 It should be noticed that keeping both GHES and a hardware-driven
83 the AMD64 families (>= K8) of memory controllers.
88 AMD CPUs up to and excluding family 0x17 provide for Memory
93 When enabled, in each of the respective memory controller directories
96 - inject_section (0..3, 16-byte section of 64-byte cacheline),
97 - inject_word (0..8, 16-bit word of 16-byte section),
98 - inject_ecc_vector (hex ecc vector: select bits of inject word)
104 tristate "Amazon's Annapurna Lab Memory Controller"
137 82443BX/GX memory controllers (440BX/GX chipsets).
172 E3-1200 based DRAM controllers.
193 i7 Core (Nehalem) Integrated Memory Controller that exists on
234 tristate "Intel Sandy-Bridge/Ivy-Bridge/Haswell Integrated MC"
238 Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
248 Skylake server Integrated Memory Controllers. If your
249 system has non-volatile DIMMs you should also manually
260 10nm server Integrated Memory Controllers. If your
261 system has non-volatile DIMMs you should also manually
270 Pondicherry2 Integrated Memory Controller. This SoC IP is
272 micro-server but may appear on others in the future.
280 client SoC Integrated Memory Controller using In-Band ECC IP.
281 This In-Band ECC is first used on the Elkhart Lake SoC but
295 Support for error detection and correction on Freescale memory
306 tristate "Cell Broadband Engine memory controller"
310 Cell Broadband Engine internal memory controller
314 tristate "PPC4xx IBM DDR2 Memory Controller"
317 This enables support for EDAC on the ECC memory used
318 with the IBM DDR2 memory controller found in various
323 tristate "AMD8131 HyperTransport PCI-X Tunnel"
327 AMD8131 HyperTransport PCI-X Tunnel chip.
341 tristate "IBM CPC925 Memory Controller (PPC970FX)"
345 IBM CPC925 Bridge and Memory Controller, which is
350 tristate "Highbank Memory Controller"
354 Calxeda Highbank memory controller.
361 Calxeda Highbank memory controller.
378 tristate "Cavium Octeon DRAM Memory Controller (LMC)"
385 tristate "Cavium Octeon PCI Controller"
397 Cavium ThunderX memory controllers (LMC), Cache
414 Altera SDRAM Memory for Altera SoCs. Note that the
423 Altera L2 cache Memory for Altera SoCs. This option
427 bool "Altera On-Chip RAM ECC"
431 Altera On-Chip RAM Memory for Altera SoCs.
438 Altera Ethernet FIFO Memory for Altera SoCs.
445 Altera NAND FIFO Memory for Altera SoCs.
452 Altera DMA FIFO Memory for Altera SoCs.
459 Altera USB FIFO Memory for Altera SoCs.
466 Altera QSPI FIFO Memory for Altera SoCs.
473 Altera SDMMC FIFO Memory for Altera SoCs.
489 tristate "Synopsys DDR Memory Controller"
493 memory controller.
496 tristate "APM X-Gene SoC"
500 APM X-Gene family of SOCs.
503 tristate "Texas Instruments DDR3 ECC Controller"
509 tristate "QCOM EDAC Controller"
516 As of now, it supports error reporting for Last Level Cache Controller (LLCC)
532 tristate "Mellanox BlueField Memory ECC"
539 tristate "ARM DMC-520 ECC"
543 SoCs with ARM DMC-520 DRAM controller.
546 tristate "Xilinx ZynqMP OCM Controller"
550 Xilinx ZynqMP OCM (On Chip Memory) controller. It can also be
554 tristate "Nuvoton NPCM DDR Memory Controller"
558 memory controller.
560 The memory controller supports single bit error correction, double bit
561 error detection (in-line ECC in which a section 1/8th of the memory