include/asm/immap_83xx.h

1 /* SPDX-License-Identifier: GPL-2.0+ */
3  * Copyright 2004-2011 Freescale Semiconductor, Inc.
5  * MPC83xx Internal Memory Map
35 	u32 immrbar;		/* Internal memory map base address register */
138  * Integrated Programmable Interrupt Controller
143 	u32 sipnr_h;		/* System Internal Interrupt Pending Register - High */
144 	u32 sipnr_l;		/* System Internal Interrupt Pending Register - Low */
149 	u32 simsr_h;		/* System Internal Interrupt Mask Register - High */
150 	u32 simsr_l;		/* System Internal Interrupt Mask Register - Low */
161 	u32 sifcr_h;		/* System Internal Interrupt Force Register - High */
162 	u32 sifcr_l;		/* System Internal Interrupt Force Register - Low */
268 	u32 lbmcsar;		/* Local bus memory controller start address */
269 	u32 sdmcsar;		/* Secondary DDR memory controller start address */
271 	u32 lbmcear;		/* Local bus memory controller end address */
272 	u32 sdmcear;		/* Secondary DDR memory controller end address */
274 	u32 lbmcar;		/* Local bus memory controller attributes */
275 	u32 sdmcar;		/* Secondary DDR memory controller attributes */
280  * DDR Memory Controller Memory Map for DDR1
290 	ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */
314 	u32 data_err_inject_hi;	/* Memory Data Path Error Injection Mask High */
315 	u32 data_err_inject_lo;	/* Memory Data Path Error Injection Mask Low */
316 	u32 ecc_err_inject;	/* Memory Data Path Error Injection Mask ECC */
318 	u32 capture_data_hi;	/* Memory Data Path Read Capture High */
319 	u32 capture_data_lo;	/* Memory Data Path Read Capture Low */
320 	u32 capture_ecc;	/* Memory Data Path Read Capture ECC */
322 	u32 err_detect;		/* Memory Error Detect */
323 	u32 err_disable;	/* Memory Error Disable */
324 	u32 err_int_en;		/* Memory Error Interrupt Enable */
325 	u32 capture_attributes;	/* Memory Error Attributes Capture */
326 	u32 capture_address;	/* Memory Error Address Capture */
327 	u32 capture_ext_address;/* Memory Error Extended Address Capture */
328 	u32 err_sbe;		/* Memory Single-Bit ECC Error Management */
357 	u32 res0[0xC];		/* 0x0-0x29 reseverd */
360 	u32 res1[0x6];		/* 0x38-0x49 reserved */
366 	u32 res2;		/* 0x64-0x67 reserved */
368 	u32 res3[0x5];		/* 0x6C-0x79 reserved */
371 	u32 res4[0x1E];		/* 0x88-0x99 reserved */
410  * PCI Controller Control and Status Registers
635 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
646 	struct ccsr_ddr		ddr;	/* DDR Memory Controller Memory */
648 	ddr83xx_t		ddr;	/* DDR Memory Controller Memory */
654 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
660 	pcictrl83xx_t		pci_ctrl[2];	/* PCI Controller Control and Status Registers */
671 #define CONFIG_SYS_MPC83xx_USB1_OFFSET  0x22000	/* use the MPH controller */
675 #define CONFIG_SYS_MPC83xx_USB2_OFFSET  0x23000	/* use the DR controller */
689 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
696 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
701 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
708 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
724 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
731 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
736 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
743 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
745 	pex83xx_t		pciexp[2];	/* PCI Express Controller */
747 	tdm83xx_t		tdm;		/* TDM Controller */
749 	sata83xx_t		sata[2];	/* SATA Controller */
751 	usb83xx_t		usb[1];		/* USB DR Controller */
769 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
776 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
781 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
788 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
790 	pex83xx_t		pciexp[2];	/* PCI Express Controller */
792 	sata83xx_t		sata[4];	/* SATA Controller */
794 	usb83xx_t		usb[1];		/* USB DR Controller */
797 	sdhc83xx_t		sdhc;		/* SDHC Controller */
813 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
826 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
831 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
837 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
839 	ddr83xx_t		ddr_secondary;	/* Secondary DDR Memory Controller Memory Map */
853 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
865 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
870 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
876 	pcictrl83xx_t		pci_ctrl[1];	/* PCI Controller Control and Status Registers */
889 	ipic83xx_t		ipic;		/* Integrated Programmable Interrupt Controller */
899 	ddr83xx_t		ddr;		/* DDR Memory Controller Memory */
906 	fsl_lbc_t		im_lbc;		/* Local Bus Controller Regs */
925 	sdhc83xx_t		sdhc;		/* SDHC Controller */
953 #define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)