1b886d83cSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2dba7a77cSGrant Erickson /*
3dba7a77cSGrant Erickson * Copyright (c) 2008 Nuovation System Designs, LLC
4dba7a77cSGrant Erickson * Grant Erickson <gerickson@nuovations.com>
5dba7a77cSGrant Erickson */
6dba7a77cSGrant Erickson
7dba7a77cSGrant Erickson #include <linux/edac.h>
8dba7a77cSGrant Erickson #include <linux/interrupt.h>
9dba7a77cSGrant Erickson #include <linux/irq.h>
10dba7a77cSGrant Erickson #include <linux/kernel.h>
11dba7a77cSGrant Erickson #include <linux/mm.h>
12dba7a77cSGrant Erickson #include <linux/module.h>
13dba7a77cSGrant Erickson #include <linux/of_device.h>
14bce02f71SChristophe Leroy #include <linux/of_irq.h>
15dba7a77cSGrant Erickson #include <linux/of_platform.h>
16dba7a77cSGrant Erickson #include <linux/types.h>
17dba7a77cSGrant Erickson
18dba7a77cSGrant Erickson #include <asm/dcr.h>
19dba7a77cSGrant Erickson
2078d88e8aSMauro Carvalho Chehab #include "edac_module.h"
21dba7a77cSGrant Erickson #include "ppc4xx_edac.h"
22dba7a77cSGrant Erickson
23dba7a77cSGrant Erickson /*
24dba7a77cSGrant Erickson * This file implements a driver for monitoring and handling events
25dba7a77cSGrant Erickson * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
26dba7a77cSGrant Erickson * 405EX[r], 440SP, 440SPe, 460EX, 460GT and 460SX.
27dba7a77cSGrant Erickson *
28dba7a77cSGrant Erickson * As realized in the 405EX[r], this controller features:
29dba7a77cSGrant Erickson *
30dba7a77cSGrant Erickson * - Support for registered- and non-registered DDR1 and DDR2 memory.
31dba7a77cSGrant Erickson * - 32-bit or 16-bit memory interface with optional ECC.
32dba7a77cSGrant Erickson *
33dba7a77cSGrant Erickson * o ECC support includes:
34dba7a77cSGrant Erickson *
35dba7a77cSGrant Erickson * - 4-bit SEC/DED
36dba7a77cSGrant Erickson * - Aligned-nibble error detect
37dba7a77cSGrant Erickson * - Bypass mode
38dba7a77cSGrant Erickson *
39dba7a77cSGrant Erickson * - Two (2) memory banks/ranks.
40dba7a77cSGrant Erickson * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
41dba7a77cSGrant Erickson * bank/rank in 16-bit mode.
42dba7a77cSGrant Erickson *
43dba7a77cSGrant Erickson * As realized in the 440SP and 440SPe, this controller changes/adds:
44dba7a77cSGrant Erickson *
45dba7a77cSGrant Erickson * - 64-bit or 32-bit memory interface with optional ECC.
46dba7a77cSGrant Erickson *
47dba7a77cSGrant Erickson * o ECC support includes:
48dba7a77cSGrant Erickson *
49dba7a77cSGrant Erickson * - 8-bit SEC/DED
50dba7a77cSGrant Erickson * - Aligned-nibble error detect
51dba7a77cSGrant Erickson * - Bypass mode
52dba7a77cSGrant Erickson *
53dba7a77cSGrant Erickson * - Up to 4 GiB per bank/rank in 64-bit mode and up to 2 GiB
54dba7a77cSGrant Erickson * per bank/rank in 32-bit mode.
55dba7a77cSGrant Erickson *
56dba7a77cSGrant Erickson * As realized in the 460EX and 460GT, this controller changes/adds:
57dba7a77cSGrant Erickson *
58dba7a77cSGrant Erickson * - 64-bit or 32-bit memory interface with optional ECC.
59dba7a77cSGrant Erickson *
60dba7a77cSGrant Erickson * o ECC support includes:
61dba7a77cSGrant Erickson *
62dba7a77cSGrant Erickson * - 8-bit SEC/DED
63dba7a77cSGrant Erickson * - Aligned-nibble error detect
64dba7a77cSGrant Erickson * - Bypass mode
65dba7a77cSGrant Erickson *
66dba7a77cSGrant Erickson * - Four (4) memory banks/ranks.
67dba7a77cSGrant Erickson * - Up to 16 GiB per bank/rank in 64-bit mode and up to 8 GiB
68dba7a77cSGrant Erickson * per bank/rank in 32-bit mode.
69dba7a77cSGrant Erickson *
70dba7a77cSGrant Erickson * At present, this driver has ONLY been tested against the controller
71dba7a77cSGrant Erickson * realization in the 405EX[r] on the AMCC Kilauea and Haleakala
72dba7a77cSGrant Erickson * boards (256 MiB w/o ECC memory soldered onto the board) and a
73dba7a77cSGrant Erickson * proprietary board based on those designs (128 MiB ECC memory, also
74dba7a77cSGrant Erickson * soldered onto the board).
75dba7a77cSGrant Erickson *
76dba7a77cSGrant Erickson * Dynamic feature detection and handling needs to be added for the
77dba7a77cSGrant Erickson * other realizations of this controller listed above.
78dba7a77cSGrant Erickson *
79dba7a77cSGrant Erickson * Eventually, this driver will likely be adapted to the above variant
80dba7a77cSGrant Erickson * realizations of this controller as well as broken apart to handle
81dba7a77cSGrant Erickson * the other known ECC-capable controllers prevalent in other 4xx
82dba7a77cSGrant Erickson * processors:
83dba7a77cSGrant Erickson *
84dba7a77cSGrant Erickson * - IBM SDRAM (405GP, 405CR and 405EP) "ibm,sdram-4xx"
85dba7a77cSGrant Erickson * - IBM DDR1 (440GP, 440GX, 440EP and 440GR) "ibm,sdram-4xx-ddr"
86dba7a77cSGrant Erickson * - Denali DDR1/DDR2 (440EPX and 440GRX) "denali,sdram-4xx-ddr2"
87dba7a77cSGrant Erickson *
88dba7a77cSGrant Erickson * For this controller, unfortunately, correctable errors report
89dba7a77cSGrant Erickson * nothing more than the beat/cycle and byte/lane the correction
90dba7a77cSGrant Erickson * occurred on and the check bit group that covered the error.
91dba7a77cSGrant Erickson *
92dba7a77cSGrant Erickson * In contrast, uncorrectable errors also report the failing address,
93dba7a77cSGrant Erickson * the bus master and the transaction direction (i.e. read or write)
94dba7a77cSGrant Erickson *
95dba7a77cSGrant Erickson * Regardless of whether the error is a CE or a UE, we report the
96dba7a77cSGrant Erickson * following pieces of information in the driver-unique message to the
97dba7a77cSGrant Erickson * EDAC subsystem:
98dba7a77cSGrant Erickson *
99dba7a77cSGrant Erickson * - Device tree path
100dba7a77cSGrant Erickson * - Bank(s)
101dba7a77cSGrant Erickson * - Check bit error group
102dba7a77cSGrant Erickson * - Beat(s)/lane(s)
103dba7a77cSGrant Erickson */
104dba7a77cSGrant Erickson
105dba7a77cSGrant Erickson /* Preprocessor Definitions */
106dba7a77cSGrant Erickson
107dba7a77cSGrant Erickson #define EDAC_OPSTATE_INT_STR "interrupt"
108dba7a77cSGrant Erickson #define EDAC_OPSTATE_POLL_STR "polled"
109dba7a77cSGrant Erickson #define EDAC_OPSTATE_UNKNOWN_STR "unknown"
110dba7a77cSGrant Erickson
111dba7a77cSGrant Erickson #define PPC4XX_EDAC_MODULE_NAME "ppc4xx_edac"
112152ba394SMichal Marek #define PPC4XX_EDAC_MODULE_REVISION "v1.0.0"
113dba7a77cSGrant Erickson
114dba7a77cSGrant Erickson #define PPC4XX_EDAC_MESSAGE_SIZE 256
115dba7a77cSGrant Erickson
116dba7a77cSGrant Erickson /*
117dba7a77cSGrant Erickson * Kernel logging without an EDAC instance
118dba7a77cSGrant Erickson */
119dba7a77cSGrant Erickson #define ppc4xx_edac_printk(level, fmt, arg...) \
120dba7a77cSGrant Erickson edac_printk(level, "PPC4xx MC", fmt, ##arg)
121dba7a77cSGrant Erickson
122dba7a77cSGrant Erickson /*
123dba7a77cSGrant Erickson * Kernel logging with an EDAC instance
124dba7a77cSGrant Erickson */
125dba7a77cSGrant Erickson #define ppc4xx_edac_mc_printk(level, mci, fmt, arg...) \
126dba7a77cSGrant Erickson edac_mc_chipset_printk(mci, level, "PPC4xx", fmt, ##arg)
127dba7a77cSGrant Erickson
128dba7a77cSGrant Erickson /*
129dba7a77cSGrant Erickson * Macros to convert bank configuration size enumerations into MiB and
130dba7a77cSGrant Erickson * page values.
131dba7a77cSGrant Erickson */
132dba7a77cSGrant Erickson #define SDRAM_MBCF_SZ_MiB_MIN 4
133dba7a77cSGrant Erickson #define SDRAM_MBCF_SZ_TO_MiB(n) (SDRAM_MBCF_SZ_MiB_MIN \
134dba7a77cSGrant Erickson << (SDRAM_MBCF_SZ_DECODE(n)))
135dba7a77cSGrant Erickson #define SDRAM_MBCF_SZ_TO_PAGES(n) (SDRAM_MBCF_SZ_MiB_MIN \
136dba7a77cSGrant Erickson << (20 - PAGE_SHIFT + \
137dba7a77cSGrant Erickson SDRAM_MBCF_SZ_DECODE(n)))
138dba7a77cSGrant Erickson
139dba7a77cSGrant Erickson /*
140dba7a77cSGrant Erickson * The ibm,sdram-4xx-ddr2 Device Control Registers (DCRs) are
14142b2aa86SJustin P. Mattock * indirectly accessed and have a base and length defined by the
142dba7a77cSGrant Erickson * device tree. The base can be anything; however, we expect the
143dba7a77cSGrant Erickson * length to be precisely two registers, the first for the address
144dba7a77cSGrant Erickson * window and the second for the data window.
145dba7a77cSGrant Erickson */
146dba7a77cSGrant Erickson #define SDRAM_DCR_RESOURCE_LEN 2
147dba7a77cSGrant Erickson #define SDRAM_DCR_ADDR_OFFSET 0
148dba7a77cSGrant Erickson #define SDRAM_DCR_DATA_OFFSET 1
149dba7a77cSGrant Erickson
150dba7a77cSGrant Erickson /*
151dba7a77cSGrant Erickson * Device tree interrupt indices
152dba7a77cSGrant Erickson */
153dba7a77cSGrant Erickson #define INTMAP_ECCDED_INDEX 0 /* Double-bit Error Detect */
154dba7a77cSGrant Erickson #define INTMAP_ECCSEC_INDEX 1 /* Single-bit Error Correct */
155dba7a77cSGrant Erickson
156dba7a77cSGrant Erickson /* Type Definitions */
157dba7a77cSGrant Erickson
158dba7a77cSGrant Erickson /*
159dba7a77cSGrant Erickson * PPC4xx SDRAM memory controller private instance data
160dba7a77cSGrant Erickson */
161dba7a77cSGrant Erickson struct ppc4xx_edac_pdata {
162dba7a77cSGrant Erickson dcr_host_t dcr_host; /* Indirect DCR address/data window mapping */
163dba7a77cSGrant Erickson struct {
164dba7a77cSGrant Erickson int sec; /* Single-bit correctable error IRQ assigned */
165dba7a77cSGrant Erickson int ded; /* Double-bit detectable error IRQ assigned */
166dba7a77cSGrant Erickson } irqs;
167dba7a77cSGrant Erickson };
168dba7a77cSGrant Erickson
169dba7a77cSGrant Erickson /*
170dba7a77cSGrant Erickson * Various status data gathered and manipulated when checking and
171dba7a77cSGrant Erickson * reporting ECC status.
172dba7a77cSGrant Erickson */
173dba7a77cSGrant Erickson struct ppc4xx_ecc_status {
174dba7a77cSGrant Erickson u32 ecces;
175dba7a77cSGrant Erickson u32 besr;
176dba7a77cSGrant Erickson u32 bearh;
177dba7a77cSGrant Erickson u32 bearl;
178dba7a77cSGrant Erickson u32 wmirq;
179dba7a77cSGrant Erickson };
180dba7a77cSGrant Erickson
181dba7a77cSGrant Erickson /* Global Variables */
182dba7a77cSGrant Erickson
183dba7a77cSGrant Erickson /*
184dba7a77cSGrant Erickson * Device tree node type and compatible tuples this driver can match
185dba7a77cSGrant Erickson * on.
186dba7a77cSGrant Erickson */
1871afaa055SFabian Frederick static const struct of_device_id ppc4xx_edac_match[] = {
188dba7a77cSGrant Erickson {
189dba7a77cSGrant Erickson .compatible = "ibm,sdram-4xx-ddr2"
190dba7a77cSGrant Erickson },
191dba7a77cSGrant Erickson { }
192dba7a77cSGrant Erickson };
19390b3b373SLuis de Bethencourt MODULE_DEVICE_TABLE(of, ppc4xx_edac_match);
194dba7a77cSGrant Erickson
195dba7a77cSGrant Erickson /*
196dba7a77cSGrant Erickson * TODO: The row and channel parameters likely need to be dynamically
197dba7a77cSGrant Erickson * set based on the aforementioned variant controller realizations.
198dba7a77cSGrant Erickson */
199dba7a77cSGrant Erickson static const unsigned ppc4xx_edac_nr_csrows = 2;
200dba7a77cSGrant Erickson static const unsigned ppc4xx_edac_nr_chans = 1;
201dba7a77cSGrant Erickson
202dba7a77cSGrant Erickson /*
203dba7a77cSGrant Erickson * Strings associated with PLB master IDs capable of being posted in
204dba7a77cSGrant Erickson * SDRAM_BESR or SDRAM_WMIRQ on uncorrectable ECC errors.
205dba7a77cSGrant Erickson */
206dba7a77cSGrant Erickson static const char * const ppc4xx_plb_masters[9] = {
207dba7a77cSGrant Erickson [SDRAM_PLB_M0ID_ICU] = "ICU",
208dba7a77cSGrant Erickson [SDRAM_PLB_M0ID_PCIE0] = "PCI-E 0",
209dba7a77cSGrant Erickson [SDRAM_PLB_M0ID_PCIE1] = "PCI-E 1",
210dba7a77cSGrant Erickson [SDRAM_PLB_M0ID_DMA] = "DMA",
211dba7a77cSGrant Erickson [SDRAM_PLB_M0ID_DCU] = "DCU",
212dba7a77cSGrant Erickson [SDRAM_PLB_M0ID_OPB] = "OPB",
213dba7a77cSGrant Erickson [SDRAM_PLB_M0ID_MAL] = "MAL",
214dba7a77cSGrant Erickson [SDRAM_PLB_M0ID_SEC] = "SEC",
215dba7a77cSGrant Erickson [SDRAM_PLB_M0ID_AHB] = "AHB"
216dba7a77cSGrant Erickson };
217dba7a77cSGrant Erickson
218dba7a77cSGrant Erickson /**
219dba7a77cSGrant Erickson * mfsdram - read and return controller register data
220dba7a77cSGrant Erickson * @dcr_host: A pointer to the DCR mapping.
221dba7a77cSGrant Erickson * @idcr_n: The indirect DCR register to read.
222dba7a77cSGrant Erickson *
223dba7a77cSGrant Erickson * This routine reads and returns the data associated with the
224dba7a77cSGrant Erickson * controller's specified indirect DCR register.
225dba7a77cSGrant Erickson *
226dba7a77cSGrant Erickson * Returns the read data.
227dba7a77cSGrant Erickson */
228dba7a77cSGrant Erickson static inline u32
mfsdram(const dcr_host_t * dcr_host,unsigned int idcr_n)229dba7a77cSGrant Erickson mfsdram(const dcr_host_t *dcr_host, unsigned int idcr_n)
230dba7a77cSGrant Erickson {
231dba7a77cSGrant Erickson return __mfdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
232dba7a77cSGrant Erickson dcr_host->base + SDRAM_DCR_DATA_OFFSET,
233dba7a77cSGrant Erickson idcr_n);
234dba7a77cSGrant Erickson }
235dba7a77cSGrant Erickson
236dba7a77cSGrant Erickson /**
237dba7a77cSGrant Erickson * mtsdram - write controller register data
238dba7a77cSGrant Erickson * @dcr_host: A pointer to the DCR mapping.
239dba7a77cSGrant Erickson * @idcr_n: The indirect DCR register to write.
240dba7a77cSGrant Erickson * @value: The data to write.
241dba7a77cSGrant Erickson *
242dba7a77cSGrant Erickson * This routine writes the provided data to the controller's specified
243dba7a77cSGrant Erickson * indirect DCR register.
244dba7a77cSGrant Erickson */
245dba7a77cSGrant Erickson static inline void
mtsdram(const dcr_host_t * dcr_host,unsigned int idcr_n,u32 value)246dba7a77cSGrant Erickson mtsdram(const dcr_host_t *dcr_host, unsigned int idcr_n, u32 value)
247dba7a77cSGrant Erickson {
248dba7a77cSGrant Erickson return __mtdcri(dcr_host->base + SDRAM_DCR_ADDR_OFFSET,
249dba7a77cSGrant Erickson dcr_host->base + SDRAM_DCR_DATA_OFFSET,
250dba7a77cSGrant Erickson idcr_n,
251dba7a77cSGrant Erickson value);
252dba7a77cSGrant Erickson }
253dba7a77cSGrant Erickson
254dba7a77cSGrant Erickson /**
255dba7a77cSGrant Erickson * ppc4xx_edac_check_bank_error - check a bank for an ECC bank error
256dba7a77cSGrant Erickson * @status: A pointer to the ECC status structure to check for an
257dba7a77cSGrant Erickson * ECC bank error.
258dba7a77cSGrant Erickson * @bank: The bank to check for an ECC error.
259dba7a77cSGrant Erickson *
260dba7a77cSGrant Erickson * This routine determines whether the specified bank has an ECC
261dba7a77cSGrant Erickson * error.
262dba7a77cSGrant Erickson *
263dba7a77cSGrant Erickson * Returns true if the specified bank has an ECC error; otherwise,
264dba7a77cSGrant Erickson * false.
265dba7a77cSGrant Erickson */
266dba7a77cSGrant Erickson static bool
ppc4xx_edac_check_bank_error(const struct ppc4xx_ecc_status * status,unsigned int bank)267dba7a77cSGrant Erickson ppc4xx_edac_check_bank_error(const struct ppc4xx_ecc_status *status,
268dba7a77cSGrant Erickson unsigned int bank)
269dba7a77cSGrant Erickson {
270dba7a77cSGrant Erickson switch (bank) {
271dba7a77cSGrant Erickson case 0:
272dba7a77cSGrant Erickson return status->ecces & SDRAM_ECCES_BK0ER;
273dba7a77cSGrant Erickson case 1:
274dba7a77cSGrant Erickson return status->ecces & SDRAM_ECCES_BK1ER;
275dba7a77cSGrant Erickson default:
276dba7a77cSGrant Erickson return false;
277dba7a77cSGrant Erickson }
278dba7a77cSGrant Erickson }
279dba7a77cSGrant Erickson
280dba7a77cSGrant Erickson /**
281dba7a77cSGrant Erickson * ppc4xx_edac_generate_bank_message - generate interpretted bank status message
282dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance associated
283dba7a77cSGrant Erickson * with the bank message being generated.
284dba7a77cSGrant Erickson * @status: A pointer to the ECC status structure to generate the
285dba7a77cSGrant Erickson * message from.
286dba7a77cSGrant Erickson * @buffer: A pointer to the buffer in which to generate the
287dba7a77cSGrant Erickson * message.
288dba7a77cSGrant Erickson * @size: The size, in bytes, of space available in buffer.
289dba7a77cSGrant Erickson *
290dba7a77cSGrant Erickson * This routine generates to the provided buffer the portion of the
291dba7a77cSGrant Erickson * driver-unique report message associated with the ECCESS[BKNER]
292dba7a77cSGrant Erickson * field of the specified ECC status.
293dba7a77cSGrant Erickson *
294dba7a77cSGrant Erickson * Returns the number of characters generated on success; otherwise, <
295dba7a77cSGrant Erickson * 0 on error.
296dba7a77cSGrant Erickson */
297dba7a77cSGrant Erickson static int
ppc4xx_edac_generate_bank_message(const struct mem_ctl_info * mci,const struct ppc4xx_ecc_status * status,char * buffer,size_t size)298dba7a77cSGrant Erickson ppc4xx_edac_generate_bank_message(const struct mem_ctl_info *mci,
299dba7a77cSGrant Erickson const struct ppc4xx_ecc_status *status,
300dba7a77cSGrant Erickson char *buffer,
301dba7a77cSGrant Erickson size_t size)
302dba7a77cSGrant Erickson {
303dba7a77cSGrant Erickson int n, total = 0;
304dba7a77cSGrant Erickson unsigned int row, rows;
305dba7a77cSGrant Erickson
306dba7a77cSGrant Erickson n = snprintf(buffer, size, "%s: Banks: ", mci->dev_name);
307dba7a77cSGrant Erickson
308dba7a77cSGrant Erickson if (n < 0 || n >= size)
309dba7a77cSGrant Erickson goto fail;
310dba7a77cSGrant Erickson
311dba7a77cSGrant Erickson buffer += n;
312dba7a77cSGrant Erickson size -= n;
313dba7a77cSGrant Erickson total += n;
314dba7a77cSGrant Erickson
315dba7a77cSGrant Erickson for (rows = 0, row = 0; row < mci->nr_csrows; row++) {
316dba7a77cSGrant Erickson if (ppc4xx_edac_check_bank_error(status, row)) {
317dba7a77cSGrant Erickson n = snprintf(buffer, size, "%s%u",
318dba7a77cSGrant Erickson (rows++ ? ", " : ""), row);
319dba7a77cSGrant Erickson
320dba7a77cSGrant Erickson if (n < 0 || n >= size)
321dba7a77cSGrant Erickson goto fail;
322dba7a77cSGrant Erickson
323dba7a77cSGrant Erickson buffer += n;
324dba7a77cSGrant Erickson size -= n;
325dba7a77cSGrant Erickson total += n;
326dba7a77cSGrant Erickson }
327dba7a77cSGrant Erickson }
328dba7a77cSGrant Erickson
329dba7a77cSGrant Erickson n = snprintf(buffer, size, "%s; ", rows ? "" : "None");
330dba7a77cSGrant Erickson
331dba7a77cSGrant Erickson if (n < 0 || n >= size)
332dba7a77cSGrant Erickson goto fail;
333dba7a77cSGrant Erickson
334dba7a77cSGrant Erickson buffer += n;
335dba7a77cSGrant Erickson size -= n;
336dba7a77cSGrant Erickson total += n;
337dba7a77cSGrant Erickson
338dba7a77cSGrant Erickson fail:
339dba7a77cSGrant Erickson return total;
340dba7a77cSGrant Erickson }
341dba7a77cSGrant Erickson
342dba7a77cSGrant Erickson /**
343dba7a77cSGrant Erickson * ppc4xx_edac_generate_checkbit_message - generate interpretted checkbit message
344dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance associated
345dba7a77cSGrant Erickson * with the checkbit message being generated.
346dba7a77cSGrant Erickson * @status: A pointer to the ECC status structure to generate the
347dba7a77cSGrant Erickson * message from.
348dba7a77cSGrant Erickson * @buffer: A pointer to the buffer in which to generate the
349dba7a77cSGrant Erickson * message.
350dba7a77cSGrant Erickson * @size: The size, in bytes, of space available in buffer.
351dba7a77cSGrant Erickson *
352dba7a77cSGrant Erickson * This routine generates to the provided buffer the portion of the
353dba7a77cSGrant Erickson * driver-unique report message associated with the ECCESS[CKBER]
354dba7a77cSGrant Erickson * field of the specified ECC status.
355dba7a77cSGrant Erickson *
356dba7a77cSGrant Erickson * Returns the number of characters generated on success; otherwise, <
357dba7a77cSGrant Erickson * 0 on error.
358dba7a77cSGrant Erickson */
359dba7a77cSGrant Erickson static int
ppc4xx_edac_generate_checkbit_message(const struct mem_ctl_info * mci,const struct ppc4xx_ecc_status * status,char * buffer,size_t size)360dba7a77cSGrant Erickson ppc4xx_edac_generate_checkbit_message(const struct mem_ctl_info *mci,
361dba7a77cSGrant Erickson const struct ppc4xx_ecc_status *status,
362dba7a77cSGrant Erickson char *buffer,
363dba7a77cSGrant Erickson size_t size)
364dba7a77cSGrant Erickson {
365dba7a77cSGrant Erickson const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
366dba7a77cSGrant Erickson const char *ckber = NULL;
367dba7a77cSGrant Erickson
368dba7a77cSGrant Erickson switch (status->ecces & SDRAM_ECCES_CKBER_MASK) {
369dba7a77cSGrant Erickson case SDRAM_ECCES_CKBER_NONE:
370dba7a77cSGrant Erickson ckber = "None";
371dba7a77cSGrant Erickson break;
372dba7a77cSGrant Erickson case SDRAM_ECCES_CKBER_32_ECC_0_3:
373dba7a77cSGrant Erickson ckber = "ECC0:3";
374dba7a77cSGrant Erickson break;
375dba7a77cSGrant Erickson case SDRAM_ECCES_CKBER_32_ECC_4_8:
376dba7a77cSGrant Erickson switch (mfsdram(&pdata->dcr_host, SDRAM_MCOPT1) &
377dba7a77cSGrant Erickson SDRAM_MCOPT1_WDTH_MASK) {
378dba7a77cSGrant Erickson case SDRAM_MCOPT1_WDTH_16:
379dba7a77cSGrant Erickson ckber = "ECC0:3";
380dba7a77cSGrant Erickson break;
381dba7a77cSGrant Erickson case SDRAM_MCOPT1_WDTH_32:
382dba7a77cSGrant Erickson ckber = "ECC4:8";
383dba7a77cSGrant Erickson break;
384dba7a77cSGrant Erickson default:
385dba7a77cSGrant Erickson ckber = "Unknown";
386dba7a77cSGrant Erickson break;
387dba7a77cSGrant Erickson }
388dba7a77cSGrant Erickson break;
389dba7a77cSGrant Erickson case SDRAM_ECCES_CKBER_32_ECC_0_8:
390dba7a77cSGrant Erickson ckber = "ECC0:8";
391dba7a77cSGrant Erickson break;
392dba7a77cSGrant Erickson default:
393dba7a77cSGrant Erickson ckber = "Unknown";
394dba7a77cSGrant Erickson break;
395dba7a77cSGrant Erickson }
396dba7a77cSGrant Erickson
397dba7a77cSGrant Erickson return snprintf(buffer, size, "Checkbit Error: %s", ckber);
398dba7a77cSGrant Erickson }
399dba7a77cSGrant Erickson
400dba7a77cSGrant Erickson /**
401dba7a77cSGrant Erickson * ppc4xx_edac_generate_lane_message - generate interpretted byte lane message
402dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance associated
403dba7a77cSGrant Erickson * with the byte lane message being generated.
404dba7a77cSGrant Erickson * @status: A pointer to the ECC status structure to generate the
405dba7a77cSGrant Erickson * message from.
406dba7a77cSGrant Erickson * @buffer: A pointer to the buffer in which to generate the
407dba7a77cSGrant Erickson * message.
408dba7a77cSGrant Erickson * @size: The size, in bytes, of space available in buffer.
409dba7a77cSGrant Erickson *
410dba7a77cSGrant Erickson * This routine generates to the provided buffer the portion of the
411dba7a77cSGrant Erickson * driver-unique report message associated with the ECCESS[BNCE]
412dba7a77cSGrant Erickson * field of the specified ECC status.
413dba7a77cSGrant Erickson *
414dba7a77cSGrant Erickson * Returns the number of characters generated on success; otherwise, <
415dba7a77cSGrant Erickson * 0 on error.
416dba7a77cSGrant Erickson */
417dba7a77cSGrant Erickson static int
ppc4xx_edac_generate_lane_message(const struct mem_ctl_info * mci,const struct ppc4xx_ecc_status * status,char * buffer,size_t size)418dba7a77cSGrant Erickson ppc4xx_edac_generate_lane_message(const struct mem_ctl_info *mci,
419dba7a77cSGrant Erickson const struct ppc4xx_ecc_status *status,
420dba7a77cSGrant Erickson char *buffer,
421dba7a77cSGrant Erickson size_t size)
422dba7a77cSGrant Erickson {
423dba7a77cSGrant Erickson int n, total = 0;
424dba7a77cSGrant Erickson unsigned int lane, lanes;
425dba7a77cSGrant Erickson const unsigned int first_lane = 0;
426dba7a77cSGrant Erickson const unsigned int lane_count = 16;
427dba7a77cSGrant Erickson
428dba7a77cSGrant Erickson n = snprintf(buffer, size, "; Byte Lane Errors: ");
429dba7a77cSGrant Erickson
430dba7a77cSGrant Erickson if (n < 0 || n >= size)
431dba7a77cSGrant Erickson goto fail;
432dba7a77cSGrant Erickson
433dba7a77cSGrant Erickson buffer += n;
434dba7a77cSGrant Erickson size -= n;
435dba7a77cSGrant Erickson total += n;
436dba7a77cSGrant Erickson
437dba7a77cSGrant Erickson for (lanes = 0, lane = first_lane; lane < lane_count; lane++) {
438dba7a77cSGrant Erickson if ((status->ecces & SDRAM_ECCES_BNCE_ENCODE(lane)) != 0) {
439dba7a77cSGrant Erickson n = snprintf(buffer, size,
440dba7a77cSGrant Erickson "%s%u",
441dba7a77cSGrant Erickson (lanes++ ? ", " : ""), lane);
442dba7a77cSGrant Erickson
443dba7a77cSGrant Erickson if (n < 0 || n >= size)
444dba7a77cSGrant Erickson goto fail;
445dba7a77cSGrant Erickson
446dba7a77cSGrant Erickson buffer += n;
447dba7a77cSGrant Erickson size -= n;
448dba7a77cSGrant Erickson total += n;
449dba7a77cSGrant Erickson }
450dba7a77cSGrant Erickson }
451dba7a77cSGrant Erickson
452dba7a77cSGrant Erickson n = snprintf(buffer, size, "%s; ", lanes ? "" : "None");
453dba7a77cSGrant Erickson
454dba7a77cSGrant Erickson if (n < 0 || n >= size)
455dba7a77cSGrant Erickson goto fail;
456dba7a77cSGrant Erickson
457dba7a77cSGrant Erickson buffer += n;
458dba7a77cSGrant Erickson size -= n;
459dba7a77cSGrant Erickson total += n;
460dba7a77cSGrant Erickson
461dba7a77cSGrant Erickson fail:
462dba7a77cSGrant Erickson return total;
463dba7a77cSGrant Erickson }
464dba7a77cSGrant Erickson
465dba7a77cSGrant Erickson /**
466dba7a77cSGrant Erickson * ppc4xx_edac_generate_ecc_message - generate interpretted ECC status message
467dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance associated
468dba7a77cSGrant Erickson * with the ECCES message being generated.
469dba7a77cSGrant Erickson * @status: A pointer to the ECC status structure to generate the
470dba7a77cSGrant Erickson * message from.
471dba7a77cSGrant Erickson * @buffer: A pointer to the buffer in which to generate the
472dba7a77cSGrant Erickson * message.
473dba7a77cSGrant Erickson * @size: The size, in bytes, of space available in buffer.
474dba7a77cSGrant Erickson *
475dba7a77cSGrant Erickson * This routine generates to the provided buffer the portion of the
476dba7a77cSGrant Erickson * driver-unique report message associated with the ECCESS register of
477dba7a77cSGrant Erickson * the specified ECC status.
478dba7a77cSGrant Erickson *
479dba7a77cSGrant Erickson * Returns the number of characters generated on success; otherwise, <
480dba7a77cSGrant Erickson * 0 on error.
481dba7a77cSGrant Erickson */
482dba7a77cSGrant Erickson static int
ppc4xx_edac_generate_ecc_message(const struct mem_ctl_info * mci,const struct ppc4xx_ecc_status * status,char * buffer,size_t size)483dba7a77cSGrant Erickson ppc4xx_edac_generate_ecc_message(const struct mem_ctl_info *mci,
484dba7a77cSGrant Erickson const struct ppc4xx_ecc_status *status,
485dba7a77cSGrant Erickson char *buffer,
486dba7a77cSGrant Erickson size_t size)
487dba7a77cSGrant Erickson {
488dba7a77cSGrant Erickson int n, total = 0;
489dba7a77cSGrant Erickson
490dba7a77cSGrant Erickson n = ppc4xx_edac_generate_bank_message(mci, status, buffer, size);
491dba7a77cSGrant Erickson
492dba7a77cSGrant Erickson if (n < 0 || n >= size)
493dba7a77cSGrant Erickson goto fail;
494dba7a77cSGrant Erickson
495dba7a77cSGrant Erickson buffer += n;
496dba7a77cSGrant Erickson size -= n;
497dba7a77cSGrant Erickson total += n;
498dba7a77cSGrant Erickson
499dba7a77cSGrant Erickson n = ppc4xx_edac_generate_checkbit_message(mci, status, buffer, size);
500dba7a77cSGrant Erickson
501dba7a77cSGrant Erickson if (n < 0 || n >= size)
502dba7a77cSGrant Erickson goto fail;
503dba7a77cSGrant Erickson
504dba7a77cSGrant Erickson buffer += n;
505dba7a77cSGrant Erickson size -= n;
506dba7a77cSGrant Erickson total += n;
507dba7a77cSGrant Erickson
508dba7a77cSGrant Erickson n = ppc4xx_edac_generate_lane_message(mci, status, buffer, size);
509dba7a77cSGrant Erickson
510dba7a77cSGrant Erickson if (n < 0 || n >= size)
511dba7a77cSGrant Erickson goto fail;
512dba7a77cSGrant Erickson
513dba7a77cSGrant Erickson buffer += n;
514dba7a77cSGrant Erickson size -= n;
515dba7a77cSGrant Erickson total += n;
516dba7a77cSGrant Erickson
517dba7a77cSGrant Erickson fail:
518dba7a77cSGrant Erickson return total;
519dba7a77cSGrant Erickson }
520dba7a77cSGrant Erickson
521dba7a77cSGrant Erickson /**
522dba7a77cSGrant Erickson * ppc4xx_edac_generate_plb_message - generate interpretted PLB status message
523dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance associated
524dba7a77cSGrant Erickson * with the PLB message being generated.
525dba7a77cSGrant Erickson * @status: A pointer to the ECC status structure to generate the
526dba7a77cSGrant Erickson * message from.
527dba7a77cSGrant Erickson * @buffer: A pointer to the buffer in which to generate the
528dba7a77cSGrant Erickson * message.
529dba7a77cSGrant Erickson * @size: The size, in bytes, of space available in buffer.
530dba7a77cSGrant Erickson *
531dba7a77cSGrant Erickson * This routine generates to the provided buffer the portion of the
532dba7a77cSGrant Erickson * driver-unique report message associated with the PLB-related BESR
533dba7a77cSGrant Erickson * and/or WMIRQ registers of the specified ECC status.
534dba7a77cSGrant Erickson *
535dba7a77cSGrant Erickson * Returns the number of characters generated on success; otherwise, <
536dba7a77cSGrant Erickson * 0 on error.
537dba7a77cSGrant Erickson */
538dba7a77cSGrant Erickson static int
ppc4xx_edac_generate_plb_message(const struct mem_ctl_info * mci,const struct ppc4xx_ecc_status * status,char * buffer,size_t size)539dba7a77cSGrant Erickson ppc4xx_edac_generate_plb_message(const struct mem_ctl_info *mci,
540dba7a77cSGrant Erickson const struct ppc4xx_ecc_status *status,
541dba7a77cSGrant Erickson char *buffer,
542dba7a77cSGrant Erickson size_t size)
543dba7a77cSGrant Erickson {
544dba7a77cSGrant Erickson unsigned int master;
545dba7a77cSGrant Erickson bool read;
546dba7a77cSGrant Erickson
547dba7a77cSGrant Erickson if ((status->besr & SDRAM_BESR_MASK) == 0)
548dba7a77cSGrant Erickson return 0;
549dba7a77cSGrant Erickson
550dba7a77cSGrant Erickson if ((status->besr & SDRAM_BESR_M0ET_MASK) == SDRAM_BESR_M0ET_NONE)
551dba7a77cSGrant Erickson return 0;
552dba7a77cSGrant Erickson
553dba7a77cSGrant Erickson read = ((status->besr & SDRAM_BESR_M0RW_MASK) == SDRAM_BESR_M0RW_READ);
554dba7a77cSGrant Erickson
555dba7a77cSGrant Erickson master = SDRAM_BESR_M0ID_DECODE(status->besr);
556dba7a77cSGrant Erickson
557dba7a77cSGrant Erickson return snprintf(buffer, size,
558dba7a77cSGrant Erickson "%s error w/ PLB master %u \"%s\"; ",
559dba7a77cSGrant Erickson (read ? "Read" : "Write"),
560dba7a77cSGrant Erickson master,
561dba7a77cSGrant Erickson (((master >= SDRAM_PLB_M0ID_FIRST) &&
562dba7a77cSGrant Erickson (master <= SDRAM_PLB_M0ID_LAST)) ?
563dba7a77cSGrant Erickson ppc4xx_plb_masters[master] : "UNKNOWN"));
564dba7a77cSGrant Erickson }
565dba7a77cSGrant Erickson
566dba7a77cSGrant Erickson /**
567dba7a77cSGrant Erickson * ppc4xx_edac_generate_message - generate interpretted status message
568dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance associated
569dba7a77cSGrant Erickson * with the driver-unique message being generated.
570dba7a77cSGrant Erickson * @status: A pointer to the ECC status structure to generate the
571dba7a77cSGrant Erickson * message from.
572dba7a77cSGrant Erickson * @buffer: A pointer to the buffer in which to generate the
573dba7a77cSGrant Erickson * message.
574dba7a77cSGrant Erickson * @size: The size, in bytes, of space available in buffer.
575dba7a77cSGrant Erickson *
576dba7a77cSGrant Erickson * This routine generates to the provided buffer the driver-unique
577dba7a77cSGrant Erickson * EDAC report message from the specified ECC status.
578dba7a77cSGrant Erickson */
579dba7a77cSGrant Erickson static void
ppc4xx_edac_generate_message(const struct mem_ctl_info * mci,const struct ppc4xx_ecc_status * status,char * buffer,size_t size)580dba7a77cSGrant Erickson ppc4xx_edac_generate_message(const struct mem_ctl_info *mci,
581dba7a77cSGrant Erickson const struct ppc4xx_ecc_status *status,
582dba7a77cSGrant Erickson char *buffer,
583dba7a77cSGrant Erickson size_t size)
584dba7a77cSGrant Erickson {
585dba7a77cSGrant Erickson int n;
586dba7a77cSGrant Erickson
587dba7a77cSGrant Erickson if (buffer == NULL || size == 0)
588dba7a77cSGrant Erickson return;
589dba7a77cSGrant Erickson
590dba7a77cSGrant Erickson n = ppc4xx_edac_generate_ecc_message(mci, status, buffer, size);
591dba7a77cSGrant Erickson
592dba7a77cSGrant Erickson if (n < 0 || n >= size)
593dba7a77cSGrant Erickson return;
594dba7a77cSGrant Erickson
595dba7a77cSGrant Erickson buffer += n;
596dba7a77cSGrant Erickson size -= n;
597dba7a77cSGrant Erickson
598dba7a77cSGrant Erickson ppc4xx_edac_generate_plb_message(mci, status, buffer, size);
599dba7a77cSGrant Erickson }
600dba7a77cSGrant Erickson
601dba7a77cSGrant Erickson #ifdef DEBUG
602dba7a77cSGrant Erickson /**
603dba7a77cSGrant Erickson * ppc4xx_ecc_dump_status - dump controller ECC status registers
604dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance
605dba7a77cSGrant Erickson * associated with the status being dumped.
606dba7a77cSGrant Erickson * @status: A pointer to the ECC status structure to generate the
607dba7a77cSGrant Erickson * dump from.
608dba7a77cSGrant Erickson *
609dba7a77cSGrant Erickson * This routine dumps to the kernel log buffer the raw and
610dba7a77cSGrant Erickson * interpretted specified ECC status.
611dba7a77cSGrant Erickson */
612dba7a77cSGrant Erickson static void
ppc4xx_ecc_dump_status(const struct mem_ctl_info * mci,const struct ppc4xx_ecc_status * status)613dba7a77cSGrant Erickson ppc4xx_ecc_dump_status(const struct mem_ctl_info *mci,
614dba7a77cSGrant Erickson const struct ppc4xx_ecc_status *status)
615dba7a77cSGrant Erickson {
616dba7a77cSGrant Erickson char message[PPC4XX_EDAC_MESSAGE_SIZE];
617dba7a77cSGrant Erickson
618dba7a77cSGrant Erickson ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
619dba7a77cSGrant Erickson
620dba7a77cSGrant Erickson ppc4xx_edac_mc_printk(KERN_INFO, mci,
621dba7a77cSGrant Erickson "\n"
622dba7a77cSGrant Erickson "\tECCES: 0x%08x\n"
623dba7a77cSGrant Erickson "\tWMIRQ: 0x%08x\n"
624dba7a77cSGrant Erickson "\tBESR: 0x%08x\n"
625dba7a77cSGrant Erickson "\tBEAR: 0x%08x%08x\n"
626dba7a77cSGrant Erickson "\t%s\n",
627dba7a77cSGrant Erickson status->ecces,
628dba7a77cSGrant Erickson status->wmirq,
629dba7a77cSGrant Erickson status->besr,
630dba7a77cSGrant Erickson status->bearh,
631dba7a77cSGrant Erickson status->bearl,
632dba7a77cSGrant Erickson message);
633dba7a77cSGrant Erickson }
634dba7a77cSGrant Erickson #endif /* DEBUG */
635dba7a77cSGrant Erickson
636dba7a77cSGrant Erickson /**
637dba7a77cSGrant Erickson * ppc4xx_ecc_get_status - get controller ECC status
638dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance
639dba7a77cSGrant Erickson * associated with the status being retrieved.
640dba7a77cSGrant Erickson * @status: A pointer to the ECC status structure to populate the
641dba7a77cSGrant Erickson * ECC status with.
642dba7a77cSGrant Erickson *
643dba7a77cSGrant Erickson * This routine reads and masks, as appropriate, all the relevant
644dba7a77cSGrant Erickson * status registers that deal with ibm,sdram-4xx-ddr2 ECC errors.
645dba7a77cSGrant Erickson * While we read all of them, for correctable errors, we only expect
646dba7a77cSGrant Erickson * to deal with ECCES. For uncorrectable errors, we expect to deal
647dba7a77cSGrant Erickson * with all of them.
648dba7a77cSGrant Erickson */
649dba7a77cSGrant Erickson static void
ppc4xx_ecc_get_status(const struct mem_ctl_info * mci,struct ppc4xx_ecc_status * status)650dba7a77cSGrant Erickson ppc4xx_ecc_get_status(const struct mem_ctl_info *mci,
651dba7a77cSGrant Erickson struct ppc4xx_ecc_status *status)
652dba7a77cSGrant Erickson {
653dba7a77cSGrant Erickson const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
654dba7a77cSGrant Erickson const dcr_host_t *dcr_host = &pdata->dcr_host;
655dba7a77cSGrant Erickson
656dba7a77cSGrant Erickson status->ecces = mfsdram(dcr_host, SDRAM_ECCES) & SDRAM_ECCES_MASK;
657dba7a77cSGrant Erickson status->wmirq = mfsdram(dcr_host, SDRAM_WMIRQ) & SDRAM_WMIRQ_MASK;
658dba7a77cSGrant Erickson status->besr = mfsdram(dcr_host, SDRAM_BESR) & SDRAM_BESR_MASK;
659dba7a77cSGrant Erickson status->bearl = mfsdram(dcr_host, SDRAM_BEARL);
660dba7a77cSGrant Erickson status->bearh = mfsdram(dcr_host, SDRAM_BEARH);
661dba7a77cSGrant Erickson }
662dba7a77cSGrant Erickson
663dba7a77cSGrant Erickson /**
664dba7a77cSGrant Erickson * ppc4xx_ecc_clear_status - clear controller ECC status
665dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance
666dba7a77cSGrant Erickson * associated with the status being cleared.
667dba7a77cSGrant Erickson * @status: A pointer to the ECC status structure containing the
668dba7a77cSGrant Erickson * values to write to clear the ECC status.
669dba7a77cSGrant Erickson *
670dba7a77cSGrant Erickson * This routine clears--by writing the masked (as appropriate) status
671dba7a77cSGrant Erickson * values back to--the status registers that deal with
672dba7a77cSGrant Erickson * ibm,sdram-4xx-ddr2 ECC errors.
673dba7a77cSGrant Erickson */
674dba7a77cSGrant Erickson static void
ppc4xx_ecc_clear_status(const struct mem_ctl_info * mci,const struct ppc4xx_ecc_status * status)675dba7a77cSGrant Erickson ppc4xx_ecc_clear_status(const struct mem_ctl_info *mci,
676dba7a77cSGrant Erickson const struct ppc4xx_ecc_status *status)
677dba7a77cSGrant Erickson {
678dba7a77cSGrant Erickson const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
679dba7a77cSGrant Erickson const dcr_host_t *dcr_host = &pdata->dcr_host;
680dba7a77cSGrant Erickson
681dba7a77cSGrant Erickson mtsdram(dcr_host, SDRAM_ECCES, status->ecces & SDRAM_ECCES_MASK);
682dba7a77cSGrant Erickson mtsdram(dcr_host, SDRAM_WMIRQ, status->wmirq & SDRAM_WMIRQ_MASK);
683dba7a77cSGrant Erickson mtsdram(dcr_host, SDRAM_BESR, status->besr & SDRAM_BESR_MASK);
684dba7a77cSGrant Erickson mtsdram(dcr_host, SDRAM_BEARL, 0);
685dba7a77cSGrant Erickson mtsdram(dcr_host, SDRAM_BEARH, 0);
686dba7a77cSGrant Erickson }
687dba7a77cSGrant Erickson
688dba7a77cSGrant Erickson /**
689dba7a77cSGrant Erickson * ppc4xx_edac_handle_ce - handle controller correctable ECC error (CE)
690dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance
691dba7a77cSGrant Erickson * associated with the correctable error being handled and reported.
692dba7a77cSGrant Erickson * @status: A pointer to the ECC status structure associated with
693dba7a77cSGrant Erickson * the correctable error being handled and reported.
694dba7a77cSGrant Erickson *
695dba7a77cSGrant Erickson * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
696dba7a77cSGrant Erickson * correctable error. Per the aforementioned discussion, there's not
697dba7a77cSGrant Erickson * enough status available to use the full EDAC correctable error
698dba7a77cSGrant Erickson * interface, so we just pass driver-unique message to the "no info"
699dba7a77cSGrant Erickson * interface.
700dba7a77cSGrant Erickson */
701dba7a77cSGrant Erickson static void
ppc4xx_edac_handle_ce(struct mem_ctl_info * mci,const struct ppc4xx_ecc_status * status)702dba7a77cSGrant Erickson ppc4xx_edac_handle_ce(struct mem_ctl_info *mci,
703dba7a77cSGrant Erickson const struct ppc4xx_ecc_status *status)
704dba7a77cSGrant Erickson {
705dba7a77cSGrant Erickson int row;
706dba7a77cSGrant Erickson char message[PPC4XX_EDAC_MESSAGE_SIZE];
707dba7a77cSGrant Erickson
708dba7a77cSGrant Erickson ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
709dba7a77cSGrant Erickson
710dba7a77cSGrant Erickson for (row = 0; row < mci->nr_csrows; row++)
711dba7a77cSGrant Erickson if (ppc4xx_edac_check_bank_error(status, row))
7129eb07a7fSMauro Carvalho Chehab edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
71394d93374SMauro Carvalho Chehab 0, 0, 0,
71494d93374SMauro Carvalho Chehab row, 0, -1,
71503f7eae8SMauro Carvalho Chehab message, "");
716dba7a77cSGrant Erickson }
717dba7a77cSGrant Erickson
718dba7a77cSGrant Erickson /**
719dba7a77cSGrant Erickson * ppc4xx_edac_handle_ue - handle controller uncorrectable ECC error (UE)
720dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance
721dba7a77cSGrant Erickson * associated with the uncorrectable error being handled and
722dba7a77cSGrant Erickson * reported.
723dba7a77cSGrant Erickson * @status: A pointer to the ECC status structure associated with
724dba7a77cSGrant Erickson * the uncorrectable error being handled and reported.
725dba7a77cSGrant Erickson *
726dba7a77cSGrant Erickson * This routine handles an ibm,sdram-4xx-ddr2 controller ECC
727dba7a77cSGrant Erickson * uncorrectable error.
728dba7a77cSGrant Erickson */
729dba7a77cSGrant Erickson static void
ppc4xx_edac_handle_ue(struct mem_ctl_info * mci,const struct ppc4xx_ecc_status * status)730dba7a77cSGrant Erickson ppc4xx_edac_handle_ue(struct mem_ctl_info *mci,
731dba7a77cSGrant Erickson const struct ppc4xx_ecc_status *status)
732dba7a77cSGrant Erickson {
733dba7a77cSGrant Erickson const u64 bear = ((u64)status->bearh << 32 | status->bearl);
734dba7a77cSGrant Erickson const unsigned long page = bear >> PAGE_SHIFT;
735dba7a77cSGrant Erickson const unsigned long offset = bear & ~PAGE_MASK;
736dba7a77cSGrant Erickson int row;
737dba7a77cSGrant Erickson char message[PPC4XX_EDAC_MESSAGE_SIZE];
738dba7a77cSGrant Erickson
739dba7a77cSGrant Erickson ppc4xx_edac_generate_message(mci, status, message, sizeof(message));
740dba7a77cSGrant Erickson
741dba7a77cSGrant Erickson for (row = 0; row < mci->nr_csrows; row++)
742dba7a77cSGrant Erickson if (ppc4xx_edac_check_bank_error(status, row))
7439eb07a7fSMauro Carvalho Chehab edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
74494d93374SMauro Carvalho Chehab page, offset, 0,
74594d93374SMauro Carvalho Chehab row, 0, -1,
74603f7eae8SMauro Carvalho Chehab message, "");
747dba7a77cSGrant Erickson }
748dba7a77cSGrant Erickson
749dba7a77cSGrant Erickson /**
750dba7a77cSGrant Erickson * ppc4xx_edac_check - check controller for ECC errors
751dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance
752dba7a77cSGrant Erickson * associated with the ibm,sdram-4xx-ddr2 controller being
753dba7a77cSGrant Erickson * checked.
754dba7a77cSGrant Erickson *
755dba7a77cSGrant Erickson * This routine is used to check and post ECC errors and is called by
756dba7a77cSGrant Erickson * both the EDAC polling thread and this driver's CE and UE interrupt
757dba7a77cSGrant Erickson * handler.
758dba7a77cSGrant Erickson */
759dba7a77cSGrant Erickson static void
ppc4xx_edac_check(struct mem_ctl_info * mci)760dba7a77cSGrant Erickson ppc4xx_edac_check(struct mem_ctl_info *mci)
761dba7a77cSGrant Erickson {
762dba7a77cSGrant Erickson #ifdef DEBUG
763dba7a77cSGrant Erickson static unsigned int count;
764dba7a77cSGrant Erickson #endif
765dba7a77cSGrant Erickson struct ppc4xx_ecc_status status;
766dba7a77cSGrant Erickson
767dba7a77cSGrant Erickson ppc4xx_ecc_get_status(mci, &status);
768dba7a77cSGrant Erickson
769dba7a77cSGrant Erickson #ifdef DEBUG
770dba7a77cSGrant Erickson if (count++ % 30 == 0)
771dba7a77cSGrant Erickson ppc4xx_ecc_dump_status(mci, &status);
772dba7a77cSGrant Erickson #endif
773dba7a77cSGrant Erickson
774dba7a77cSGrant Erickson if (status.ecces & SDRAM_ECCES_UE)
775dba7a77cSGrant Erickson ppc4xx_edac_handle_ue(mci, &status);
776dba7a77cSGrant Erickson
777dba7a77cSGrant Erickson if (status.ecces & SDRAM_ECCES_CE)
778dba7a77cSGrant Erickson ppc4xx_edac_handle_ce(mci, &status);
779dba7a77cSGrant Erickson
780dba7a77cSGrant Erickson ppc4xx_ecc_clear_status(mci, &status);
781dba7a77cSGrant Erickson }
782dba7a77cSGrant Erickson
783dba7a77cSGrant Erickson /**
784dba7a77cSGrant Erickson * ppc4xx_edac_isr - SEC (CE) and DED (UE) interrupt service routine
785dba7a77cSGrant Erickson * @irq: The virtual interrupt number being serviced.
786dba7a77cSGrant Erickson * @dev_id: A pointer to the EDAC memory controller instance
787dba7a77cSGrant Erickson * associated with the interrupt being handled.
788dba7a77cSGrant Erickson *
789dba7a77cSGrant Erickson * This routine implements the interrupt handler for both correctable
790dba7a77cSGrant Erickson * (CE) and uncorrectable (UE) ECC errors for the ibm,sdram-4xx-ddr2
791dba7a77cSGrant Erickson * controller. It simply calls through to the same routine used during
792dba7a77cSGrant Erickson * polling to check, report and clear the ECC status.
793dba7a77cSGrant Erickson *
794dba7a77cSGrant Erickson * Unconditionally returns IRQ_HANDLED.
795dba7a77cSGrant Erickson */
796dba7a77cSGrant Erickson static irqreturn_t
ppc4xx_edac_isr(int irq,void * dev_id)797dba7a77cSGrant Erickson ppc4xx_edac_isr(int irq, void *dev_id)
798dba7a77cSGrant Erickson {
799dba7a77cSGrant Erickson struct mem_ctl_info *mci = dev_id;
800dba7a77cSGrant Erickson
801dba7a77cSGrant Erickson ppc4xx_edac_check(mci);
802dba7a77cSGrant Erickson
803dba7a77cSGrant Erickson return IRQ_HANDLED;
804dba7a77cSGrant Erickson }
805dba7a77cSGrant Erickson
806dba7a77cSGrant Erickson /**
807dba7a77cSGrant Erickson * ppc4xx_edac_get_dtype - return the controller memory width
808dba7a77cSGrant Erickson * @mcopt1: The 32-bit Memory Controller Option 1 register value
809dba7a77cSGrant Erickson * currently set for the controller, from which the width
810dba7a77cSGrant Erickson * is derived.
811dba7a77cSGrant Erickson *
812dba7a77cSGrant Erickson * This routine returns the EDAC device type width appropriate for the
813dba7a77cSGrant Erickson * current controller configuration.
814dba7a77cSGrant Erickson *
815dba7a77cSGrant Erickson * TODO: This needs to be conditioned dynamically through feature
816dba7a77cSGrant Erickson * flags or some such when other controller variants are supported as
817dba7a77cSGrant Erickson * the 405EX[r] is 16-/32-bit and the others are 32-/64-bit with the
818dba7a77cSGrant Erickson * 16- and 64-bit field definition/value/enumeration (b1) overloaded
819dba7a77cSGrant Erickson * among them.
820dba7a77cSGrant Erickson *
821dba7a77cSGrant Erickson * Returns a device type width enumeration.
822dba7a77cSGrant Erickson */
ppc4xx_edac_get_dtype(u32 mcopt1)8239b3c6e85SGreg Kroah-Hartman static enum dev_type ppc4xx_edac_get_dtype(u32 mcopt1)
824dba7a77cSGrant Erickson {
825dba7a77cSGrant Erickson switch (mcopt1 & SDRAM_MCOPT1_WDTH_MASK) {
826dba7a77cSGrant Erickson case SDRAM_MCOPT1_WDTH_16:
827dba7a77cSGrant Erickson return DEV_X2;
828dba7a77cSGrant Erickson case SDRAM_MCOPT1_WDTH_32:
829dba7a77cSGrant Erickson return DEV_X4;
830dba7a77cSGrant Erickson default:
831dba7a77cSGrant Erickson return DEV_UNKNOWN;
832dba7a77cSGrant Erickson }
833dba7a77cSGrant Erickson }
834dba7a77cSGrant Erickson
835dba7a77cSGrant Erickson /**
836dba7a77cSGrant Erickson * ppc4xx_edac_get_mtype - return controller memory type
837dba7a77cSGrant Erickson * @mcopt1: The 32-bit Memory Controller Option 1 register value
838dba7a77cSGrant Erickson * currently set for the controller, from which the memory type
839dba7a77cSGrant Erickson * is derived.
840dba7a77cSGrant Erickson *
841dba7a77cSGrant Erickson * This routine returns the EDAC memory type appropriate for the
842dba7a77cSGrant Erickson * current controller configuration.
843dba7a77cSGrant Erickson *
844dba7a77cSGrant Erickson * Returns a memory type enumeration.
845dba7a77cSGrant Erickson */
ppc4xx_edac_get_mtype(u32 mcopt1)8469b3c6e85SGreg Kroah-Hartman static enum mem_type ppc4xx_edac_get_mtype(u32 mcopt1)
847dba7a77cSGrant Erickson {
848dba7a77cSGrant Erickson bool rden = ((mcopt1 & SDRAM_MCOPT1_RDEN_MASK) == SDRAM_MCOPT1_RDEN);
849dba7a77cSGrant Erickson
850dba7a77cSGrant Erickson switch (mcopt1 & SDRAM_MCOPT1_DDR_TYPE_MASK) {
851dba7a77cSGrant Erickson case SDRAM_MCOPT1_DDR2_TYPE:
852dba7a77cSGrant Erickson return rden ? MEM_RDDR2 : MEM_DDR2;
853dba7a77cSGrant Erickson case SDRAM_MCOPT1_DDR1_TYPE:
854dba7a77cSGrant Erickson return rden ? MEM_RDDR : MEM_DDR;
855dba7a77cSGrant Erickson default:
856dba7a77cSGrant Erickson return MEM_UNKNOWN;
857dba7a77cSGrant Erickson }
858dba7a77cSGrant Erickson }
859dba7a77cSGrant Erickson
860dba7a77cSGrant Erickson /**
861b595076aSUwe Kleine-König * ppc4xx_edac_init_csrows - initialize driver instance rows
862dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance
863dba7a77cSGrant Erickson * associated with the ibm,sdram-4xx-ddr2 controller for which
864dba7a77cSGrant Erickson * the csrows (i.e. banks/ranks) are being initialized.
865dba7a77cSGrant Erickson * @mcopt1: The 32-bit Memory Controller Option 1 register value
866dba7a77cSGrant Erickson * currently set for the controller, from which bank width
867dba7a77cSGrant Erickson * and memory typ information is derived.
868dba7a77cSGrant Erickson *
869b595076aSUwe Kleine-König * This routine initializes the virtual "chip select rows" associated
870dba7a77cSGrant Erickson * with the EDAC memory controller instance. An ibm,sdram-4xx-ddr2
871dba7a77cSGrant Erickson * controller bank/rank is mapped to a row.
872dba7a77cSGrant Erickson *
873dba7a77cSGrant Erickson * Returns 0 if OK; otherwise, -EINVAL if the memory bank size
874dba7a77cSGrant Erickson * configuration cannot be determined.
875dba7a77cSGrant Erickson */
ppc4xx_edac_init_csrows(struct mem_ctl_info * mci,u32 mcopt1)8769b3c6e85SGreg Kroah-Hartman static int ppc4xx_edac_init_csrows(struct mem_ctl_info *mci, u32 mcopt1)
877dba7a77cSGrant Erickson {
878dba7a77cSGrant Erickson const struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
879dba7a77cSGrant Erickson int status = 0;
880dba7a77cSGrant Erickson enum mem_type mtype;
881dba7a77cSGrant Erickson enum dev_type dtype;
882dba7a77cSGrant Erickson enum edac_type edac_mode;
883084a4fccSMauro Carvalho Chehab int row, j;
884a895bf8bSMauro Carvalho Chehab u32 mbxcf, size, nr_pages;
885dba7a77cSGrant Erickson
886dba7a77cSGrant Erickson /* Establish the memory type and width */
887dba7a77cSGrant Erickson
888dba7a77cSGrant Erickson mtype = ppc4xx_edac_get_mtype(mcopt1);
889dba7a77cSGrant Erickson dtype = ppc4xx_edac_get_dtype(mcopt1);
890dba7a77cSGrant Erickson
891dba7a77cSGrant Erickson /* Establish EDAC mode */
892dba7a77cSGrant Erickson
893dba7a77cSGrant Erickson if (mci->edac_cap & EDAC_FLAG_SECDED)
894dba7a77cSGrant Erickson edac_mode = EDAC_SECDED;
895dba7a77cSGrant Erickson else if (mci->edac_cap & EDAC_FLAG_EC)
896dba7a77cSGrant Erickson edac_mode = EDAC_EC;
897dba7a77cSGrant Erickson else
898dba7a77cSGrant Erickson edac_mode = EDAC_NONE;
899dba7a77cSGrant Erickson
900dba7a77cSGrant Erickson /*
901dba7a77cSGrant Erickson * Initialize each chip select row structure which correspond
902dba7a77cSGrant Erickson * 1:1 with a controller bank/rank.
903dba7a77cSGrant Erickson */
904dba7a77cSGrant Erickson
905dba7a77cSGrant Erickson for (row = 0; row < mci->nr_csrows; row++) {
9065c16179bSMichael Walle struct csrow_info *csi = mci->csrows[row];
907dba7a77cSGrant Erickson
908dba7a77cSGrant Erickson /*
909dba7a77cSGrant Erickson * Get the configuration settings for this
910dba7a77cSGrant Erickson * row/bank/rank and skip disabled banks.
911dba7a77cSGrant Erickson */
912dba7a77cSGrant Erickson
913dba7a77cSGrant Erickson mbxcf = mfsdram(&pdata->dcr_host, SDRAM_MBXCF(row));
914dba7a77cSGrant Erickson
915dba7a77cSGrant Erickson if ((mbxcf & SDRAM_MBCF_BE_MASK) != SDRAM_MBCF_BE_ENABLE)
916dba7a77cSGrant Erickson continue;
917dba7a77cSGrant Erickson
918dba7a77cSGrant Erickson /* Map the bank configuration size setting to pages. */
919dba7a77cSGrant Erickson
920dba7a77cSGrant Erickson size = mbxcf & SDRAM_MBCF_SZ_MASK;
921dba7a77cSGrant Erickson
922dba7a77cSGrant Erickson switch (size) {
923dba7a77cSGrant Erickson case SDRAM_MBCF_SZ_4MB:
924dba7a77cSGrant Erickson case SDRAM_MBCF_SZ_8MB:
925dba7a77cSGrant Erickson case SDRAM_MBCF_SZ_16MB:
926dba7a77cSGrant Erickson case SDRAM_MBCF_SZ_32MB:
927dba7a77cSGrant Erickson case SDRAM_MBCF_SZ_64MB:
928dba7a77cSGrant Erickson case SDRAM_MBCF_SZ_128MB:
929dba7a77cSGrant Erickson case SDRAM_MBCF_SZ_256MB:
930dba7a77cSGrant Erickson case SDRAM_MBCF_SZ_512MB:
931dba7a77cSGrant Erickson case SDRAM_MBCF_SZ_1GB:
932dba7a77cSGrant Erickson case SDRAM_MBCF_SZ_2GB:
933dba7a77cSGrant Erickson case SDRAM_MBCF_SZ_4GB:
934dba7a77cSGrant Erickson case SDRAM_MBCF_SZ_8GB:
935a895bf8bSMauro Carvalho Chehab nr_pages = SDRAM_MBCF_SZ_TO_PAGES(size);
936dba7a77cSGrant Erickson break;
937dba7a77cSGrant Erickson default:
938dba7a77cSGrant Erickson ppc4xx_edac_mc_printk(KERN_ERR, mci,
939dba7a77cSGrant Erickson "Unrecognized memory bank %d "
940dba7a77cSGrant Erickson "size 0x%08x\n",
941dba7a77cSGrant Erickson row, SDRAM_MBCF_SZ_DECODE(size));
942dba7a77cSGrant Erickson status = -EINVAL;
943dba7a77cSGrant Erickson goto done;
944dba7a77cSGrant Erickson }
945dba7a77cSGrant Erickson
946dba7a77cSGrant Erickson /*
947dba7a77cSGrant Erickson * It's unclear exactly what grain should be set to
948dba7a77cSGrant Erickson * here. The SDRAM_ECCES register allows resolution of
949dba7a77cSGrant Erickson * an error down to a nibble which would potentially
950dba7a77cSGrant Erickson * argue for a grain of '1' byte, even though we only
951dba7a77cSGrant Erickson * know the associated address for uncorrectable
952dba7a77cSGrant Erickson * errors. This value is not used at present for
953dba7a77cSGrant Erickson * anything other than error reporting so getting it
954dba7a77cSGrant Erickson * wrong should be of little consequence. Other
955dba7a77cSGrant Erickson * possible values would be the PLB width (16), the
956dba7a77cSGrant Erickson * page size (PAGE_SIZE) or the memory width (2 or 4).
957dba7a77cSGrant Erickson */
958084a4fccSMauro Carvalho Chehab for (j = 0; j < csi->nr_channels; j++) {
9592d34056dSPranith Kumar struct dimm_info *dimm = csi->channels[j]->dimm;
960dba7a77cSGrant Erickson
961a895bf8bSMauro Carvalho Chehab dimm->nr_pages = nr_pages / csi->nr_channels;
962084a4fccSMauro Carvalho Chehab dimm->grain = 1;
963dba7a77cSGrant Erickson
964084a4fccSMauro Carvalho Chehab dimm->mtype = mtype;
965084a4fccSMauro Carvalho Chehab dimm->dtype = dtype;
966dba7a77cSGrant Erickson
967084a4fccSMauro Carvalho Chehab dimm->edac_mode = edac_mode;
968dba7a77cSGrant Erickson }
969084a4fccSMauro Carvalho Chehab }
970dba7a77cSGrant Erickson
971dba7a77cSGrant Erickson done:
972dba7a77cSGrant Erickson return status;
973dba7a77cSGrant Erickson }
974dba7a77cSGrant Erickson
975dba7a77cSGrant Erickson /**
976b595076aSUwe Kleine-König * ppc4xx_edac_mc_init - initialize driver instance
977dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance being
978dba7a77cSGrant Erickson * initialized.
979dba7a77cSGrant Erickson * @op: A pointer to the OpenFirmware device tree node associated
980dba7a77cSGrant Erickson * with the controller this EDAC instance is bound to.
981dba7a77cSGrant Erickson * @dcr_host: A pointer to the DCR data containing the DCR mapping
982dba7a77cSGrant Erickson * for this controller instance.
983dba7a77cSGrant Erickson * @mcopt1: The 32-bit Memory Controller Option 1 register value
984dba7a77cSGrant Erickson * currently set for the controller, from which ECC capabilities
985dba7a77cSGrant Erickson * and scrub mode are derived.
986dba7a77cSGrant Erickson *
987dba7a77cSGrant Erickson * This routine performs initialization of the EDAC memory controller
988dba7a77cSGrant Erickson * instance and related driver-private data associated with the
989dba7a77cSGrant Erickson * ibm,sdram-4xx-ddr2 memory controller the instance is bound to.
990dba7a77cSGrant Erickson *
991dba7a77cSGrant Erickson * Returns 0 if OK; otherwise, < 0 on error.
992dba7a77cSGrant Erickson */
ppc4xx_edac_mc_init(struct mem_ctl_info * mci,struct platform_device * op,const dcr_host_t * dcr_host,u32 mcopt1)9939b3c6e85SGreg Kroah-Hartman static int ppc4xx_edac_mc_init(struct mem_ctl_info *mci,
9942dc11581SGrant Likely struct platform_device *op,
9959b3c6e85SGreg Kroah-Hartman const dcr_host_t *dcr_host, u32 mcopt1)
996dba7a77cSGrant Erickson {
997dba7a77cSGrant Erickson int status = 0;
998dba7a77cSGrant Erickson const u32 memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
999dba7a77cSGrant Erickson struct ppc4xx_edac_pdata *pdata = NULL;
1000a26f95feSAnatolij Gustschin const struct device_node *np = op->dev.of_node;
1001dba7a77cSGrant Erickson
1002b1608d69SGrant Likely if (of_match_device(ppc4xx_edac_match, &op->dev) == NULL)
1003dba7a77cSGrant Erickson return -EINVAL;
1004dba7a77cSGrant Erickson
1005dba7a77cSGrant Erickson /* Initial driver pointers and private data */
1006dba7a77cSGrant Erickson
1007fd687502SMauro Carvalho Chehab mci->pdev = &op->dev;
1008dba7a77cSGrant Erickson
1009fd687502SMauro Carvalho Chehab dev_set_drvdata(mci->pdev, mci);
1010dba7a77cSGrant Erickson
1011dba7a77cSGrant Erickson pdata = mci->pvt_info;
1012dba7a77cSGrant Erickson
1013dba7a77cSGrant Erickson pdata->dcr_host = *dcr_host;
1014dba7a77cSGrant Erickson
1015dba7a77cSGrant Erickson /* Initialize controller capabilities and configuration */
1016dba7a77cSGrant Erickson
1017dba7a77cSGrant Erickson mci->mtype_cap = (MEM_FLAG_DDR | MEM_FLAG_RDDR |
1018dba7a77cSGrant Erickson MEM_FLAG_DDR2 | MEM_FLAG_RDDR2);
1019dba7a77cSGrant Erickson
1020dba7a77cSGrant Erickson mci->edac_ctl_cap = (EDAC_FLAG_NONE |
1021dba7a77cSGrant Erickson EDAC_FLAG_EC |
1022dba7a77cSGrant Erickson EDAC_FLAG_SECDED);
1023dba7a77cSGrant Erickson
1024dba7a77cSGrant Erickson mci->scrub_cap = SCRUB_NONE;
1025dba7a77cSGrant Erickson mci->scrub_mode = SCRUB_NONE;
1026dba7a77cSGrant Erickson
1027dba7a77cSGrant Erickson /*
1028dba7a77cSGrant Erickson * Update the actual capabilites based on the MCOPT1[MCHK]
1029dba7a77cSGrant Erickson * settings. Scrubbing is only useful if reporting is enabled.
1030dba7a77cSGrant Erickson */
1031dba7a77cSGrant Erickson
1032dba7a77cSGrant Erickson switch (memcheck) {
1033dba7a77cSGrant Erickson case SDRAM_MCOPT1_MCHK_CHK:
1034dba7a77cSGrant Erickson mci->edac_cap = EDAC_FLAG_EC;
1035dba7a77cSGrant Erickson break;
1036dba7a77cSGrant Erickson case SDRAM_MCOPT1_MCHK_CHK_REP:
1037dba7a77cSGrant Erickson mci->edac_cap = (EDAC_FLAG_EC | EDAC_FLAG_SECDED);
1038dba7a77cSGrant Erickson mci->scrub_mode = SCRUB_SW_SRC;
1039dba7a77cSGrant Erickson break;
1040dba7a77cSGrant Erickson default:
1041dba7a77cSGrant Erickson mci->edac_cap = EDAC_FLAG_NONE;
1042dba7a77cSGrant Erickson break;
1043dba7a77cSGrant Erickson }
1044dba7a77cSGrant Erickson
1045dba7a77cSGrant Erickson /* Initialize strings */
1046dba7a77cSGrant Erickson
1047dba7a77cSGrant Erickson mci->mod_name = PPC4XX_EDAC_MODULE_NAME;
1048e0e04274SZheng Yongjun mci->ctl_name = ppc4xx_edac_match->compatible;
1049dba7a77cSGrant Erickson mci->dev_name = np->full_name;
1050dba7a77cSGrant Erickson
1051dba7a77cSGrant Erickson /* Initialize callbacks */
1052dba7a77cSGrant Erickson
1053dba7a77cSGrant Erickson mci->edac_check = ppc4xx_edac_check;
1054dba7a77cSGrant Erickson mci->ctl_page_to_phys = NULL;
1055dba7a77cSGrant Erickson
1056dba7a77cSGrant Erickson /* Initialize chip select rows */
1057dba7a77cSGrant Erickson
1058dba7a77cSGrant Erickson status = ppc4xx_edac_init_csrows(mci, mcopt1);
1059dba7a77cSGrant Erickson
1060dba7a77cSGrant Erickson if (status)
1061dba7a77cSGrant Erickson ppc4xx_edac_mc_printk(KERN_ERR, mci,
1062dba7a77cSGrant Erickson "Failed to initialize rows!\n");
1063dba7a77cSGrant Erickson
1064dba7a77cSGrant Erickson return status;
1065dba7a77cSGrant Erickson }
1066dba7a77cSGrant Erickson
1067dba7a77cSGrant Erickson /**
1068dba7a77cSGrant Erickson * ppc4xx_edac_register_irq - setup and register controller interrupts
1069dba7a77cSGrant Erickson * @op: A pointer to the OpenFirmware device tree node associated
1070dba7a77cSGrant Erickson * with the controller this EDAC instance is bound to.
1071dba7a77cSGrant Erickson * @mci: A pointer to the EDAC memory controller instance
1072dba7a77cSGrant Erickson * associated with the ibm,sdram-4xx-ddr2 controller for which
1073dba7a77cSGrant Erickson * interrupts are being registered.
1074dba7a77cSGrant Erickson *
1075dba7a77cSGrant Erickson * This routine parses the correctable (CE) and uncorrectable error (UE)
1076dba7a77cSGrant Erickson * interrupts from the device tree node and maps and assigns them to
1077dba7a77cSGrant Erickson * the associated EDAC memory controller instance.
1078dba7a77cSGrant Erickson *
1079dba7a77cSGrant Erickson * Returns 0 if OK; otherwise, -ENODEV if the interrupts could not be
1080dba7a77cSGrant Erickson * mapped and assigned.
1081dba7a77cSGrant Erickson */
ppc4xx_edac_register_irq(struct platform_device * op,struct mem_ctl_info * mci)10829b3c6e85SGreg Kroah-Hartman static int ppc4xx_edac_register_irq(struct platform_device *op,
10839b3c6e85SGreg Kroah-Hartman struct mem_ctl_info *mci)
1084dba7a77cSGrant Erickson {
1085dba7a77cSGrant Erickson int status = 0;
1086dba7a77cSGrant Erickson int ded_irq, sec_irq;
1087dba7a77cSGrant Erickson struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1088a26f95feSAnatolij Gustschin struct device_node *np = op->dev.of_node;
1089dba7a77cSGrant Erickson
1090dba7a77cSGrant Erickson ded_irq = irq_of_parse_and_map(np, INTMAP_ECCDED_INDEX);
1091dba7a77cSGrant Erickson sec_irq = irq_of_parse_and_map(np, INTMAP_ECCSEC_INDEX);
1092dba7a77cSGrant Erickson
109337209572SMichael Ellerman if (!ded_irq || !sec_irq) {
1094dba7a77cSGrant Erickson ppc4xx_edac_mc_printk(KERN_ERR, mci,
1095dba7a77cSGrant Erickson "Unable to map interrupts.\n");
1096dba7a77cSGrant Erickson status = -ENODEV;
1097dba7a77cSGrant Erickson goto fail;
1098dba7a77cSGrant Erickson }
1099dba7a77cSGrant Erickson
1100dba7a77cSGrant Erickson status = request_irq(ded_irq,
1101dba7a77cSGrant Erickson ppc4xx_edac_isr,
11025c43cbdfSMichael Opdenacker 0,
1103dba7a77cSGrant Erickson "[EDAC] MC ECCDED",
1104dba7a77cSGrant Erickson mci);
1105dba7a77cSGrant Erickson
1106dba7a77cSGrant Erickson if (status < 0) {
1107dba7a77cSGrant Erickson ppc4xx_edac_mc_printk(KERN_ERR, mci,
1108dba7a77cSGrant Erickson "Unable to request irq %d for ECC DED",
1109dba7a77cSGrant Erickson ded_irq);
1110dba7a77cSGrant Erickson status = -ENODEV;
1111dba7a77cSGrant Erickson goto fail1;
1112dba7a77cSGrant Erickson }
1113dba7a77cSGrant Erickson
1114dba7a77cSGrant Erickson status = request_irq(sec_irq,
1115dba7a77cSGrant Erickson ppc4xx_edac_isr,
11165c43cbdfSMichael Opdenacker 0,
1117dba7a77cSGrant Erickson "[EDAC] MC ECCSEC",
1118dba7a77cSGrant Erickson mci);
1119dba7a77cSGrant Erickson
1120dba7a77cSGrant Erickson if (status < 0) {
1121dba7a77cSGrant Erickson ppc4xx_edac_mc_printk(KERN_ERR, mci,
1122dba7a77cSGrant Erickson "Unable to request irq %d for ECC SEC",
1123dba7a77cSGrant Erickson sec_irq);
1124dba7a77cSGrant Erickson status = -ENODEV;
1125dba7a77cSGrant Erickson goto fail2;
1126dba7a77cSGrant Erickson }
1127dba7a77cSGrant Erickson
1128dba7a77cSGrant Erickson ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCDED irq is %d\n", ded_irq);
1129dba7a77cSGrant Erickson ppc4xx_edac_mc_printk(KERN_INFO, mci, "ECCSEC irq is %d\n", sec_irq);
1130dba7a77cSGrant Erickson
1131dba7a77cSGrant Erickson pdata->irqs.ded = ded_irq;
1132dba7a77cSGrant Erickson pdata->irqs.sec = sec_irq;
1133dba7a77cSGrant Erickson
1134dba7a77cSGrant Erickson return 0;
1135dba7a77cSGrant Erickson
1136dba7a77cSGrant Erickson fail2:
1137dba7a77cSGrant Erickson free_irq(sec_irq, mci);
1138dba7a77cSGrant Erickson
1139dba7a77cSGrant Erickson fail1:
1140dba7a77cSGrant Erickson free_irq(ded_irq, mci);
1141dba7a77cSGrant Erickson
1142dba7a77cSGrant Erickson fail:
1143dba7a77cSGrant Erickson return status;
1144dba7a77cSGrant Erickson }
1145dba7a77cSGrant Erickson
1146dba7a77cSGrant Erickson /**
1147dba7a77cSGrant Erickson * ppc4xx_edac_map_dcrs - locate and map controller registers
1148dba7a77cSGrant Erickson * @np: A pointer to the device tree node containing the DCR
1149dba7a77cSGrant Erickson * resources to map.
1150dba7a77cSGrant Erickson * @dcr_host: A pointer to the DCR data to populate with the
1151dba7a77cSGrant Erickson * DCR mapping.
1152dba7a77cSGrant Erickson *
1153dba7a77cSGrant Erickson * This routine attempts to locate in the device tree and map the DCR
1154dba7a77cSGrant Erickson * register resources associated with the controller's indirect DCR
1155dba7a77cSGrant Erickson * address and data windows.
1156dba7a77cSGrant Erickson *
1157dba7a77cSGrant Erickson * Returns 0 if the DCRs were successfully mapped; otherwise, < 0 on
1158dba7a77cSGrant Erickson * error.
1159dba7a77cSGrant Erickson */
ppc4xx_edac_map_dcrs(const struct device_node * np,dcr_host_t * dcr_host)11609b3c6e85SGreg Kroah-Hartman static int ppc4xx_edac_map_dcrs(const struct device_node *np,
11619b3c6e85SGreg Kroah-Hartman dcr_host_t *dcr_host)
1162dba7a77cSGrant Erickson {
1163dba7a77cSGrant Erickson unsigned int dcr_base, dcr_len;
1164dba7a77cSGrant Erickson
1165dba7a77cSGrant Erickson if (np == NULL || dcr_host == NULL)
1166dba7a77cSGrant Erickson return -EINVAL;
1167dba7a77cSGrant Erickson
1168dba7a77cSGrant Erickson /* Get the DCR resource extent and sanity check the values. */
1169dba7a77cSGrant Erickson
1170dba7a77cSGrant Erickson dcr_base = dcr_resource_start(np, 0);
1171dba7a77cSGrant Erickson dcr_len = dcr_resource_len(np, 0);
1172dba7a77cSGrant Erickson
1173dba7a77cSGrant Erickson if (dcr_base == 0 || dcr_len == 0) {
1174dba7a77cSGrant Erickson ppc4xx_edac_printk(KERN_ERR,
1175dba7a77cSGrant Erickson "Failed to obtain DCR property.\n");
1176dba7a77cSGrant Erickson return -ENODEV;
1177dba7a77cSGrant Erickson }
1178dba7a77cSGrant Erickson
1179dba7a77cSGrant Erickson if (dcr_len != SDRAM_DCR_RESOURCE_LEN) {
1180dba7a77cSGrant Erickson ppc4xx_edac_printk(KERN_ERR,
1181dba7a77cSGrant Erickson "Unexpected DCR length %d, expected %d.\n",
1182dba7a77cSGrant Erickson dcr_len, SDRAM_DCR_RESOURCE_LEN);
1183dba7a77cSGrant Erickson return -ENODEV;
1184dba7a77cSGrant Erickson }
1185dba7a77cSGrant Erickson
1186dba7a77cSGrant Erickson /* Attempt to map the DCR extent. */
1187dba7a77cSGrant Erickson
1188dba7a77cSGrant Erickson *dcr_host = dcr_map(np, dcr_base, dcr_len);
1189dba7a77cSGrant Erickson
1190dba7a77cSGrant Erickson if (!DCR_MAP_OK(*dcr_host)) {
1191dba7a77cSGrant Erickson ppc4xx_edac_printk(KERN_INFO, "Failed to map DCRs.\n");
1192dba7a77cSGrant Erickson return -ENODEV;
1193dba7a77cSGrant Erickson }
1194dba7a77cSGrant Erickson
1195dba7a77cSGrant Erickson return 0;
1196dba7a77cSGrant Erickson }
1197dba7a77cSGrant Erickson
1198dba7a77cSGrant Erickson /**
1199dba7a77cSGrant Erickson * ppc4xx_edac_probe - check controller and bind driver
1200dba7a77cSGrant Erickson * @op: A pointer to the OpenFirmware device tree node associated
1201dba7a77cSGrant Erickson * with the controller being probed for driver binding.
1202dba7a77cSGrant Erickson *
1203dba7a77cSGrant Erickson * This routine probes a specific ibm,sdram-4xx-ddr2 controller
1204dba7a77cSGrant Erickson * instance for binding with the driver.
1205dba7a77cSGrant Erickson *
1206dba7a77cSGrant Erickson * Returns 0 if the controller instance was successfully bound to the
1207dba7a77cSGrant Erickson * driver; otherwise, < 0 on error.
1208dba7a77cSGrant Erickson */
ppc4xx_edac_probe(struct platform_device * op)12099b3c6e85SGreg Kroah-Hartman static int ppc4xx_edac_probe(struct platform_device *op)
1210dba7a77cSGrant Erickson {
1211dba7a77cSGrant Erickson int status = 0;
1212dba7a77cSGrant Erickson u32 mcopt1, memcheck;
1213dba7a77cSGrant Erickson dcr_host_t dcr_host;
1214a26f95feSAnatolij Gustschin const struct device_node *np = op->dev.of_node;
1215dba7a77cSGrant Erickson struct mem_ctl_info *mci = NULL;
121694d93374SMauro Carvalho Chehab struct edac_mc_layer layers[2];
1217dba7a77cSGrant Erickson static int ppc4xx_edac_instance;
1218dba7a77cSGrant Erickson
1219dba7a77cSGrant Erickson /*
1220dba7a77cSGrant Erickson * At this point, we only support the controller realized on
1221dba7a77cSGrant Erickson * the AMCC PPC 405EX[r]. Reject anything else.
1222dba7a77cSGrant Erickson */
1223dba7a77cSGrant Erickson
1224dba7a77cSGrant Erickson if (!of_device_is_compatible(np, "ibm,sdram-405ex") &&
1225dba7a77cSGrant Erickson !of_device_is_compatible(np, "ibm,sdram-405exr")) {
1226dba7a77cSGrant Erickson ppc4xx_edac_printk(KERN_NOTICE,
1227dba7a77cSGrant Erickson "Only the PPC405EX[r] is supported.\n");
1228dba7a77cSGrant Erickson return -ENODEV;
1229dba7a77cSGrant Erickson }
1230dba7a77cSGrant Erickson
1231dba7a77cSGrant Erickson /*
1232dba7a77cSGrant Erickson * Next, get the DCR property and attempt to map it so that we
1233dba7a77cSGrant Erickson * can probe the controller.
1234dba7a77cSGrant Erickson */
1235dba7a77cSGrant Erickson
1236dba7a77cSGrant Erickson status = ppc4xx_edac_map_dcrs(np, &dcr_host);
1237dba7a77cSGrant Erickson
1238dba7a77cSGrant Erickson if (status)
1239dba7a77cSGrant Erickson return status;
1240dba7a77cSGrant Erickson
1241dba7a77cSGrant Erickson /*
1242dba7a77cSGrant Erickson * First determine whether ECC is enabled at all. If not,
1243dba7a77cSGrant Erickson * there is no useful checking or monitoring that can be done
1244dba7a77cSGrant Erickson * for this controller.
1245dba7a77cSGrant Erickson */
1246dba7a77cSGrant Erickson
1247dba7a77cSGrant Erickson mcopt1 = mfsdram(&dcr_host, SDRAM_MCOPT1);
1248dba7a77cSGrant Erickson memcheck = (mcopt1 & SDRAM_MCOPT1_MCHK_MASK);
1249dba7a77cSGrant Erickson
1250dba7a77cSGrant Erickson if (memcheck == SDRAM_MCOPT1_MCHK_NON) {
12512efdda4aSRob Herring ppc4xx_edac_printk(KERN_INFO, "%pOF: No ECC memory detected or "
12522efdda4aSRob Herring "ECC is disabled.\n", np);
1253dba7a77cSGrant Erickson status = -ENODEV;
1254dba7a77cSGrant Erickson goto done;
1255dba7a77cSGrant Erickson }
1256dba7a77cSGrant Erickson
1257dba7a77cSGrant Erickson /*
1258dba7a77cSGrant Erickson * At this point, we know ECC is enabled, allocate an EDAC
1259dba7a77cSGrant Erickson * controller instance and perform the appropriate
1260dba7a77cSGrant Erickson * initialization.
1261dba7a77cSGrant Erickson */
126294d93374SMauro Carvalho Chehab layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
126394d93374SMauro Carvalho Chehab layers[0].size = ppc4xx_edac_nr_csrows;
126494d93374SMauro Carvalho Chehab layers[0].is_virt_csrow = true;
126594d93374SMauro Carvalho Chehab layers[1].type = EDAC_MC_LAYER_CHANNEL;
126694d93374SMauro Carvalho Chehab layers[1].size = ppc4xx_edac_nr_chans;
126794d93374SMauro Carvalho Chehab layers[1].is_virt_csrow = false;
1268ca0907b9SMauro Carvalho Chehab mci = edac_mc_alloc(ppc4xx_edac_instance, ARRAY_SIZE(layers), layers,
126994d93374SMauro Carvalho Chehab sizeof(struct ppc4xx_edac_pdata));
1270dba7a77cSGrant Erickson if (mci == NULL) {
12712efdda4aSRob Herring ppc4xx_edac_printk(KERN_ERR, "%pOF: "
1272dba7a77cSGrant Erickson "Failed to allocate EDAC MC instance!\n",
12732efdda4aSRob Herring np);
1274dba7a77cSGrant Erickson status = -ENOMEM;
1275dba7a77cSGrant Erickson goto done;
1276dba7a77cSGrant Erickson }
1277dba7a77cSGrant Erickson
127800006124SGrant Likely status = ppc4xx_edac_mc_init(mci, op, &dcr_host, mcopt1);
1279dba7a77cSGrant Erickson
1280dba7a77cSGrant Erickson if (status) {
1281dba7a77cSGrant Erickson ppc4xx_edac_mc_printk(KERN_ERR, mci,
1282dba7a77cSGrant Erickson "Failed to initialize instance!\n");
1283dba7a77cSGrant Erickson goto fail;
1284dba7a77cSGrant Erickson }
1285dba7a77cSGrant Erickson
1286dba7a77cSGrant Erickson /*
1287dba7a77cSGrant Erickson * We have a valid, initialized EDAC instance bound to the
1288dba7a77cSGrant Erickson * controller. Attempt to register it with the EDAC subsystem
1289dba7a77cSGrant Erickson * and, if necessary, register interrupts.
1290dba7a77cSGrant Erickson */
1291dba7a77cSGrant Erickson
1292dba7a77cSGrant Erickson if (edac_mc_add_mc(mci)) {
1293dba7a77cSGrant Erickson ppc4xx_edac_mc_printk(KERN_ERR, mci,
1294dba7a77cSGrant Erickson "Failed to add instance!\n");
1295dba7a77cSGrant Erickson status = -ENODEV;
1296dba7a77cSGrant Erickson goto fail;
1297dba7a77cSGrant Erickson }
1298dba7a77cSGrant Erickson
1299dba7a77cSGrant Erickson if (edac_op_state == EDAC_OPSTATE_INT) {
1300dba7a77cSGrant Erickson status = ppc4xx_edac_register_irq(op, mci);
1301dba7a77cSGrant Erickson
1302dba7a77cSGrant Erickson if (status)
1303dba7a77cSGrant Erickson goto fail1;
1304dba7a77cSGrant Erickson }
1305dba7a77cSGrant Erickson
1306dba7a77cSGrant Erickson ppc4xx_edac_instance++;
1307dba7a77cSGrant Erickson
1308dba7a77cSGrant Erickson return 0;
1309dba7a77cSGrant Erickson
1310dba7a77cSGrant Erickson fail1:
1311fd687502SMauro Carvalho Chehab edac_mc_del_mc(mci->pdev);
1312dba7a77cSGrant Erickson
1313dba7a77cSGrant Erickson fail:
1314dba7a77cSGrant Erickson edac_mc_free(mci);
1315dba7a77cSGrant Erickson
1316dba7a77cSGrant Erickson done:
1317dba7a77cSGrant Erickson return status;
1318dba7a77cSGrant Erickson }
1319dba7a77cSGrant Erickson
1320dba7a77cSGrant Erickson /**
1321dba7a77cSGrant Erickson * ppc4xx_edac_remove - unbind driver from controller
1322dba7a77cSGrant Erickson * @op: A pointer to the OpenFirmware device tree node associated
1323dba7a77cSGrant Erickson * with the controller this EDAC instance is to be unbound/removed
1324dba7a77cSGrant Erickson * from.
1325dba7a77cSGrant Erickson *
1326dba7a77cSGrant Erickson * This routine unbinds the EDAC memory controller instance associated
1327dba7a77cSGrant Erickson * with the specified ibm,sdram-4xx-ddr2 controller described by the
1328dba7a77cSGrant Erickson * OpenFirmware device tree node passed as a parameter.
1329dba7a77cSGrant Erickson *
1330dba7a77cSGrant Erickson * Unconditionally returns 0.
1331dba7a77cSGrant Erickson */
1332dba7a77cSGrant Erickson static int
ppc4xx_edac_remove(struct platform_device * op)13332dc11581SGrant Likely ppc4xx_edac_remove(struct platform_device *op)
1334dba7a77cSGrant Erickson {
1335dba7a77cSGrant Erickson struct mem_ctl_info *mci = dev_get_drvdata(&op->dev);
1336dba7a77cSGrant Erickson struct ppc4xx_edac_pdata *pdata = mci->pvt_info;
1337dba7a77cSGrant Erickson
1338dba7a77cSGrant Erickson if (edac_op_state == EDAC_OPSTATE_INT) {
1339dba7a77cSGrant Erickson free_irq(pdata->irqs.sec, mci);
1340dba7a77cSGrant Erickson free_irq(pdata->irqs.ded, mci);
1341dba7a77cSGrant Erickson }
1342dba7a77cSGrant Erickson
1343dba7a77cSGrant Erickson dcr_unmap(pdata->dcr_host, SDRAM_DCR_RESOURCE_LEN);
1344dba7a77cSGrant Erickson
1345fd687502SMauro Carvalho Chehab edac_mc_del_mc(mci->pdev);
1346dba7a77cSGrant Erickson edac_mc_free(mci);
1347dba7a77cSGrant Erickson
1348dba7a77cSGrant Erickson return 0;
1349dba7a77cSGrant Erickson }
1350dba7a77cSGrant Erickson
1351dba7a77cSGrant Erickson /**
1352dba7a77cSGrant Erickson * ppc4xx_edac_opstate_init - initialize EDAC reporting method
1353dba7a77cSGrant Erickson *
1354dba7a77cSGrant Erickson * This routine ensures that the EDAC memory controller reporting
1355dba7a77cSGrant Erickson * method is mapped to a sane value as the EDAC core defines the value
1356dba7a77cSGrant Erickson * to EDAC_OPSTATE_INVAL by default. We don't call the global
1357dba7a77cSGrant Erickson * opstate_init as that defaults to polling and we want interrupt as
1358dba7a77cSGrant Erickson * the default.
1359dba7a77cSGrant Erickson */
1360dba7a77cSGrant Erickson static inline void __init
ppc4xx_edac_opstate_init(void)1361dba7a77cSGrant Erickson ppc4xx_edac_opstate_init(void)
1362dba7a77cSGrant Erickson {
1363dba7a77cSGrant Erickson switch (edac_op_state) {
1364dba7a77cSGrant Erickson case EDAC_OPSTATE_POLL:
1365dba7a77cSGrant Erickson case EDAC_OPSTATE_INT:
1366dba7a77cSGrant Erickson break;
1367dba7a77cSGrant Erickson default:
1368dba7a77cSGrant Erickson edac_op_state = EDAC_OPSTATE_INT;
1369dba7a77cSGrant Erickson break;
1370dba7a77cSGrant Erickson }
1371dba7a77cSGrant Erickson
1372dba7a77cSGrant Erickson ppc4xx_edac_printk(KERN_INFO, "Reporting type: %s\n",
1373dba7a77cSGrant Erickson ((edac_op_state == EDAC_OPSTATE_POLL) ?
1374dba7a77cSGrant Erickson EDAC_OPSTATE_POLL_STR :
1375dba7a77cSGrant Erickson ((edac_op_state == EDAC_OPSTATE_INT) ?
1376dba7a77cSGrant Erickson EDAC_OPSTATE_INT_STR :
1377dba7a77cSGrant Erickson EDAC_OPSTATE_UNKNOWN_STR)));
1378dba7a77cSGrant Erickson }
1379dba7a77cSGrant Erickson
1380*d5e4eeeaSUwe Kleine-König static struct platform_driver ppc4xx_edac_driver = {
1381*d5e4eeeaSUwe Kleine-König .probe = ppc4xx_edac_probe,
1382*d5e4eeeaSUwe Kleine-König .remove = ppc4xx_edac_remove,
1383*d5e4eeeaSUwe Kleine-König .driver = {
1384*d5e4eeeaSUwe Kleine-König .name = PPC4XX_EDAC_MODULE_NAME,
1385*d5e4eeeaSUwe Kleine-König .of_match_table = ppc4xx_edac_match,
1386*d5e4eeeaSUwe Kleine-König },
1387*d5e4eeeaSUwe Kleine-König };
1388*d5e4eeeaSUwe Kleine-König
1389dba7a77cSGrant Erickson /**
1390dba7a77cSGrant Erickson * ppc4xx_edac_init - driver/module insertion entry point
1391dba7a77cSGrant Erickson *
1392dba7a77cSGrant Erickson * This routine is the driver/module insertion entry point. It
1393dba7a77cSGrant Erickson * initializes the EDAC memory controller reporting state and
1394dba7a77cSGrant Erickson * registers the driver as an OpenFirmware device tree platform
1395dba7a77cSGrant Erickson * driver.
1396dba7a77cSGrant Erickson */
1397dba7a77cSGrant Erickson static int __init
ppc4xx_edac_init(void)1398dba7a77cSGrant Erickson ppc4xx_edac_init(void)
1399dba7a77cSGrant Erickson {
1400dba7a77cSGrant Erickson ppc4xx_edac_printk(KERN_INFO, PPC4XX_EDAC_MODULE_REVISION "\n");
1401dba7a77cSGrant Erickson
1402dba7a77cSGrant Erickson ppc4xx_edac_opstate_init();
1403dba7a77cSGrant Erickson
140400006124SGrant Likely return platform_driver_register(&ppc4xx_edac_driver);
1405dba7a77cSGrant Erickson }
1406dba7a77cSGrant Erickson
1407dba7a77cSGrant Erickson /**
1408dba7a77cSGrant Erickson * ppc4xx_edac_exit - driver/module removal entry point
1409dba7a77cSGrant Erickson *
1410dba7a77cSGrant Erickson * This routine is the driver/module removal entry point. It
1411dba7a77cSGrant Erickson * unregisters the driver as an OpenFirmware device tree platform
1412dba7a77cSGrant Erickson * driver.
1413dba7a77cSGrant Erickson */
1414dba7a77cSGrant Erickson static void __exit
ppc4xx_edac_exit(void)1415dba7a77cSGrant Erickson ppc4xx_edac_exit(void)
1416dba7a77cSGrant Erickson {
141700006124SGrant Likely platform_driver_unregister(&ppc4xx_edac_driver);
1418dba7a77cSGrant Erickson }
1419dba7a77cSGrant Erickson
1420dba7a77cSGrant Erickson module_init(ppc4xx_edac_init);
1421dba7a77cSGrant Erickson module_exit(ppc4xx_edac_exit);
1422dba7a77cSGrant Erickson
1423dba7a77cSGrant Erickson MODULE_LICENSE("GPL v2");
1424dba7a77cSGrant Erickson MODULE_AUTHOR("Grant Erickson <gerickson@nuovations.com>");
1425dba7a77cSGrant Erickson MODULE_DESCRIPTION("EDAC MC Driver for the PPC4xx IBM DDR2 Memory Controller");
1426dba7a77cSGrant Erickson module_param(edac_op_state, int, 0444);
1427dba7a77cSGrant Erickson MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting State: "
1428dba7a77cSGrant Erickson "0=" EDAC_OPSTATE_POLL_STR ", 2=" EDAC_OPSTATE_INT_STR);
1429