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/openbmc/qemu/target/rx/
H A Dtranslate.c21 #include "qemu/qemu-print.h"
23 #include "tcg/tcg-op.h"
24 #include "exec/helper-proto.h"
25 #include "exec/helper-gen.h"
27 #include "exec/translation-block.h"
31 #include "exec/helper-info.c.inc"
36 DisasContextBase base; member
60 /* Target-specific values for dc->base.is_jmp. */
80 uint8_t b = translator_ldub(ctx->env, &ctx->base, ctx->base.pc_next++); in decode_load_bytes()
81 insn |= b << (32 - i * 8); in decode_load_bytes()
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/openbmc/qemu/hw/pci-host/
H A Ddesignware.c29 #include "hw/qdev-properties.h"
32 #include "hw/pci-host/designware.h"
67 k->max_dev = 1; in designware_pcie_root_bus_class_init()
74 return DESIGNWARE_PCIE_HOST(bus->parent); in designware_pcie_root_to_host()
85 * AHB/AXI bus like any other PCI-device-initiated DMA read. in designware_pcie_root_msi_read()
87 * well-behaved guests won't ever ask a PCI device to DMA from in designware_pcie_root_msi_read()
100 root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; in designware_pcie_root_msi_write()
102 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { in designware_pcie_root_msi_write()
103 qemu_set_irq(host->pci.msi, 1); in designware_pcie_root_msi_write()
120 MemoryRegion *mem = &root->msi.iomem; in designware_pcie_root_update_msi_mapping() local
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/openbmc/u-boot/drivers/core/
H A Dof_extra.c1 // SPDX-License-Identifier: GPL-2.0+
17 if (ofnode_read_u32(node, "image-pos", &entry->offset)) { in ofnode_read_fmap_entry()
18 debug("Node '%s' has bad/missing 'image-pos' property\n", in ofnode_read_fmap_entry()
20 return log_ret(-ENOENT); in ofnode_read_fmap_entry()
22 if (ofnode_read_u32(node, "size", &entry->length)) { in ofnode_read_fmap_entry()
25 return log_ret(-ENOENT); in ofnode_read_fmap_entry()
27 entry->used = ofnode_read_s32_default(node, "used", entry->length); in ofnode_read_fmap_entry()
31 entry->compress_algo = FMAP_COMPRESS_LZ4; in ofnode_read_fmap_entry()
34 -EINVAL); in ofnode_read_fmap_entry()
36 entry->compress_algo = FMAP_COMPRESS_NONE; in ofnode_read_fmap_entry()
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/openbmc/qemu/hw/usb/
H A Dlibhw.c28 DMADirection dir = (p->pid == USB_TOKEN_IN) ? in usb_packet_map()
30 void *mem; in usb_packet_map() local
33 for (i = 0; i < sgl->nsg; i++) { in usb_packet_map()
34 dma_addr_t base = sgl->sg[i].base; in usb_packet_map() local
35 dma_addr_t len = sgl->sg[i].len; in usb_packet_map()
39 mem = dma_memory_map(sgl->as, base, &xlen, dir, in usb_packet_map()
41 if (!mem) { in usb_packet_map()
47 qemu_iovec_add(&p->iov, mem, xlen); in usb_packet_map()
48 len -= xlen; in usb_packet_map()
49 base += xlen; in usb_packet_map()
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/openbmc/u-boot/post/drivers/
H A Dmemory.c1 // SPDX-License-Identifier: GPL-2.0+
18 * o For the address line test, it is a good idea to use the base
44 * ---------------
77 * ------------------
85 * To test all address lines, we start with the given base address and
94 * Example for a 4 bit address space with the base at 0000:
95 * 0000 <- base
96 * 0001 <- test 1
97 * 0010 <- test 2
98 * 0100 <- test 3
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/openbmc/u-boot/drivers/pci/
H A Dpci_mvebu.c1 // SPDX-License-Identifier: GPL-2.0
5 * Based on Barebox drivers/pci/pci-mvebu.c
7 * Ported to U-Boot by:
14 #include <dm/device-internal.h>
38 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
69 void __iomem *base; member
71 struct resource mem; member
85 * into SoCs address space. Each controller will map 128M of MEM
94 val = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_link_up()
102 stat = readl(pcie->base + PCIE_STAT_OFF); in mvebu_pcie_set_local_bus_nr()
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H A Dpcie_dw_mvebu.c1 // SPDX-License-Identifier: GPL-2.0+
8 * - drivers/pci/pcie_imx.c
9 * - drivers/pci/pci_mvebu.c
10 * - drivers/pci/pcie_xilinx.c
17 #include <asm-generic/gpio.h>
97 * struct pcie_dw_mvebu - MVEBU DW PCIe controller state
99 * @ctrl_base: The base address of the register space
100 * @cfg_base: The base address of the configuration space
104 * first_busno stores the bus number of the PCIe root-port
114 /* IO and MEM PCI regions */
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/openbmc/qemu/hw/display/
H A Dframebuffer.c9 * Contributions after 2012-01-13 are licensed under the terms of the
14 - Do something similar for framebuffers with local ram
15 - Handle rotation here instead of hacking dest_pitch
16 - Use common pixel conversion routines instead of per-device drawfn
17 - Remove all DisplayState knowledge from devices.
27 hwaddr base, in framebuffer_update_memory_section() argument
33 if (mem_section->mr) { in framebuffer_update_memory_section()
34 memory_region_set_log(mem_section->mr, false, DIRTY_MEMORY_VGA); in framebuffer_update_memory_section()
35 memory_region_unref(mem_section->mr); in framebuffer_update_memory_section()
36 mem_section->mr = NULL; in framebuffer_update_memory_section()
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/openbmc/qemu/hw/virtio/
H A Dvirtio-mem-pci.h2 * Virtio MEM PCI device
10 * See the COPYING file in the top-level directory.
16 #include "hw/virtio/virtio-md-pci.h"
17 #include "hw/virtio/virtio-mem.h"
23 * virtio-mem-pci: This extends VirtIOMDPCI.
25 #define TYPE_VIRTIO_MEM_PCI "virtio-mem-pci-base"
/openbmc/u-boot/drivers/usb/dwc3/
H A Dio.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * io.h - DesignWare USB3 DRD IO Header
5 * Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
10 * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/io.h) and ported
23 static inline u32 dwc3_readl(void __iomem *base, u32 offset) in dwc3_readl() argument
25 unsigned long offs = offset - DWC3_GLOBALS_REGS_START; in dwc3_readl()
29 * We requested the mem region starting from the Globals address in dwc3_readl()
33 value = readl(base + offs); in dwc3_readl()
38 static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value) in dwc3_writel() argument
40 unsigned long offs = offset - DWC3_GLOBALS_REGS_START; in dwc3_writel()
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/openbmc/qemu/hw/vmapple/
H A Dvmapple.c7 * See the COPYING file in the top-level directory.
9 * SPDX-License-Identifier: GPL-2.0-or-later
11 * VMApple is the device model that the macOS built-in hypervisor called
20 #include "qemu/error-report.h"
21 #include "qemu/guest-random.h"
22 #include "qemu/help-texts.h"
31 #include "hw/qdev-properties.h"
40 #include "hw/pci-host/gpex.h"
41 #include "hw/usb/hcd-xhci-pci.h"
42 #include "hw/virtio/virtio-pci.h"
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/openbmc/qemu/rust/qemu-api/src/
H A Dvmstate.rs3 // SPDX-License-Identifier: GPL-2.0-or-later
17 //! structs and for `bilge`-defined types)
24 //! `include/migration/vmstate.h`. These are not type-safe and only provide
27 use core::{marker::PhantomData, mem, ptr::NonNull};
45 /// const fn size_of_field<T>(_: PhantomData<T>) -> usize {
46 /// std::mem::size_of::<T>()
58 // https://users.rust-lang.org/t/inferring-type-of-field/122857
63 … const fn phantom__<T>(_: &T) -> ::core::marker::PhantomData<T> { ::core::marker::PhantomData }
137 /// provides the base contents of a `VMStateField` (minus the name and offset).
147 /// yet be included in the [`BASE`](VMState::BASE) associated constant;
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/openbmc/qemu/system/
H A Ddma-helpers.c11 #include "system/block-backend.h"
15 #include "qemu/main-loop.h"
32 qsg->sg = g_new(ScatterGatherEntry, alloc_hint); in qemu_sglist_init()
33 qsg->nsg = 0; in qemu_sglist_init()
34 qsg->nalloc = alloc_hint; in qemu_sglist_init()
35 qsg->size = 0; in qemu_sglist_init()
36 qsg->as = as; in qemu_sglist_init()
37 qsg->dev = dev; in qemu_sglist_init()
41 void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len) in qemu_sglist_add() argument
43 if (qsg->nsg == qsg->nalloc) { in qemu_sglist_add()
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/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ram.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
32 ret = clk_get_by_name(priv->dev, clkname[idx], &clk); in stm32mp1_ddr_clk_enable()
43 priv->clk = clk; in stm32mp1_ddr_clk_enable()
44 ddrphy_clk = clk_get_rate(&priv->clk); in stm32mp1_ddr_clk_enable()
49 ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000); in stm32mp1_ddr_clk_enable()
53 return -EINVAL; in stm32mp1_ddr_clk_enable()
71 #define CTL_PARAM(x) PARAM("st,ctl-"#x, c_##x) in stm32mp1_ddr_setup()
72 #define PHY_PARAM(x) PARAM("st,phy-"#x, p_##x) in stm32mp1_ddr_setup()
88 config.info.speed = dev_read_u32_default(dev, "st,mem-speed", 0); in stm32mp1_ddr_setup()
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/openbmc/u-boot/arch/arm/mach-uniphier/
H A Dmicro-support-card.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2012-2015 Panasonic Corporation
4 * Copyright (C) 2015-2016 Socionext Inc.
12 #include "micro-support-card.h"
79 phys_addr_t base; member
83 static int mem_is_flash(const struct memory_bank *mem) in mem_is_flash() argument
92 scratch_addr = map_physmem(mem->base + mem->size - sizeof(u32) * loop, in mem_is_flash()
121 return flash_banks_list[i]->base; in cfi_flash_bank_addr()
126 return flash_banks_list[i]->size; in cfi_flash_bank_size()
147 debug("flash bank found: base = 0x%lx, size = 0x%lx\n", in detect_num_flash_banks()
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/openbmc/u-boot/arch/mips/include/asm/
H A Dio.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 1994 - 2000, 06 Ralf Baechle
18 #include <asm/cpu-features.h>
19 #include <asm/pgtable-bits.h>
24 #include <mangle-port.h>
39 /* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
49 return gd->arch.io_port_base; in mips_io_port_base()
52 static inline void set_io_port_base(unsigned long base) in set_io_port_base() argument
56 gd->arch.io_port_base = base; in set_io_port_base()
67 static inline void set_io_port_base(unsigned long base) in set_io_port_base() argument
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/openbmc/u-boot/drivers/ata/
H A Dahci.c1 // SPDX-License-Identifier: GPL-2.0+
26 #include <dm/device-internal.h>
53 __weak void __iomem *ahci_port_base(void __iomem *base, u32 port) in ahci_port_base() argument
55 return base + 0x100 + (port * 0x80); in ahci_port_base()
59 static void ahci_setup_port(struct ahci_ioports *port, void __iomem *base, in ahci_setup_port() argument
62 base = ahci_port_base(base, port_idx); in ahci_setup_port()
64 port->cmd_addr = base; in ahci_setup_port()
65 port->scr_addr = base + PORT_SCR; in ahci_setup_port()
100 ahci_dcache_flush_range((unsigned long)pp->cmd_slot, in ahci_dcache_flush_sata_cmd()
114 return (i < timeout_msec) ? 0 : -1; in waiting_for_cmd_completed()
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/openbmc/u-boot/board/armltd/vexpress64/
H A Dpcie.c6 * SPDX-Licence-Identifier: GPL-2.0+
52 #define XR3PCI_ATR_TRSLID_AXIMEMORY (0x4e0004) /* Write-through, read/write allocate */
73 void xr3pci_set_atr_entry(unsigned long base, unsigned long src_addr, in xr3pci_set_atr_entry() argument
78 - bit 0: enable entry, in xr3pci_set_atr_entry()
79 - bits 1-6: ATR window size: total size in bytes: 2^(ATR_WSIZE + 1) in xr3pci_set_atr_entry()
80 - bits 7-11: reserved in xr3pci_set_atr_entry()
81 - bits 12-31: start of source address in xr3pci_set_atr_entry()
83 writel((u32)(src_addr & 0xfffff000) | (window_size - 1) << 1 | 1, in xr3pci_set_atr_entry()
84 base + XR3PCI_ATR_SRC_ADDR_LOW); in xr3pci_set_atr_entry()
85 writel((u32)(src_addr >> 32), base + XR3PCI_ATR_SRC_ADDR_HIGH); in xr3pci_set_atr_entry()
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/openbmc/hiomapd/vpnor/
H A Dbackend.cpp1 // SPDX-License-Identifier: Apache-2.0
33 #include <phosphor-logging/elog-errors.hpp>
34 #include <phosphor-logging/log.hpp>
48 strncpy(paths->ro_loc, PARTITION_FILES_RO_LOC, PATH_MAX); in vpnor_default_paths()
49 paths->ro_loc[PATH_MAX - 1] = '\0'; in vpnor_default_paths()
50 strncpy(paths->rw_loc, PARTITION_FILES_RW_LOC, PATH_MAX); in vpnor_default_paths()
51 paths->rw_loc[PATH_MAX - 1] = '\0'; in vpnor_default_paths()
52 strncpy(paths->prsv_loc, PARTITION_FILES_PRSV_LOC, PATH_MAX); in vpnor_default_paths()
53 paths->prsv_loc[PATH_MAX - 1] = '\0'; in vpnor_default_paths()
54 strncpy(paths->patch_loc, PARTITION_FILES_PATCH_LOC, PATH_MAX); in vpnor_default_paths()
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/openbmc/u-boot/include/linux/mtd/
H A Dspinand.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2016-2017 Micron Technology, Inc.
18 #include <linux/spi/spi-mem.h>
22 #include <spi-mem.h>
152 * struct spinand_id - SPI NAND id structure
157 * struct_spinand_id->data contains all bytes returned after a READ_ID command,
160 * struct_manufacurer_ops->detect().
168 * struct manufacurer_ops - SPI NAND manufacturer specific operations
170 * the core calls the struct_manufacurer_ops->detect() hook of each
173 * in struct_spinand_device->id matches the manufacturer whose
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/openbmc/qemu/disas/
H A Dalpha.c1 /* alpha-dis.c -- Disassemble Alpha AXP instructions
23 #include "disas/dis-asm.h"
65 #define AXP_OPCODE_BASE 0x0001 /* Base architecture -- all cpus. */
102 i |= (op & ((1 << o->bits) - 1)) << o->shift;
121 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
122 if ((o->flags & AXP_OPERAND_SIGNED) != 0
123 && (op & (1 << (o->bits - 1))) != 0)
124 op -= 1 << o->bits;
131 non-zero if this operand type can not actually be extracted from
182 a flags value of 0 can be treated as end-of-arguments. */
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/openbmc/qemu/hw/dma/
H A Dsoc_dma.c2 * On-chip DMA controller framework.
21 #include "qemu/error-report.h"
27 memcpy(ch->paddr[0], ch->paddr[1], ch->bytes); in transfer_mem2mem()
28 ch->paddr[0] += ch->bytes; in transfer_mem2mem()
29 ch->paddr[1] += ch->bytes; in transfer_mem2mem()
34 ch->io_fn[1](ch->io_opaque[1], ch->paddr[0], ch->bytes); in transfer_mem2fifo()
35 ch->paddr[0] += ch->bytes; in transfer_mem2fifo()
40 ch->io_fn[0](ch->io_opaque[0], ch->paddr[1], ch->bytes); in transfer_fifo2mem()
41 ch->paddr[1] += ch->bytes; in transfer_fifo2mem()
51 if (ch->bytes > fifo_size) in transfer_fifo2fifo()
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/openbmc/u-boot/include/net/pfe_eth/pfe/
H A Dpfe_hw.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2015-2016 Freescale Semiconductor, Inc.
16 /* Only valid for mem access register interface */
22 /* Only valid for mem access register interface */
66 /* DDR physical base address as seen by PE's. */
70 /* CBUS physical base address as seen by PE's. */
73 /* Host<->PFE Mapping */
75 #define CBUS_VIRT_TO_PFE(v) (((v) - CBUS_BASE_ADDR) +\
77 #define CBUS_PFE_TO_VIRT(p) (((p) - PFE_CBUS_PHYS_BASE_ADDR) +\
114 u32 dmem_base_addr; /* PE's dmem base address */
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/openbmc/u-boot/arch/arm/mach-orion5x/
H A Dlowlevel_init.S1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
23 /* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
36 * For Guideline MEM-3 - Drive Strength value
43 * For Guideline MEM-4 - DQS Reference Delay Tuning
62 * Low-level init happens right after start.S has switched to SVC32,
65 * set up the RAM to copy U-Boot into.
74 /* Use 'r2 as the base for internal register accesses */
83 /* Use R3 as the base for DRAM registers */
90 /* Use R3 as the base for PCI registers */
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/openbmc/u-boot/include/configs/
H A Dsmdkc100.h1 /* SPDX-License-Identifier: GPL-2.0+ */
29 /* DRAM Base */
32 /* Text Base */
58 " mem=128M"
61 " mem=128M " \
74 "onenand erase block 147-4095;" \
104 "meminfo=mem=128M\0" \
119 /* SMDKC100 has 1 banks of DRAM, we use only one in U-Boot */
125 /*-----------------------------------------------------------------------
141 /*-----------------------------------------------------------------------
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