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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmdio-mux-multiplexer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer consumer device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of MDIO mux when MDIO mux is defined as a consumer
14 of a mux producer device. The mux producer can be of any type like mmio mux
15 producer, gpio mux producer or generic register based mux producer.
19 - $ref: /schemas/net/mdio-mux.yaml#
[all …]
H A Dmdio-mux-mmioreg.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
[all …]
H A Dallwinner,sun8i-a83t-emac.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/allwinner,sun8i-a83t-emac.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
16 - const: allwinner,sun8i-a83t-emac
17 - const: allwinner,sun8i-h3-emac
18 - const: allwinner,sun8i-r40-gmac
19 - const: allwinner,sun8i-v3s-emac
[all …]
H A Dbrcm,mdio-mux-iproc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/brcm,mdio-mux-iproc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO bus multiplexer found in Broadcom iProc based SoCs.
10 - Florian Fainelli <f.fainelli@gmail.com>
13 This MDIO bus multiplexer defines buses that could be internal as well as
14 external to SoCs and could accept MDIO transaction compatible to C-22 or
15 C-45 Clause. When child bus is selected, one needs to select these two
16 properties as well to generate desired MDIO transaction on appropriate bus.
[all …]
H A Damlogic,gxl-mdio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/amlogic,gxl-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Amlogic GXL MDIO bus multiplexer
10 - Jerome Brunet <jbrunet@baylibre.com>
13 This is a special case of a MDIO bus multiplexer. It allows to choose between
14 the internal mdio bus leading to the embedded 10/100 PHY or the external
15 MDIO bus on the Amlogic GXL SoC family.
18 - $ref: mdio-mux.yaml#
[all …]
H A Dbrcm,bcm6368-mdio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/brcm,bcm6368-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM6368 MDIO bus multiplexer
10 - Álvaro Fernández Rojas <noltari@gmail.com>
13 This MDIO bus multiplexer defines buses that could be internal as well as
15 properties as well to generate desired MDIO transaction on appropriate bus.
18 - $ref: mdio-mux.yaml#
22 const: brcm,bcm6368-mdio-mux
[all …]
H A Dmdio-mux-gpio.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-gpio.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. One or more GPIO
17 - $ref: /schemas/net/mdio-mux.yaml#
21 const: mdio-mux-gpio
30 - compatible
[all …]
H A Damlogic,g12a-mdio-mux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/net/amlogic,g12a-mdio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MDIO bus multiplexer/glue of Amlogic G12a SoC family
10 This is a special case of a MDIO bus multiplexer. It allows to choose between
11 the internal mdio bus leading to the embedded 10/100 PHY or the external
12 MDIO bus.
15 - Neil Armstrong <neil.armstrong@linaro.org>
18 - $ref: mdio-mux.yaml#
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mux/
H A Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
27 mux-reg-masks:
[all …]
/openbmc/linux/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2160a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "MC34717-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
H A Dfsl-lx2162a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
9 #include "fsl-lx2160a.dtsi"
13 compatible = "fsl,lx2162a-qds", "fsl,lx2160a";
23 stdout-path = "serial0:115200n8";
26 sb_3v3: regulator-sb3v3 {
27 compatible = "regulator-fixed";
28 regulator-name = "LTM4619-3.3VSB";
29 regulator-min-microvolt = <3300000>;
30 regulator-max-microvolt = <3300000>;
[all …]
H A Dfsl-ls208xa-qds.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
14 phy-handle = <&mdio0_phy12>;
15 phy-connection-type = "sgmii";
19 phy-handle = <&mdio0_phy13>;
20 phy-connection-type = "sgmii";
24 phy-handle = <&mdio0_phy14>;
25 phy-connection-type = "sgmii";
29 phy-handle = <&mdio0_phy15>;
30 phy-connection-type = "sgmii";
34 mmc-hs200-1_8v;
[all …]
H A Dfsl-ls1028a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
11 /dts-v1/;
13 #include "fsl-ls1028a.dtsi"
17 compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
32 stdout-path = "serial0:115200n8";
40 sys_mclk: clock-mclk {
41 compatible = "fixed-clock";
42 #clock-cells = <0>;
43 clock-frequency = <25000000>;
46 reg_1p8v: regulator-1p8v {
[all …]
H A Dfsl-ls1043a-qds.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
5 * Copyright 2014-2015 Freescale Semiconductor, Inc.
6 * Copyright 2018-2021 NXP
11 /dts-v1/;
12 #include "fsl-ls1043a.dtsi"
16 compatible = "fsl,ls1043a-qds", "fsl,ls1043a";
27 sgmii-riser-s1-p1 = &sgmii_phy_s1_p1;
28 sgmii-riser-s2-p1 = &sgmii_phy_s2_p1;
29 sgmii-riser-s3-p1 = &sgmii_phy_s3_p1;
[all …]
/openbmc/u-boot/board/freescale/corenet_ds/
H A Deth_hydra.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
10 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
11 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
30 * 1) The status of each virtual MDIO node that is referenced by an Ethernet
33 * 2) The phy-handle property of each active Ethernet MAC node is set to the
36 * 3) The "mux value" for each virtual MDIO node is set to the correct value,
37 * if necessary. Some virtual MDIO nodes do not have configurable mux
38 * values, so those values are hard-coded in the DTS. On the HYDRA board,
39 * the virtual MDIO node for the SGMII card needs to be updated.
[all …]
H A Deth_superhydra.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2011 Freescale Semiconductor, Inc.
10 * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are
11 * provided by the standard Freescale four-port SGMII riser card. The 10Gb
12 * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans
30 * 1) The status of each virtual MDIO node that is referenced by an Ethernet
33 * 2) The phy-handle property of each active Ethernet MAC node is set to the
36 * 3) The "mux value" for each virtual MDIO node is set to the correct value,
37 * if necessary. Some virtual MDIO nodes do not have configurable mux
38 * values, so those values are hard-coded in the DTS. On the HYDRA board,
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dlantiq,pinctrl-xway.txt4 - compatible: "lantiq,<chip>-pinctrl", where <chip> is:
10 - reg: Should contain the physical address and length of the gpio/pinmux
13 Please refer to pinctrl-bindings.txt in this directory for details of the
20 mux function to select on those group(s), and two pin configuration parameters:
21 pull-up and open-drain
27 other words, a subnode that lists a mux function but no pin configuration
30 information about e.g. the mux function.
32 We support 2 types of nodes.
34 Definition of mux function groups:
36 Required subnode-properties:
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dmeson-gxl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
19 compatible = "amlogic,meson-gxl-dwc3";
20 #address-cells = <2>;
21 #size-cells = <2>;
[all …]
H A Dls1021a-qds.dtsi1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright 2013-2015 Freescale Semiconductor, Inc.
14 enet0-rgmii-phy = &rgmii_phy1;
15 enet1-rgmii-phy = &rgmii_phy2;
16 enet2-rgmii-phy = &rgmii_phy3;
17 enet0-sgmii-phy = &sgmii_phy1c;
18 enet1-sgmii-phy = &sgmii_phy1d;
25 bus-num = <0>;
29 #address-cells = <1>;
30 #size-cells = <1>;
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp5040ds.dts4 * Copyright 2012 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
35 /include/ "p5040si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
74 reserved-memory {
75 #address-cells = <2>;
76 #size-cells = <2>;
79 bman_fbpr: bman-fbpr {
[all …]
H A Dt2080qds.dts4 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
35 /include/ "t208xsi-pre.dtsi"
41 #address-cells = <2>;
42 #size-cells = <2>;
43 interrupt-parent = <&mpic>;
66 phy-handle = <&phy_sgmii_s3_1e>;
67 phy-connection-type = "xgmii";
71 phy-handle = <&phy_sgmii_s3_1f>;
72 phy-connection-type = "xgmii";
[all …]
H A Dp4080ds.dts4 * Copyright 2009 - 2015 Freescale Semiconductor Inc.
20 * Foundation, either version 2 of that License or (at your option) any
35 /include/ "p4080si-pre.dtsi"
40 #address-cells = <2>;
41 #size-cells = <2>;
42 interrupt-parent = <&mpic>;
62 reserved-memory {
63 #address-cells = <2>;
64 #size-cells = <2>;
67 bman_fbpr: bman-fbpr {
[all …]
/openbmc/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,pruss.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 TI Programmable Real-Time Unit and Industrial Communication Subsystem
11 - Suman Anna <s-anna@ti.com>
15 The Programmable Real-Time Unit and Industrial Communication Subsystem
16 (PRU-ICSS a.k.a. PRUSS) is present on various TI SoCs such as AM335x, AM437x,
17 Keystone 66AK2G, OMAP-L138/DA850 etc. A PRUSS consists of dual 32-bit RISC
18 cores (Programmable Real-Time Units, or PRUs), shared RAM, data and
23 peripheral interfaces, fast real-time responses, or specialized data handling.
[all …]
/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm5301x.dtsi9 #include "bcm-ns.dtsi"
12 mpcore-bus@19000000 {
14 #clock-cells = <0>;
15 compatible = "brcm,nsp-armpll";
21 compatible = "arm,cortex-a9-twd-wdt";
23 interrupts = <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
30 compatible = "arm,cortex-a9-pmu";
37 #address-cells = <1>;
38 #size-cells = <1>;
42 #clock-cells = <0>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxl.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include "meson-gx.dtsi"
8 #include <dt-bindings/clock/gxbb-clkc.h>
9 #include <dt-bindings/clock/gxbb-aoclkc.h>
10 #include <dt-bindings/gpio/meson-gxl-gpio.h>
11 #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
14 compatible = "amlogic,meson-gxl";
18 compatible = "amlogic,meson-gxl-usb-ctrl";
21 #address-cells = <2>;
22 #size-cells = <2>;
[all …]

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