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/openbmc/linux/drivers/cpufreq/
H A Dfreq_table.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2002 - 2003 Dominik Brodowski
14 * FREQUENCY TABLE HELPERS *
19 struct cpufreq_frequency_table *pos, *table = policy->freq_table; in policy_has_boost_freq()
25 if (pos->flags & CPUFREQ_BOOST_FREQ) in policy_has_boost_freq()
41 freq = pos->frequency; in cpufreq_frequency_table_cpuinfo()
43 if ((!cpufreq_boost_enabled() || !policy->boost_enabled) in cpufreq_frequency_table_cpuinfo()
44 && (pos->flags & CPUFREQ_BOOST_FREQ)) in cpufreq_frequency_table_cpuinfo()
47 pr_debug("table entry %u: %u kHz\n", (int)(pos - table), freq); in cpufreq_frequency_table_cpuinfo()
54 policy->min = policy->cpuinfo.min_freq = min_freq; in cpufreq_frequency_table_cpuinfo()
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/openbmc/linux/Documentation/admin-guide/pm/
H A Dintel-speed-select.rst1 .. SPDX-License-Identifier: GPL-2.0
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
38 # cd tools/power/x86/intel-speed-select/
43 ------------
47 # intel-speed-select --help
49 The top-level help describes arguments and features. Notice that there is a
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/openbmc/u-boot/arch/arm/dts/
H A Dast2600-bletchley.dts1 // SPDX-License-Identifier: GPL-2.0+
3 /dts-v1/;
5 #include "ast2600-u-boot.dtsi"
9 compatible = "facebook,bletchley-bmc", "aspeed,ast2600";
17 stdout-path = &uart5;
35 clock-frequency = <800000000>;
38 clock-frequency = <800000000>;
44 u-boot,dm-pre-reloc;
49 clock-frequency = <400000000>;
66 pinctrl-names = "default";
[all …]
H A Dtegra30-apalis.dts1 /dts-v1/;
10 stdout-path = &uarta;
35 pcie-controller@00003000 {
37 avdd-pexa-supply = <&vdd2_reg>;
38 vdd-pexa-supply = <&vdd2_reg>;
39 avdd-pexb-supply = <&vdd2_reg>;
40 vdd-pexb-supply = <&vdd2_reg>;
41 avdd-pex-pll-supply = <&vdd2_reg>;
42 avdd-plle-supply = <&ldo6_reg>;
43 vddio-pex-ctl-supply = <&sys_3v3_reg>;
[all …]
H A Dast2600-slt.dts1 /dts-v1/;
3 #include "ast2600-u-boot.dtsi"
12 stdout-path = &uart5;
30 clock-frequency = <800000000>;
33 clock-frequency = <800000000>;
39 u-boot,dm-pre-reloc;
44 clock-frequency = <400000000>;
48 u-boot,dm-pre-reloc;
53 u-boot,dm-pre-reloc;
58 u-boot,dm-pre-reloc;
[all …]
H A Dast2600-pfr.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /dts-v1/;
4 #include "ast2600-u-boot.dtsi"
8 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
16 stdout-path = &uart5;
34 clock-frequency = <800000000>;
37 clock-frequency = <800000000>;
43 u-boot,dm-pre-reloc;
48 clock-frequency = <400000000>;
65 pinctrl-names = "default";
[all …]
H A Dast2600-intel.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "ast2600-u-boot.dtsi"
8 compatible = "aspeed,ast2600-intel", "aspeed,ast2600";
16 stdout-path = &uart5;
34 clock-frequency = <1200000000>;
37 clock-frequency = <1200000000>;
43 u-boot,dm-pre-reloc;
48 clock-frequency = <400000000>;
65 pinctrl-names = "default";
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H A Dast2600-evb.dts1 /dts-v1/;
3 #include "ast2600-u-boot.dtsi"
7 compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
15 stdout-path = &uart5;
33 clock-frequency = <800000000>;
36 clock-frequency = <800000000>;
42 u-boot,dm-pre-reloc;
47 clock-frequency = <400000000>;
64 pinctrl-names = "default";
65 pinctrl-0 = < &pinctrl_mdio1_default &pinctrl_mdio2_default
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H A Dast2600-gb200nvl-bmc-nvidia.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
4 #include "ast2600-u-boot.dtsi"
8 compatible = "nvidia,gb200nvl-bmc", "aspeed,ast2600";
16 stdout-path = &uart5;
34 clock-frequency = <800000000>;
37 clock-frequency = <800000000>;
43 u-boot,dm-pre-reloc;
48 clock-frequency = <400000000>;
66 pinctrl-names = "default";
[all …]
H A Dtegra30-beaver.dts1 /dts-v1/;
10 stdout-path = &uarta;
31 pcie-controller@00003000 {
34 avdd-pexa-supply = <&ldo1_reg>;
35 vdd-pexa-supply = <&ldo1_reg>;
36 avdd-pexb-supply = <&ldo1_reg>;
37 vdd-pexb-supply = <&ldo1_reg>;
38 avdd-pex-pll-supply = <&ldo1_reg>;
39 avdd-plle-supply = <&ldo1_reg>;
40 vddio-pex-ctl-supply = <&sys_3v3_reg>;
[all …]
H A Dtegra124-cei-tk1-som.dts1 /dts-v1/;
6 model = "Colorado Engineering TK1-SOM";
7 compatible = "nvidia,cei-tk1-som", "nvidia,tegra124";
10 stdout-path = &uartd;
32 pcie-controller@01003000 {
35 avddio-pex-supply = <&vdd_1v05_run>;
36 dvddio-pex-supply = <&vdd_1v05_run>;
37 avdd-pex-pll-supply = <&vdd_1v05_run>;
38 hvdd-pex-supply = <&vdd_3v3_lp0>;
39 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
[all …]
H A Dtegra124-jetson-tk1.dts1 /dts-v1/;
7 compatible = "nvidia,jetson-tk1", "nvidia,tegra124";
10 stdout-path = &uartd;
32 pcie-controller@01003000 {
35 avddio-pex-supply = <&vdd_1v05_run>;
36 dvddio-pex-supply = <&vdd_1v05_run>;
37 avdd-pex-pll-supply = <&vdd_1v05_run>;
38 hvdd-pex-supply = <&vdd_3v3_lp0>;
39 hvdd-pex-pll-e-supply = <&vdd_3v3_lp0>;
40 vddio-pex-ctl-supply = <&vdd_3v3_lp0>;
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/openbmc/linux/Documentation/cpu-freq/
H A Dcpu-drivers.rst1 .. SPDX-License-Identifier: GPL-2.0
10 - Dominik Brodowski <linux@brodo.de>
11 - Rafael J. Wysocki <rafael.j.wysocki@intel.com>
12 - Viresh Kumar <viresh.kumar@linaro.org>
18 1.2 Per-CPU Initialization
24 2. Frequency Table Helpers
31 So, you just got a brand-new CPU / chipset with datasheets and want to
37 ------------------
46 .name - The name of this driver.
48 .init - A pointer to the per-policy initialization function.
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/openbmc/linux/include/linux/
H A Dcpufreq.h1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
28 * Frequency values here are CPU kHz
30 * Maximum transition latency is in nanoseconds - if it's unknown,
34 #define CPUFREQ_ETERNAL (-1)
51 /* in 10^(-9) s = nanoseconds */
69 unsigned int max; /* in kHz */ member
96 * - Any routine that wants to read from the policy structure will
98 * - Any routine that will write to the policy structure and/or may take away
106 * - fast_switch_possible should be set by the driver if it can
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/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-msm8960-cdp.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
4 #include "qcom-msm8960.dtsi"
8 compatible = "qcom,msm8960-cdp", "qcom,msm8960";
15 stdout-path = "serial0:115200n8";
18 ext_l2: gpio-regulator {
19 compatible = "regulator-fixed";
20 regulator-name = "ext_l2";
22 startup-delay-us = <10000>;
23 enable-active-high;
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H A Dqcom-msm8960-samsung-expressatt.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/input/input.h>
4 #include "qcom-msm8960.dtsi"
5 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
8 model = "Samsung Galaxy Express SGH-I437";
10 chassis-type = "handset";
19 stdout-path = "serial0:115200n8";
33 vmmc-supply = <&pm8921_l5>;
38 vmmc-supply = <&pm8921_l6>;
39 vqmmc-supply = <&pm8921_l7>;
[all …]
H A Dqcom-apq8064-sony-xperia-lagan-yuga.dts1 // SPDX-License-Identifier: GPL-2.0
2 #include "qcom-apq8064-v2.0.dtsi"
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
10 compatible = "sony,xperia-yuga", "qcom,apq8064";
11 chassis-type = "handset";
18 stdout-path = "serial0:115200n8";
21 gpio-keys {
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/openbmc/u-boot/doc/device-tree-bindings/spi/
H A Dspi-stm32-qspi.txt2 --------------------------------------------
5 - compatible : should be "st,stm32-qspi".
6 - reg : 1. Physical base address and size of SPI registers map.
8 - spi-max-frequency : Max supported spi frequency.
9 - status : enable in requried dts.
12 --------------------------
13 - spi-max-frequency : Max supported spi frequency.
14 - spi-tx-bus-width : Bus width (number of lines) for writing (1-4)
15 - spi-rx-bus-width : Bus width (number of lines) for reading (1-4)
16 - memory-map : Address and size for memory-mapping the flash
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/openbmc/linux/arch/arm/boot/dts/broadcom/
H A Dbcm28155-ap.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include <dt-bindings/gpio/gpio.h>
12 compatible = "brcm,bcm28155-ap", "brcm,bcm11351";
21 clock-frequency = <400000>;
26 clock-frequency = <400000>;
31 clock-frequency = <400000>;
36 clock-frequency = <100000>;
49 non-removable;
50 max-frequency = <48000000>;
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/openbmc/linux/Documentation/admin-guide/media/
H A Dsi4713.rst1 .. SPDX-License-Identifier: GPL-2.0
14 ----------------------------
26 Users must comply with local regulations on radio frequency (RF) transmission.
29 -------------------------
34 The I2C device driver exports a v4l2-subdev interface to the kernel.
36 using the v4l2-subdev calls (g_ext_ctrls, s_ext_ctrls).
42 Applications can use v4l2 radio API to specify frequency of operation, mute state,
48 ----------------------
51 Here is an output from v4l2-ctl util:
53 .. code-block:: none
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/openbmc/linux/arch/arm/boot/dts/samsung/
H A Dexynos5422-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
13 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
15 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
16 * from the LITTLE: Cortex-A7.
21 #address-cells = <1>;
22 #size-cells = <0>;
24 cpu-map {
58 compatible = "arm,cortex-a7";
61 clock-frequency = <1000000000>;
62 cci-control-port = <&cci_control0>;
[all …]
H A Dexynos5420-cpus.dtsi1 // SPDX-License-Identifier: GPL-2.0
14 * Exynos5420 and Exynos5800 always boot from Cortex-A15. On Exynos5422
16 * the gpg2-1 GPIO. By default all Exynos5422 based boards choose booting
17 * from the LITTLE: Cortex-A7.
22 #address-cells = <1>;
23 #size-cells = <0>;
25 cpu-map {
59 compatible = "arm,cortex-a15";
62 clock-frequency = <1800000000>;
63 cci-control-port = <&cci_control1>;
[all …]
/openbmc/linux/arch/riscv/boot/dts/sifive/
H A Dhifive-unmatched-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
4 #include "fu740-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pwm/pwm.h>
10 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
15 compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
19 stdout-path = "serial0";
23 timebase-frequency = <RTCCLK_FREQ>;
[all …]
H A Dhifive-unleashed-a00.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2018-2019 SiFive, Inc */
4 #include "fu540-c000.dtsi"
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/leds/common.h>
7 #include <dt-bindings/pwm/pwm.h>
9 /* Clock frequency (in Hz) of the PCB crystal for rtcclk */
14 compatible = "sifive,hifive-unleashed-a00", "sifive,fu540-c000",
18 stdout-path = "serial0";
22 timebase-frequency = <RTCCLK_FREQ>;
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dselftest_slpc.c1 // SPDX-License-Identifier: MIT
32 pr_err("Could not set min frequency to [%u]\n", freq); in slpc_set_min_freq()
45 pr_err("Could not set maximum frequency [%u]\n", in slpc_set_max_freq()
56 struct intel_guc_slpc *slpc = &gt->uc.guc.slpc; in slpc_set_freq()
60 pr_err("Unable to update max freq"); in slpc_set_freq()
73 static int slpc_restore_freq(struct intel_guc_slpc *slpc, u32 min, u32 max) in slpc_restore_freq() argument
77 err = slpc_set_max_freq(slpc, max); in slpc_restore_freq()
79 pr_err("Unable to restore max freq"); in slpc_restore_freq()
105 *freq = intel_rps_read_actual_frequency(&gt->rps); in measure_power_at_freq()
106 *power = measure_power(&gt->rps, freq); in measure_power_at_freq()
[all …]

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