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/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Dmac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
7 * e1000e_get_bus_info_pcie - Get PCIe bus information
16 struct e1000_mac_info *mac = &hw->mac; in e1000e_get_bus_info_pcie() local
17 struct e1000_bus_info *bus = &hw->bus; in e1000e_get_bus_info_pcie()
18 struct e1000_adapter *adapter = hw->adapter; in e1000e_get_bus_info_pcie()
21 cap_offset = adapter->pdev->pcie_cap; in e1000e_get_bus_info_pcie()
23 bus->width = e1000_bus_width_unknown; in e1000e_get_bus_info_pcie()
25 pci_read_config_word(adapter->pdev, in e1000e_get_bus_info_pcie()
28 bus->width = (enum e1000_bus_width)((pcie_link_status & in e1000e_get_bus_info_pcie()
[all …]
H A D82571.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
42 * e1000_init_phy_params_82571 - Init PHY func ptrs.
47 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_82571() local
50 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_82571()
51 phy->type = e1000_phy_none; in e1000_init_phy_params_82571()
55 phy->addr = 1; in e1000_init_phy_params_82571()
56 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_82571()
57 phy->reset_delay_us = 100; in e1000_init_phy_params_82571()
59 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_82571()
[all …]
H A Dethtool.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
28 "s0ix-enabled",
36 .sizeof_stat = sizeof(((struct e1000_adapter *)0)->m), \
41 .sizeof_stat = sizeof(((struct rtnl_link_stats64 *)0)->m), \
115 struct e1000_hw *hw = &adapter->hw; in e1000_get_link_ksettings()
117 if (hw->phy.media_type == e1000_media_type_copper) { in e1000_get_link_ksettings()
127 if (hw->phy.type == e1000_phy_ife) in e1000_get_link_ksettings()
131 if (hw->mac.autoneg == 1) { in e1000_get_link_ksettings()
134 advertising |= hw->phy.autoneg_advertised; in e1000_get_link_ksettings()
[all …]
H A D80003es2lan.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
35 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
40 struct e1000_phy_info *phy = &hw->phy; in e1000_init_phy_params_80003es2lan() local
43 if (hw->phy.media_type != e1000_media_type_copper) { in e1000_init_phy_params_80003es2lan()
44 phy->type = e1000_phy_none; in e1000_init_phy_params_80003es2lan()
47 phy->ops.power_up = e1000_power_up_phy_copper; in e1000_init_phy_params_80003es2lan()
48 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan; in e1000_init_phy_params_80003es2lan()
51 phy->addr = 1; in e1000_init_phy_params_80003es2lan()
52 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_init_phy_params_80003es2lan()
[all …]
H A Dich8lan.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
5 * 82562G-2 10/100 Network Connection
7 * 82562GT-2 10/100 Network Connection
9 * 82562V-2 10/100 Network Connection
10 * 82566DC-2 Gigabit Network Connection
12 * 82566DM-2 Gigabit Network Connection
19 * 82567LM-2 Gigabit Network Connection
20 * 82567LF-2 Gigabit Network Connection
21 * 82567V-2 Gigabit Network Connection
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H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
37 * e1000e_check_reset_block_generic - Check if PHY reset is blocked
40 * Read the PHY management control register and check whether a PHY reset
54 * e1000e_get_phy_id - Retrieve the PHY ID and revision
57 * Reads the PHY registers and stores the PHY ID and possibly the PHY
62 struct e1000_phy_info *phy = &hw->phy; in e1000e_get_phy_id() local
67 if (!phy->ops.read_reg) in e1000e_get_phy_id()
75 phy->id = (u32)(phy_id << 16); in e1000e_get_phy_id()
81 phy->id |= (u32)(phy_id & PHY_REVISION_MASK); in e1000e_get_phy_id()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igc/
H A Digc_base.c1 // SPDX-License-Identifier: GPL-2.0
13 * igc_reset_hw_base - Reset hardware
22 u32 ctrl; in igc_reset_hw_base() local
24 /* Prevent the PCI-E bus from sticking if there is no TLP connection in igc_reset_hw_base()
25 * on the last TLP read/write transaction when MAC is reset. in igc_reset_hw_base()
29 hw_dbg("PCI-E Master disable polling has failed\n"); in igc_reset_hw_base()
40 ctrl = rd32(IGC_CTRL); in igc_reset_hw_base()
42 hw_dbg("Issuing a global reset to MAC\n"); in igc_reset_hw_base()
43 wr32(IGC_CTRL, ctrl | IGC_CTRL_RST); in igc_reset_hw_base()
62 * igc_init_nvm_params_base - Init NVM func ptrs.
[all …]
H A Digc_mac.c1 // SPDX-License-Identifier: GPL-2.0
11 * igc_disable_pcie_master - Disables PCI-express master access
14 * Returns 0 (0) if successful, else returns -10
15 * (-IGC_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
18 * Disables PCI-Express master access and verifies there are no pending
25 u32 ctrl; in igc_disable_pcie_master() local
27 ctrl = rd32(IGC_CTRL); in igc_disable_pcie_master()
28 ctrl |= IGC_CTRL_GIO_MASTER_DISABLE; in igc_disable_pcie_master()
29 wr32(IGC_CTRL, ctrl); in igc_disable_pcie_master()
36 timeout--; in igc_disable_pcie_master()
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/openbmc/u-boot/drivers/net/
H A Dravb.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Copyright (C) 2015-2017 Renesas Electronics Corporation
103 u32 ctrl; member
135 u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1); in ravb_invalidate_dcache()
143 struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx]; in ravb_send()
149 desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len); in ravb_send()
150 desc->dptr = (uintptr_t)packet; in ravb_send()
154 if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0)) in ravb_send()
155 setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0); in ravb_send()
161 if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE) in ravb_send()
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H A De1000.c1 // SPDX-License-Identifier: GPL-2.0+
3 Intel Pro 1000 for ppcboot/das-u-boot
4 Drivers are port from Intel's Linux driver e1000-4.3.15
11 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
60 * Normally U-Boot does not support this anyway. To fix it in this driver,
160 * hw - Struct containing variables accessed by shared code
161 * eecd - EECD's current value
177 * hw - Struct containing variables accessed by shared code
178 * eecd - EECD's current value
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H A Dftmac110.c1 // SPDX-License-Identifier: GPL-2.0+
6 * Dante Su <dantesu@faraday-tech.com>
15 #include <asm/dma-mapping.h>
35 * accepts only 16-bits aligned address, 32-bits aligned is not
42 * 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
70 struct ftmac110_chip *chip = dev->priv; in mdio_read()
71 struct ftmac110_regs *regs = chip->regs; in mdio_read()
79 writel(tmp, &regs->phycr); in mdio_read()
82 tmp = readl(&regs->phycr); in mdio_read()
99 struct ftmac110_chip *chip = dev->priv; in mdio_write()
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/openbmc/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2006 Intel Corporation. */
5 * Shared functions for accessing and configuring the MAC
40 static void e1000_raise_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
41 static void e1000_lower_mdi_clk(struct e1000_hw *hw, u32 *ctrl);
89 * e1000_set_phy_type - Set the phy type member in the hw struct.
94 if (hw->mac_type == e1000_undefined) in e1000_set_phy_type()
95 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()
97 switch (hw->phy_id) { in e1000_set_phy_type()
103 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()
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/openbmc/linux/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_core.c1 // SPDX-License-Identifier: GPL-2.0-only
15 #include <linux/phy.h>
20 /* MAC core initialization */
43 /* Dump MAC registers */
87 /* Set/Get Unicast MAC addresses */
188 u32 ctrl; in sxgbe_set_eee_mode() local
191 * When Tx Automate bit is set, MAC internally handles the entry in sxgbe_set_eee_mode()
195 ctrl = readl(ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_set_eee_mode()
196 ctrl |= LPI_CTRL_STATUS_LPIEN | LPI_CTRL_STATUS_TXA; in sxgbe_set_eee_mode()
197 writel(ctrl, ioaddr + SXGBE_CORE_LPI_CTRL_STATUS); in sxgbe_set_eee_mode()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igb/
H A De1000_mac.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
18 * igb_get_bus_info_pcie - Get PCIe bus information
27 struct e1000_bus_info *bus = &hw->bus; in igb_get_bus_info_pcie()
32 bus->type = e1000_bus_type_pci_express; in igb_get_bus_info_pcie()
38 bus->width = e1000_bus_width_unknown; in igb_get_bus_info_pcie()
39 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
43 bus->speed = e1000_bus_speed_2500; in igb_get_bus_info_pcie()
46 bus->speed = e1000_bus_speed_5000; in igb_get_bus_info_pcie()
49 bus->speed = e1000_bus_speed_unknown; in igb_get_bus_info_pcie()
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H A De1000_82575.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
61 * igb_write_vfta_i350 - Write value to VLAN filter table
71 struct igb_adapter *adapter = hw->back; in igb_write_vfta_i350()
74 for (i = 10; i--;) in igb_write_vfta_i350()
78 adapter->shadow_vfta[offset] = value; in igb_write_vfta_i350()
82 * igb_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
93 switch (hw->mac.type) { in igb_sgmii_uses_mdio_82575()
114 * igb_check_for_link_media_swap - Check which M88E1112 interface linked
121 struct e1000_phy_info *phy = &hw->phy; in igb_check_for_link_media_swap() local
[all …]
H A De1000_phy.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
31 * igb_check_reset_block - Check if PHY reset is blocked
34 * Read the PHY management control register and check whether a PHY reset
48 * igb_get_phy_id - Retrieve the PHY ID and revision
51 * Reads the PHY registers and stores the PHY ID and possibly the PHY
56 struct e1000_phy_info *phy = &hw->phy; in igb_get_phy_id() local
60 /* ensure PHY page selection to fix misconfigured i210 */ in igb_get_phy_id()
61 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) in igb_get_phy_id()
62 phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0); in igb_get_phy_id()
[all …]
/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_82598.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
25 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
30 * than the 10ms recommended by the pci-e spec. To address this we need to
39 if (ixgbe_removed(hw->hw_addr)) in ixgbe_set_pcie_completion_timeout()
71 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_82598() local
73 /* Call PHY identify routine to get the phy type */ in ixgbe_get_invariants_82598()
76 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE; in ixgbe_get_invariants_82598()
77 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE; in ixgbe_get_invariants_82598()
78 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES; in ixgbe_get_invariants_82598()
[all …]
H A Dixgbe_x540.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
31 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X540() local
32 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X540() local
35 phy->ops.set_phy_power = ixgbe_set_copper_phy_power; in ixgbe_get_invariants_X540()
37 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; in ixgbe_get_invariants_X540()
38 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; in ixgbe_get_invariants_X540()
39 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; in ixgbe_get_invariants_X540()
40 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; in ixgbe_get_invariants_X540()
41 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; in ixgbe_get_invariants_X540()
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H A Dixgbe_x550.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X550_x() local
18 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x() local
19 struct ixgbe_link_info *link = &hw->link; in ixgbe_get_invariants_X550_x()
24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) in ixgbe_get_invariants_X550_x()
25 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x()
27 link->addr = IXGBE_CS4227; in ixgbe_get_invariants_X550_x()
34 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x_fw() local
39 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x_fw()
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H A Dixgbe_82599.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
65 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_init_mac_link_ops_82599() local
70 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) && in ixgbe_init_mac_link_ops_82599()
72 mac->ops.disable_tx_laser = in ixgbe_init_mac_link_ops_82599()
74 mac->ops.enable_tx_laser = in ixgbe_init_mac_link_ops_82599()
76 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber; in ixgbe_init_mac_link_ops_82599()
78 mac->ops.disable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
79 mac->ops.enable_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
80 mac->ops.flap_tx_laser = NULL; in ixgbe_init_mac_link_ops_82599()
[all …]
/openbmc/linux/drivers/net/ethernet/marvell/
H A Dskge.h1 /* SPDX-License-Identifier: GPL-2.0 */
133 CS_CLK_RUN_HOT = 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 CS_CLK_RUN_RST = 1<<12,/* CLK_RUN reset (YUKON-Lite only) */
135 CS_CLK_RUN_ENA = 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
175 IS_EXT_REG = 1<<23, /* IRQ from LM80 or PHY (GENESIS only) */
176 /* IRQ from PHY (YUKON only) */
178 IS_MAC1 = 1<<21, /* IRQ from MAC 1 */
179 IS_LNK_SYNC_M1 = 1<<20, /* Link Sync Cnt wrap MAC 1 */
180 IS_MAC2 = 1<<19, /* IRQ from MAC 2 */
181 IS_LNK_SYNC_M2 = 1<<18, /* Link Sync Cnt wrap MAC 2 */
[all …]
/openbmc/qemu/hw/net/
H A De1000x_common.h2 * QEMU e1000(e) emulation - shared code
29 e1000x_inc_reg_if_not_full(uint32_t *mac, int index) in e1000x_inc_reg_if_not_full() argument
31 if (mac[index] != UINT32_MAX) { in e1000x_inc_reg_if_not_full()
32 mac[index]++; in e1000x_inc_reg_if_not_full()
37 e1000x_grow_8reg_if_not_full(uint32_t *mac, int index, int size) in e1000x_grow_8reg_if_not_full() argument
39 uint64_t sum = mac[index] | (uint64_t)mac[index + 1] << 32; in e1000x_grow_8reg_if_not_full()
46 mac[index] = sum; in e1000x_grow_8reg_if_not_full()
47 mac[index + 1] = sum >> 32; in e1000x_grow_8reg_if_not_full()
51 e1000x_vlan_enabled(uint32_t *mac) in e1000x_vlan_enabled() argument
53 return ((mac[CTRL] & E1000_CTRL_VME) != 0); in e1000x_vlan_enabled()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Ddavinci_emac.txt7 - compatible: "ti,davinci-dm6467-emac", "ti,am3517-emac" or
8 "ti,dm816-emac"
9 - reg: Offset and length of the register set for the device
10 - ti,davinci-ctrl-reg-offset: offset to control register
11 - ti,davinci-ctrl-mod-reg-offset: offset to control module register
12 - ti,davinci-ctrl-ram-offset: offset to control module ram
13 - ti,davinci-ctrl-ram-size: size of control module ram
14 - interrupts: interrupt mapping for the davinci emac interrupts sources:
21 - phy-handle: See ethernet.txt file in the same directory.
23 - ti,davinci-rmii-en: 1 byte, 1 means use RMII
[all …]
/openbmc/linux/drivers/net/usb/
H A Dsmsc95xx.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 2007-2008 SMSC
38 /* SCSRs - System Control and Status Registers */
52 #define INT_STS_MAC_RTO_ (0x00040000) /* MAC Reset Time Out */
55 #define INT_STS_PHY_INT_ (0x00008000) /* PHY Interrupt */
84 #define HW_CFG_PSEL_ (0x00000004) /* External PHY Select */
106 #define PM_CTL_PHY_RST_ (0x00000010) /* PHY Reset */
126 #define AFC_CFG_HI_ (0x00FF0000) /* Auto Flow Ctrl High Level */
127 #define AFC_CFG_LO_ (0x0000FF00) /* Auto Flow Ctrl Low Level */
129 #define AFC_CFG_FC_MULT_ (0x00000008) /* Flow Ctrl on Mcast Frame */
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/openbmc/linux/Documentation/networking/
H A Dstatistics.rst1 .. SPDX-License-Identifier: GPL-2.0
14 - standard interface statistics based on
16 - protocol-specific statistics; and
17 - driver-defined statistics available via ethtool.
20 -----------------------------
25 $ ip -s -s link show dev ens4u1u1
38 Note that `-s` has been specified twice to see all members of
40 If `-s` is specified once the detailed errors won't be shown.
42 `ip` supports JSON formatting via the `-j` option.
44 Protocol-specific statistics
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