1ae06c70bSJeff Kirsher // SPDX-License-Identifier: GPL-2.0
251dce24bSJeff Kirsher /* Copyright(c) 1999 - 2018 Intel Corporation. */
3dee1ad47SJeff Kirsher
4dee1ad47SJeff Kirsher #include <linux/pci.h>
5dee1ad47SJeff Kirsher #include <linux/delay.h>
6dee1ad47SJeff Kirsher #include <linux/sched.h>
7dee1ad47SJeff Kirsher
8dee1ad47SJeff Kirsher #include "ixgbe.h"
9dee1ad47SJeff Kirsher #include "ixgbe_phy.h"
10dee1ad47SJeff Kirsher
11dee1ad47SJeff Kirsher #define IXGBE_82598_MAX_TX_QUEUES 32
12dee1ad47SJeff Kirsher #define IXGBE_82598_MAX_RX_QUEUES 64
13dee1ad47SJeff Kirsher #define IXGBE_82598_RAR_ENTRIES 16
14dee1ad47SJeff Kirsher #define IXGBE_82598_MC_TBL_SIZE 128
15dee1ad47SJeff Kirsher #define IXGBE_82598_VFT_TBL_SIZE 128
16dee1ad47SJeff Kirsher #define IXGBE_82598_RX_PB_SIZE 512
17dee1ad47SJeff Kirsher
18dee1ad47SJeff Kirsher static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
19dee1ad47SJeff Kirsher ixgbe_link_speed speed,
20dee1ad47SJeff Kirsher bool autoneg_wait_to_complete);
21dee1ad47SJeff Kirsher static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
22dee1ad47SJeff Kirsher u8 *eeprom_data);
23dee1ad47SJeff Kirsher
24dee1ad47SJeff Kirsher /**
25dee1ad47SJeff Kirsher * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
26dee1ad47SJeff Kirsher * @hw: pointer to the HW structure
27dee1ad47SJeff Kirsher *
28dee1ad47SJeff Kirsher * The defaults for 82598 should be in the range of 50us to 50ms,
29dee1ad47SJeff Kirsher * however the hardware default for these parts is 500us to 1ms which is less
30dee1ad47SJeff Kirsher * than the 10ms recommended by the pci-e spec. To address this we need to
31dee1ad47SJeff Kirsher * increase the value to either 10ms to 250ms for capability version 1 config,
32dee1ad47SJeff Kirsher * or 16ms to 55ms for version 2.
33dee1ad47SJeff Kirsher **/
ixgbe_set_pcie_completion_timeout(struct ixgbe_hw * hw)34dee1ad47SJeff Kirsher static void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
35dee1ad47SJeff Kirsher {
36dee1ad47SJeff Kirsher u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
37dee1ad47SJeff Kirsher u16 pcie_devctl2;
38dee1ad47SJeff Kirsher
3914438464SMark Rustad if (ixgbe_removed(hw->hw_addr))
4014438464SMark Rustad return;
4114438464SMark Rustad
42dee1ad47SJeff Kirsher /* only take action if timeout value is defaulted to 0 */
43dee1ad47SJeff Kirsher if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
44dee1ad47SJeff Kirsher goto out;
45dee1ad47SJeff Kirsher
46dee1ad47SJeff Kirsher /*
47dee1ad47SJeff Kirsher * if capababilities version is type 1 we can write the
48dee1ad47SJeff Kirsher * timeout of 10ms to 250ms through the GCR register
49dee1ad47SJeff Kirsher */
50dee1ad47SJeff Kirsher if (!(gcr & IXGBE_GCR_CAP_VER2)) {
51dee1ad47SJeff Kirsher gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
52dee1ad47SJeff Kirsher goto out;
53dee1ad47SJeff Kirsher }
54dee1ad47SJeff Kirsher
55dee1ad47SJeff Kirsher /*
56dee1ad47SJeff Kirsher * for version 2 capabilities we need to write the config space
57dee1ad47SJeff Kirsher * directly in order to set the completion timeout value for
58dee1ad47SJeff Kirsher * 16ms to 55ms
59dee1ad47SJeff Kirsher */
6014438464SMark Rustad pcie_devctl2 = ixgbe_read_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2);
61dee1ad47SJeff Kirsher pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
62ed19231cSJacob Keller ixgbe_write_pci_cfg_word(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
63dee1ad47SJeff Kirsher out:
64dee1ad47SJeff Kirsher /* disable completion timeout resend */
65dee1ad47SJeff Kirsher gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
66dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
67dee1ad47SJeff Kirsher }
68dee1ad47SJeff Kirsher
ixgbe_get_invariants_82598(struct ixgbe_hw * hw)69dee1ad47SJeff Kirsher static s32 ixgbe_get_invariants_82598(struct ixgbe_hw *hw)
70dee1ad47SJeff Kirsher {
71dee1ad47SJeff Kirsher struct ixgbe_mac_info *mac = &hw->mac;
72dee1ad47SJeff Kirsher
73dee1ad47SJeff Kirsher /* Call PHY identify routine to get the phy type */
74dee1ad47SJeff Kirsher ixgbe_identify_phy_generic(hw);
75dee1ad47SJeff Kirsher
76dee1ad47SJeff Kirsher mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
77dee1ad47SJeff Kirsher mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
78dee1ad47SJeff Kirsher mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
796997d4d1SJacob Keller mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE;
80dee1ad47SJeff Kirsher mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
81dee1ad47SJeff Kirsher mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
8271161302SEmil Tantilov mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
83dee1ad47SJeff Kirsher
84dee1ad47SJeff Kirsher return 0;
85dee1ad47SJeff Kirsher }
86dee1ad47SJeff Kirsher
87dee1ad47SJeff Kirsher /**
88dee1ad47SJeff Kirsher * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
89dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
90dee1ad47SJeff Kirsher *
91dee1ad47SJeff Kirsher * Initialize any function pointers that were not able to be
92dee1ad47SJeff Kirsher * set during get_invariants because the PHY/SFP type was
93dee1ad47SJeff Kirsher * not known. Perform the SFP init if necessary.
94dee1ad47SJeff Kirsher *
95dee1ad47SJeff Kirsher **/
ixgbe_init_phy_ops_82598(struct ixgbe_hw * hw)96dee1ad47SJeff Kirsher static s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
97dee1ad47SJeff Kirsher {
98dee1ad47SJeff Kirsher struct ixgbe_mac_info *mac = &hw->mac;
99dee1ad47SJeff Kirsher struct ixgbe_phy_info *phy = &hw->phy;
100e90dd264SMark Rustad s32 ret_val;
101dee1ad47SJeff Kirsher u16 list_offset, data_offset;
102dee1ad47SJeff Kirsher
103dee1ad47SJeff Kirsher /* Identify the PHY */
104dee1ad47SJeff Kirsher phy->ops.identify(hw);
105dee1ad47SJeff Kirsher
106dee1ad47SJeff Kirsher /* Overwrite the link function pointers if copper PHY */
107dee1ad47SJeff Kirsher if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
108dee1ad47SJeff Kirsher mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
109dee1ad47SJeff Kirsher mac->ops.get_link_capabilities =
110dee1ad47SJeff Kirsher &ixgbe_get_copper_link_capabilities_generic;
111dee1ad47SJeff Kirsher }
112dee1ad47SJeff Kirsher
113dee1ad47SJeff Kirsher switch (hw->phy.type) {
114dee1ad47SJeff Kirsher case ixgbe_phy_tn:
115dee1ad47SJeff Kirsher phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
116dee1ad47SJeff Kirsher phy->ops.check_link = &ixgbe_check_phy_link_tnx;
117dee1ad47SJeff Kirsher break;
118dee1ad47SJeff Kirsher case ixgbe_phy_nl:
119dee1ad47SJeff Kirsher phy->ops.reset = &ixgbe_reset_phy_nl;
120dee1ad47SJeff Kirsher
121dee1ad47SJeff Kirsher /* Call SFP+ identify routine to get the SFP+ module type */
122dee1ad47SJeff Kirsher ret_val = phy->ops.identify_sfp(hw);
123e90dd264SMark Rustad if (ret_val)
124e90dd264SMark Rustad return ret_val;
125e90dd264SMark Rustad if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
126*03c5b6d4SJedrzej Jagielski return -EOPNOTSUPP;
127dee1ad47SJeff Kirsher
128dee1ad47SJeff Kirsher /* Check to see if SFP+ module is supported */
129dee1ad47SJeff Kirsher ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
130dee1ad47SJeff Kirsher &list_offset,
131dee1ad47SJeff Kirsher &data_offset);
132e90dd264SMark Rustad if (ret_val)
133*03c5b6d4SJedrzej Jagielski return -EOPNOTSUPP;
134dee1ad47SJeff Kirsher break;
135dee1ad47SJeff Kirsher default:
136dee1ad47SJeff Kirsher break;
137dee1ad47SJeff Kirsher }
138dee1ad47SJeff Kirsher
139e90dd264SMark Rustad return 0;
140dee1ad47SJeff Kirsher }
141dee1ad47SJeff Kirsher
142dee1ad47SJeff Kirsher /**
143dee1ad47SJeff Kirsher * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
144dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
145dee1ad47SJeff Kirsher *
146dee1ad47SJeff Kirsher * Starts the hardware using the generic start_hw function.
147887012e8SJeff Kirsher * Disables relaxed ordering for archs other than SPARC
148887012e8SJeff Kirsher * Then set pcie completion timeout
149dee1ad47SJeff Kirsher *
150dee1ad47SJeff Kirsher **/
ixgbe_start_hw_82598(struct ixgbe_hw * hw)151dee1ad47SJeff Kirsher static s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
152dee1ad47SJeff Kirsher {
153e90dd264SMark Rustad s32 ret_val;
154dee1ad47SJeff Kirsher
155dee1ad47SJeff Kirsher ret_val = ixgbe_start_hw_generic(hw);
156e90dd264SMark Rustad if (ret_val)
157e90dd264SMark Rustad return ret_val;
158e90dd264SMark Rustad
159dee1ad47SJeff Kirsher /* set the completion timeout for interface */
160dee1ad47SJeff Kirsher ixgbe_set_pcie_completion_timeout(hw);
161dee1ad47SJeff Kirsher
162e90dd264SMark Rustad return 0;
163dee1ad47SJeff Kirsher }
164dee1ad47SJeff Kirsher
165dee1ad47SJeff Kirsher /**
166dee1ad47SJeff Kirsher * ixgbe_get_link_capabilities_82598 - Determines link capabilities
167dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
168dee1ad47SJeff Kirsher * @speed: pointer to link speed
169dee1ad47SJeff Kirsher * @autoneg: boolean auto-negotiation value
170dee1ad47SJeff Kirsher *
171dee1ad47SJeff Kirsher * Determines the link capabilities by reading the AUTOC register.
172dee1ad47SJeff Kirsher **/
ixgbe_get_link_capabilities_82598(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)173dee1ad47SJeff Kirsher static s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
174dee1ad47SJeff Kirsher ixgbe_link_speed *speed,
175dee1ad47SJeff Kirsher bool *autoneg)
176dee1ad47SJeff Kirsher {
177dee1ad47SJeff Kirsher u32 autoc = 0;
178dee1ad47SJeff Kirsher
179dee1ad47SJeff Kirsher /*
180dee1ad47SJeff Kirsher * Determine link capabilities based on the stored value of AUTOC,
181dee1ad47SJeff Kirsher * which represents EEPROM defaults. If AUTOC value has not been
182dee1ad47SJeff Kirsher * stored, use the current register value.
183dee1ad47SJeff Kirsher */
184dee1ad47SJeff Kirsher if (hw->mac.orig_link_settings_stored)
185dee1ad47SJeff Kirsher autoc = hw->mac.orig_autoc;
186dee1ad47SJeff Kirsher else
187dee1ad47SJeff Kirsher autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
188dee1ad47SJeff Kirsher
189dee1ad47SJeff Kirsher switch (autoc & IXGBE_AUTOC_LMS_MASK) {
190dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
191dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_1GB_FULL;
192dee1ad47SJeff Kirsher *autoneg = false;
193dee1ad47SJeff Kirsher break;
194dee1ad47SJeff Kirsher
195dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
196dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_10GB_FULL;
197dee1ad47SJeff Kirsher *autoneg = false;
198dee1ad47SJeff Kirsher break;
199dee1ad47SJeff Kirsher
200dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_1G_AN:
201dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_1GB_FULL;
202dee1ad47SJeff Kirsher *autoneg = true;
203dee1ad47SJeff Kirsher break;
204dee1ad47SJeff Kirsher
205dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_KX4_AN:
206dee1ad47SJeff Kirsher case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
207dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_UNKNOWN;
208dee1ad47SJeff Kirsher if (autoc & IXGBE_AUTOC_KX4_SUPP)
209dee1ad47SJeff Kirsher *speed |= IXGBE_LINK_SPEED_10GB_FULL;
210dee1ad47SJeff Kirsher if (autoc & IXGBE_AUTOC_KX_SUPP)
211dee1ad47SJeff Kirsher *speed |= IXGBE_LINK_SPEED_1GB_FULL;
212dee1ad47SJeff Kirsher *autoneg = true;
213dee1ad47SJeff Kirsher break;
214dee1ad47SJeff Kirsher
215dee1ad47SJeff Kirsher default:
216*03c5b6d4SJedrzej Jagielski return -EIO;
217dee1ad47SJeff Kirsher }
218dee1ad47SJeff Kirsher
219e90dd264SMark Rustad return 0;
220dee1ad47SJeff Kirsher }
221dee1ad47SJeff Kirsher
222dee1ad47SJeff Kirsher /**
223dee1ad47SJeff Kirsher * ixgbe_get_media_type_82598 - Determines media type
224dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
225dee1ad47SJeff Kirsher *
226dee1ad47SJeff Kirsher * Returns the media type (fiber, copper, backplane)
227dee1ad47SJeff Kirsher **/
ixgbe_get_media_type_82598(struct ixgbe_hw * hw)228dee1ad47SJeff Kirsher static enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
229dee1ad47SJeff Kirsher {
230dee1ad47SJeff Kirsher /* Detect if there is a copper PHY attached. */
231dee1ad47SJeff Kirsher switch (hw->phy.type) {
232dee1ad47SJeff Kirsher case ixgbe_phy_cu_unknown:
233dee1ad47SJeff Kirsher case ixgbe_phy_tn:
234e90dd264SMark Rustad return ixgbe_media_type_copper;
235e90dd264SMark Rustad
236dee1ad47SJeff Kirsher default:
237dee1ad47SJeff Kirsher break;
238dee1ad47SJeff Kirsher }
239dee1ad47SJeff Kirsher
240dee1ad47SJeff Kirsher /* Media type for I82598 is based on device ID */
241dee1ad47SJeff Kirsher switch (hw->device_id) {
242dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598:
243dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_BX:
244dee1ad47SJeff Kirsher /* Default device ID is mezzanine card KX/KX4 */
245e90dd264SMark Rustad return ixgbe_media_type_backplane;
246e90dd264SMark Rustad
247dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AF_DUAL_PORT:
248dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
249dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
250dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
251dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598EB_XF_LR:
252dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598EB_SFP_LOM:
253e90dd264SMark Rustad return ixgbe_media_type_fiber;
254e90dd264SMark Rustad
255dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598EB_CX4:
256dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
257e90dd264SMark Rustad return ixgbe_media_type_cx4;
258e90dd264SMark Rustad
259dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AT:
260dee1ad47SJeff Kirsher case IXGBE_DEV_ID_82598AT2:
261e90dd264SMark Rustad return ixgbe_media_type_copper;
262e90dd264SMark Rustad
263dee1ad47SJeff Kirsher default:
264e90dd264SMark Rustad return ixgbe_media_type_unknown;
265dee1ad47SJeff Kirsher }
266dee1ad47SJeff Kirsher }
267dee1ad47SJeff Kirsher
268dee1ad47SJeff Kirsher /**
269dee1ad47SJeff Kirsher * ixgbe_fc_enable_82598 - Enable flow control
270dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
271dee1ad47SJeff Kirsher *
272dee1ad47SJeff Kirsher * Enable flow control according to the current settings.
273dee1ad47SJeff Kirsher **/
ixgbe_fc_enable_82598(struct ixgbe_hw * hw)274041441d0SAlexander Duyck static s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
275dee1ad47SJeff Kirsher {
276dee1ad47SJeff Kirsher u32 fctrl_reg;
277dee1ad47SJeff Kirsher u32 rmcs_reg;
278dee1ad47SJeff Kirsher u32 reg;
279041441d0SAlexander Duyck u32 fcrtl, fcrth;
280dee1ad47SJeff Kirsher u32 link_speed = 0;
281041441d0SAlexander Duyck int i;
282dee1ad47SJeff Kirsher bool link_up;
283dee1ad47SJeff Kirsher
284e5776620SJacob Keller /* Validate the water mark configuration */
285e90dd264SMark Rustad if (!hw->fc.pause_time)
286*03c5b6d4SJedrzej Jagielski return -EINVAL;
287e5776620SJacob Keller
288e5776620SJacob Keller /* Low water mark of zero causes XOFF floods */
289e5776620SJacob Keller for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
290e5776620SJacob Keller if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
291e5776620SJacob Keller hw->fc.high_water[i]) {
292e5776620SJacob Keller if (!hw->fc.low_water[i] ||
293e5776620SJacob Keller hw->fc.low_water[i] >= hw->fc.high_water[i]) {
294041441d0SAlexander Duyck hw_dbg(hw, "Invalid water mark configuration\n");
295*03c5b6d4SJedrzej Jagielski return -EINVAL;
296041441d0SAlexander Duyck }
297e5776620SJacob Keller }
298e5776620SJacob Keller }
299dee1ad47SJeff Kirsher
300dee1ad47SJeff Kirsher /*
301dee1ad47SJeff Kirsher * On 82598 having Rx FC on causes resets while doing 1G
302dee1ad47SJeff Kirsher * so if it's on turn it off once we know link_speed. For
303dee1ad47SJeff Kirsher * more details see 82598 Specification update.
304dee1ad47SJeff Kirsher */
305dee1ad47SJeff Kirsher hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
306dee1ad47SJeff Kirsher if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
307dee1ad47SJeff Kirsher switch (hw->fc.requested_mode) {
308dee1ad47SJeff Kirsher case ixgbe_fc_full:
309dee1ad47SJeff Kirsher hw->fc.requested_mode = ixgbe_fc_tx_pause;
310dee1ad47SJeff Kirsher break;
311dee1ad47SJeff Kirsher case ixgbe_fc_rx_pause:
312dee1ad47SJeff Kirsher hw->fc.requested_mode = ixgbe_fc_none;
313dee1ad47SJeff Kirsher break;
314dee1ad47SJeff Kirsher default:
315dee1ad47SJeff Kirsher /* no change */
316dee1ad47SJeff Kirsher break;
317dee1ad47SJeff Kirsher }
318dee1ad47SJeff Kirsher }
319dee1ad47SJeff Kirsher
320dee1ad47SJeff Kirsher /* Negotiate the fc mode to use */
3212916500dSDon Skidmore hw->mac.ops.fc_autoneg(hw);
322dee1ad47SJeff Kirsher
323dee1ad47SJeff Kirsher /* Disable any previous flow control settings */
324dee1ad47SJeff Kirsher fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
325dee1ad47SJeff Kirsher fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
326dee1ad47SJeff Kirsher
327dee1ad47SJeff Kirsher rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
328dee1ad47SJeff Kirsher rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
329dee1ad47SJeff Kirsher
330dee1ad47SJeff Kirsher /*
331dee1ad47SJeff Kirsher * The possible values of fc.current_mode are:
332dee1ad47SJeff Kirsher * 0: Flow control is completely disabled
333dee1ad47SJeff Kirsher * 1: Rx flow control is enabled (we can receive pause frames,
334dee1ad47SJeff Kirsher * but not send pause frames).
335dee1ad47SJeff Kirsher * 2: Tx flow control is enabled (we can send pause frames but
336dee1ad47SJeff Kirsher * we do not support receiving pause frames).
337dee1ad47SJeff Kirsher * 3: Both Rx and Tx flow control (symmetric) are enabled.
338dee1ad47SJeff Kirsher * other: Invalid.
339dee1ad47SJeff Kirsher */
340dee1ad47SJeff Kirsher switch (hw->fc.current_mode) {
341dee1ad47SJeff Kirsher case ixgbe_fc_none:
342dee1ad47SJeff Kirsher /*
343dee1ad47SJeff Kirsher * Flow control is disabled by software override or autoneg.
344dee1ad47SJeff Kirsher * The code below will actually disable it in the HW.
345dee1ad47SJeff Kirsher */
346dee1ad47SJeff Kirsher break;
347dee1ad47SJeff Kirsher case ixgbe_fc_rx_pause:
348dee1ad47SJeff Kirsher /*
349dee1ad47SJeff Kirsher * Rx Flow control is enabled and Tx Flow control is
350dee1ad47SJeff Kirsher * disabled by software override. Since there really
351dee1ad47SJeff Kirsher * isn't a way to advertise that we are capable of RX
352dee1ad47SJeff Kirsher * Pause ONLY, we will advertise that we support both
353dee1ad47SJeff Kirsher * symmetric and asymmetric Rx PAUSE. Later, we will
354dee1ad47SJeff Kirsher * disable the adapter's ability to send PAUSE frames.
355dee1ad47SJeff Kirsher */
356dee1ad47SJeff Kirsher fctrl_reg |= IXGBE_FCTRL_RFCE;
357dee1ad47SJeff Kirsher break;
358dee1ad47SJeff Kirsher case ixgbe_fc_tx_pause:
359dee1ad47SJeff Kirsher /*
360dee1ad47SJeff Kirsher * Tx Flow control is enabled, and Rx Flow control is
361dee1ad47SJeff Kirsher * disabled by software override.
362dee1ad47SJeff Kirsher */
363dee1ad47SJeff Kirsher rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
364dee1ad47SJeff Kirsher break;
365dee1ad47SJeff Kirsher case ixgbe_fc_full:
366dee1ad47SJeff Kirsher /* Flow control (both Rx and Tx) is enabled by SW override. */
367dee1ad47SJeff Kirsher fctrl_reg |= IXGBE_FCTRL_RFCE;
368dee1ad47SJeff Kirsher rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
369dee1ad47SJeff Kirsher break;
370dee1ad47SJeff Kirsher default:
371dee1ad47SJeff Kirsher hw_dbg(hw, "Flow control param set incorrectly\n");
372*03c5b6d4SJedrzej Jagielski return -EIO;
373dee1ad47SJeff Kirsher }
374dee1ad47SJeff Kirsher
375dee1ad47SJeff Kirsher /* Set 802.3x based flow control settings. */
376dee1ad47SJeff Kirsher fctrl_reg |= IXGBE_FCTRL_DPF;
377dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
378dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
379dee1ad47SJeff Kirsher
380dee1ad47SJeff Kirsher /* Set up and enable Rx high/low water mark thresholds, enable XON. */
381041441d0SAlexander Duyck for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
382041441d0SAlexander Duyck if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
383041441d0SAlexander Duyck hw->fc.high_water[i]) {
384e5776620SJacob Keller fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
385041441d0SAlexander Duyck fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
386041441d0SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
387041441d0SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
388041441d0SAlexander Duyck } else {
389041441d0SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
390041441d0SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
391041441d0SAlexander Duyck }
392dee1ad47SJeff Kirsher
393dee1ad47SJeff Kirsher }
394dee1ad47SJeff Kirsher
395dee1ad47SJeff Kirsher /* Configure pause time (2 TCs per register) */
396041441d0SAlexander Duyck reg = hw->fc.pause_time * 0x00010001;
397041441d0SAlexander Duyck for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
398041441d0SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
399dee1ad47SJeff Kirsher
400041441d0SAlexander Duyck /* Configure flow control refresh threshold value */
401041441d0SAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
402dee1ad47SJeff Kirsher
403e90dd264SMark Rustad return 0;
404dee1ad47SJeff Kirsher }
405dee1ad47SJeff Kirsher
406dee1ad47SJeff Kirsher /**
407dee1ad47SJeff Kirsher * ixgbe_start_mac_link_82598 - Configures MAC link settings
408dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
4095ba643c6STony Nguyen * @autoneg_wait_to_complete: true when waiting for completion is needed
410dee1ad47SJeff Kirsher *
411dee1ad47SJeff Kirsher * Configures link settings based on values in the ixgbe_hw struct.
412dee1ad47SJeff Kirsher * Restarts the link. Performs autonegotiation if needed.
413dee1ad47SJeff Kirsher **/
ixgbe_start_mac_link_82598(struct ixgbe_hw * hw,bool autoneg_wait_to_complete)414dee1ad47SJeff Kirsher static s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
415dee1ad47SJeff Kirsher bool autoneg_wait_to_complete)
416dee1ad47SJeff Kirsher {
417dee1ad47SJeff Kirsher u32 autoc_reg;
418dee1ad47SJeff Kirsher u32 links_reg;
419dee1ad47SJeff Kirsher u32 i;
420dee1ad47SJeff Kirsher s32 status = 0;
421dee1ad47SJeff Kirsher
422dee1ad47SJeff Kirsher /* Restart link */
423dee1ad47SJeff Kirsher autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
424dee1ad47SJeff Kirsher autoc_reg |= IXGBE_AUTOC_AN_RESTART;
425dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
426dee1ad47SJeff Kirsher
427dee1ad47SJeff Kirsher /* Only poll for autoneg to complete if specified to do so */
428dee1ad47SJeff Kirsher if (autoneg_wait_to_complete) {
429dee1ad47SJeff Kirsher if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
430dee1ad47SJeff Kirsher IXGBE_AUTOC_LMS_KX4_AN ||
431dee1ad47SJeff Kirsher (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
432dee1ad47SJeff Kirsher IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
433dee1ad47SJeff Kirsher links_reg = 0; /* Just in case Autoneg time = 0 */
434dee1ad47SJeff Kirsher for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
435dee1ad47SJeff Kirsher links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
436dee1ad47SJeff Kirsher if (links_reg & IXGBE_LINKS_KX_AN_COMP)
437dee1ad47SJeff Kirsher break;
438dee1ad47SJeff Kirsher msleep(100);
439dee1ad47SJeff Kirsher }
440dee1ad47SJeff Kirsher if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
441*03c5b6d4SJedrzej Jagielski status = -EIO;
442dee1ad47SJeff Kirsher hw_dbg(hw, "Autonegotiation did not complete.\n");
443dee1ad47SJeff Kirsher }
444dee1ad47SJeff Kirsher }
445dee1ad47SJeff Kirsher }
446dee1ad47SJeff Kirsher
447dee1ad47SJeff Kirsher /* Add delay to filter out noises during initial link setup */
448dee1ad47SJeff Kirsher msleep(50);
449dee1ad47SJeff Kirsher
450dee1ad47SJeff Kirsher return status;
451dee1ad47SJeff Kirsher }
452dee1ad47SJeff Kirsher
453dee1ad47SJeff Kirsher /**
454dee1ad47SJeff Kirsher * ixgbe_validate_link_ready - Function looks for phy link
455dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
456dee1ad47SJeff Kirsher *
457dee1ad47SJeff Kirsher * Function indicates success when phy link is available. If phy is not ready
458dee1ad47SJeff Kirsher * within 5 seconds of MAC indicating link, the function returns error.
459dee1ad47SJeff Kirsher **/
ixgbe_validate_link_ready(struct ixgbe_hw * hw)460dee1ad47SJeff Kirsher static s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
461dee1ad47SJeff Kirsher {
462dee1ad47SJeff Kirsher u32 timeout;
463dee1ad47SJeff Kirsher u16 an_reg;
464dee1ad47SJeff Kirsher
465dee1ad47SJeff Kirsher if (hw->device_id != IXGBE_DEV_ID_82598AT2)
466dee1ad47SJeff Kirsher return 0;
467dee1ad47SJeff Kirsher
468dee1ad47SJeff Kirsher for (timeout = 0;
469dee1ad47SJeff Kirsher timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
470dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, MDIO_STAT1, MDIO_MMD_AN, &an_reg);
471dee1ad47SJeff Kirsher
472dee1ad47SJeff Kirsher if ((an_reg & MDIO_AN_STAT1_COMPLETE) &&
473dee1ad47SJeff Kirsher (an_reg & MDIO_STAT1_LSTATUS))
474dee1ad47SJeff Kirsher break;
475dee1ad47SJeff Kirsher
476dee1ad47SJeff Kirsher msleep(100);
477dee1ad47SJeff Kirsher }
478dee1ad47SJeff Kirsher
479dee1ad47SJeff Kirsher if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
480dee1ad47SJeff Kirsher hw_dbg(hw, "Link was indicated but link is down\n");
481*03c5b6d4SJedrzej Jagielski return -EIO;
482dee1ad47SJeff Kirsher }
483dee1ad47SJeff Kirsher
484dee1ad47SJeff Kirsher return 0;
485dee1ad47SJeff Kirsher }
486dee1ad47SJeff Kirsher
487dee1ad47SJeff Kirsher /**
488dee1ad47SJeff Kirsher * ixgbe_check_mac_link_82598 - Get link/speed status
489dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
490dee1ad47SJeff Kirsher * @speed: pointer to link speed
491dee1ad47SJeff Kirsher * @link_up: true is link is up, false otherwise
492dee1ad47SJeff Kirsher * @link_up_wait_to_complete: bool used to wait for link up or not
493dee1ad47SJeff Kirsher *
494dee1ad47SJeff Kirsher * Reads the links register to determine if link is up and the current speed
495dee1ad47SJeff Kirsher **/
ixgbe_check_mac_link_82598(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up,bool link_up_wait_to_complete)496dee1ad47SJeff Kirsher static s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
497dee1ad47SJeff Kirsher ixgbe_link_speed *speed, bool *link_up,
498dee1ad47SJeff Kirsher bool link_up_wait_to_complete)
499dee1ad47SJeff Kirsher {
500dee1ad47SJeff Kirsher u32 links_reg;
501dee1ad47SJeff Kirsher u32 i;
502dee1ad47SJeff Kirsher u16 link_reg, adapt_comp_reg;
503dee1ad47SJeff Kirsher
504dee1ad47SJeff Kirsher /*
505dee1ad47SJeff Kirsher * SERDES PHY requires us to read link status from register 0xC79F.
506dee1ad47SJeff Kirsher * Bit 0 set indicates link is up/ready; clear indicates link down.
507dee1ad47SJeff Kirsher * 0xC00C is read to check that the XAUI lanes are active. Bit 0
508dee1ad47SJeff Kirsher * clear indicates active; set indicates inactive.
509dee1ad47SJeff Kirsher */
510dee1ad47SJeff Kirsher if (hw->phy.type == ixgbe_phy_nl) {
511dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
512dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC79F, MDIO_MMD_PMAPMD, &link_reg);
513dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC00C, MDIO_MMD_PMAPMD,
514dee1ad47SJeff Kirsher &adapt_comp_reg);
515dee1ad47SJeff Kirsher if (link_up_wait_to_complete) {
516dee1ad47SJeff Kirsher for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
517dee1ad47SJeff Kirsher if ((link_reg & 1) &&
518dee1ad47SJeff Kirsher ((adapt_comp_reg & 1) == 0)) {
519dee1ad47SJeff Kirsher *link_up = true;
520dee1ad47SJeff Kirsher break;
521dee1ad47SJeff Kirsher } else {
522dee1ad47SJeff Kirsher *link_up = false;
523dee1ad47SJeff Kirsher }
524dee1ad47SJeff Kirsher msleep(100);
525dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC79F,
526dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD,
527dee1ad47SJeff Kirsher &link_reg);
528dee1ad47SJeff Kirsher hw->phy.ops.read_reg(hw, 0xC00C,
529dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD,
530dee1ad47SJeff Kirsher &adapt_comp_reg);
531dee1ad47SJeff Kirsher }
532dee1ad47SJeff Kirsher } else {
533dee1ad47SJeff Kirsher if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
534dee1ad47SJeff Kirsher *link_up = true;
535dee1ad47SJeff Kirsher else
536dee1ad47SJeff Kirsher *link_up = false;
537dee1ad47SJeff Kirsher }
538dee1ad47SJeff Kirsher
53923677ce3SJoe Perches if (!*link_up)
540e90dd264SMark Rustad return 0;
541dee1ad47SJeff Kirsher }
542dee1ad47SJeff Kirsher
543dee1ad47SJeff Kirsher links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
544dee1ad47SJeff Kirsher if (link_up_wait_to_complete) {
545dee1ad47SJeff Kirsher for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
546dee1ad47SJeff Kirsher if (links_reg & IXGBE_LINKS_UP) {
547dee1ad47SJeff Kirsher *link_up = true;
548dee1ad47SJeff Kirsher break;
549dee1ad47SJeff Kirsher } else {
550dee1ad47SJeff Kirsher *link_up = false;
551dee1ad47SJeff Kirsher }
552dee1ad47SJeff Kirsher msleep(100);
553dee1ad47SJeff Kirsher links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
554dee1ad47SJeff Kirsher }
555dee1ad47SJeff Kirsher } else {
556dee1ad47SJeff Kirsher if (links_reg & IXGBE_LINKS_UP)
557dee1ad47SJeff Kirsher *link_up = true;
558dee1ad47SJeff Kirsher else
559dee1ad47SJeff Kirsher *link_up = false;
560dee1ad47SJeff Kirsher }
561dee1ad47SJeff Kirsher
562dee1ad47SJeff Kirsher if (links_reg & IXGBE_LINKS_SPEED)
563dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_10GB_FULL;
564dee1ad47SJeff Kirsher else
565dee1ad47SJeff Kirsher *speed = IXGBE_LINK_SPEED_1GB_FULL;
566dee1ad47SJeff Kirsher
56723677ce3SJoe Perches if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && *link_up &&
568dee1ad47SJeff Kirsher (ixgbe_validate_link_ready(hw) != 0))
569dee1ad47SJeff Kirsher *link_up = false;
570dee1ad47SJeff Kirsher
571dee1ad47SJeff Kirsher return 0;
572dee1ad47SJeff Kirsher }
573dee1ad47SJeff Kirsher
574dee1ad47SJeff Kirsher /**
575dee1ad47SJeff Kirsher * ixgbe_setup_mac_link_82598 - Set MAC link speed
576dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
577dee1ad47SJeff Kirsher * @speed: new link speed
578dee1ad47SJeff Kirsher * @autoneg_wait_to_complete: true when waiting for completion is needed
579dee1ad47SJeff Kirsher *
580dee1ad47SJeff Kirsher * Set the link speed in the AUTOC register and restarts link.
581dee1ad47SJeff Kirsher **/
ixgbe_setup_mac_link_82598(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)582dee1ad47SJeff Kirsher static s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
583fd0326f2SJosh Hay ixgbe_link_speed speed,
584dee1ad47SJeff Kirsher bool autoneg_wait_to_complete)
585dee1ad47SJeff Kirsher {
586fd0326f2SJosh Hay bool autoneg = false;
587dee1ad47SJeff Kirsher ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
588dee1ad47SJeff Kirsher u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
589dee1ad47SJeff Kirsher u32 autoc = curr_autoc;
590dee1ad47SJeff Kirsher u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
591dee1ad47SJeff Kirsher
592dee1ad47SJeff Kirsher /* Check to see if speed passed in is supported. */
593dee1ad47SJeff Kirsher ixgbe_get_link_capabilities_82598(hw, &link_capabilities, &autoneg);
594dee1ad47SJeff Kirsher speed &= link_capabilities;
595dee1ad47SJeff Kirsher
596dee1ad47SJeff Kirsher if (speed == IXGBE_LINK_SPEED_UNKNOWN)
597*03c5b6d4SJedrzej Jagielski return -EINVAL;
598dee1ad47SJeff Kirsher
599dee1ad47SJeff Kirsher /* Set KX4/KX support according to speed requested */
600dee1ad47SJeff Kirsher else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
601dee1ad47SJeff Kirsher link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
602dee1ad47SJeff Kirsher autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
603dee1ad47SJeff Kirsher if (speed & IXGBE_LINK_SPEED_10GB_FULL)
604dee1ad47SJeff Kirsher autoc |= IXGBE_AUTOC_KX4_SUPP;
605dee1ad47SJeff Kirsher if (speed & IXGBE_LINK_SPEED_1GB_FULL)
606dee1ad47SJeff Kirsher autoc |= IXGBE_AUTOC_KX_SUPP;
607dee1ad47SJeff Kirsher if (autoc != curr_autoc)
608dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
609dee1ad47SJeff Kirsher }
610dee1ad47SJeff Kirsher
611e90dd264SMark Rustad /* Setup and restart the link based on the new values in
612dee1ad47SJeff Kirsher * ixgbe_hw This will write the AUTOC register based on the new
613dee1ad47SJeff Kirsher * stored values
614dee1ad47SJeff Kirsher */
615e90dd264SMark Rustad return ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
616dee1ad47SJeff Kirsher }
617dee1ad47SJeff Kirsher
618dee1ad47SJeff Kirsher
619dee1ad47SJeff Kirsher /**
620dee1ad47SJeff Kirsher * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
621dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
622dee1ad47SJeff Kirsher * @speed: new link speed
623dee1ad47SJeff Kirsher * @autoneg_wait_to_complete: true if waiting is needed to complete
624dee1ad47SJeff Kirsher *
625dee1ad47SJeff Kirsher * Sets the link speed in the AUTOC register in the MAC and restarts link.
626dee1ad47SJeff Kirsher **/
ixgbe_setup_copper_link_82598(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)627dee1ad47SJeff Kirsher static s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
628dee1ad47SJeff Kirsher ixgbe_link_speed speed,
629dee1ad47SJeff Kirsher bool autoneg_wait_to_complete)
630dee1ad47SJeff Kirsher {
631dee1ad47SJeff Kirsher s32 status;
632dee1ad47SJeff Kirsher
633dee1ad47SJeff Kirsher /* Setup the PHY according to input speed */
63499b76642SJosh Hay status = hw->phy.ops.setup_link_speed(hw, speed,
635dee1ad47SJeff Kirsher autoneg_wait_to_complete);
636dee1ad47SJeff Kirsher /* Set up MAC */
637dee1ad47SJeff Kirsher ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
638dee1ad47SJeff Kirsher
639dee1ad47SJeff Kirsher return status;
640dee1ad47SJeff Kirsher }
641dee1ad47SJeff Kirsher
642dee1ad47SJeff Kirsher /**
643dee1ad47SJeff Kirsher * ixgbe_reset_hw_82598 - Performs hardware reset
644dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
645dee1ad47SJeff Kirsher *
646dee1ad47SJeff Kirsher * Resets the hardware by resetting the transmit and receive units, masks and
647dee1ad47SJeff Kirsher * clears all interrupts, performing a PHY reset, and performing a link (MAC)
648dee1ad47SJeff Kirsher * reset.
649dee1ad47SJeff Kirsher **/
ixgbe_reset_hw_82598(struct ixgbe_hw * hw)650dee1ad47SJeff Kirsher static s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
651dee1ad47SJeff Kirsher {
652e90dd264SMark Rustad s32 status;
653dee1ad47SJeff Kirsher s32 phy_status = 0;
654dee1ad47SJeff Kirsher u32 ctrl;
655dee1ad47SJeff Kirsher u32 gheccr;
656dee1ad47SJeff Kirsher u32 i;
657dee1ad47SJeff Kirsher u32 autoc;
658dee1ad47SJeff Kirsher u8 analog_val;
659dee1ad47SJeff Kirsher
660dee1ad47SJeff Kirsher /* Call adapter stop to disable tx/rx and clear interrupts */
661ff9d1a5aSEmil Tantilov status = hw->mac.ops.stop_adapter(hw);
662e90dd264SMark Rustad if (status)
663e90dd264SMark Rustad return status;
664dee1ad47SJeff Kirsher
665dee1ad47SJeff Kirsher /*
666dee1ad47SJeff Kirsher * Power up the Atlas Tx lanes if they are currently powered down.
667dee1ad47SJeff Kirsher * Atlas Tx lanes are powered down for MAC loopback tests, but
668dee1ad47SJeff Kirsher * they are not automatically restored on reset.
669dee1ad47SJeff Kirsher */
670dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
671dee1ad47SJeff Kirsher if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
672dee1ad47SJeff Kirsher /* Enable Tx Atlas so packets can be transmitted again */
673dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
674dee1ad47SJeff Kirsher &analog_val);
675dee1ad47SJeff Kirsher analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
676dee1ad47SJeff Kirsher hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
677dee1ad47SJeff Kirsher analog_val);
678dee1ad47SJeff Kirsher
679dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
680dee1ad47SJeff Kirsher &analog_val);
681dee1ad47SJeff Kirsher analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
682dee1ad47SJeff Kirsher hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
683dee1ad47SJeff Kirsher analog_val);
684dee1ad47SJeff Kirsher
685dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
686dee1ad47SJeff Kirsher &analog_val);
687dee1ad47SJeff Kirsher analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
688dee1ad47SJeff Kirsher hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
689dee1ad47SJeff Kirsher analog_val);
690dee1ad47SJeff Kirsher
691dee1ad47SJeff Kirsher hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
692dee1ad47SJeff Kirsher &analog_val);
693dee1ad47SJeff Kirsher analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
694dee1ad47SJeff Kirsher hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
695dee1ad47SJeff Kirsher analog_val);
696dee1ad47SJeff Kirsher }
697dee1ad47SJeff Kirsher
698dee1ad47SJeff Kirsher /* Reset PHY */
699dee1ad47SJeff Kirsher if (hw->phy.reset_disable == false) {
700dee1ad47SJeff Kirsher /* PHY ops must be identified and initialized prior to reset */
701dee1ad47SJeff Kirsher
702dee1ad47SJeff Kirsher /* Init PHY and function pointers, perform SFP setup */
703dee1ad47SJeff Kirsher phy_status = hw->phy.ops.init(hw);
704*03c5b6d4SJedrzej Jagielski if (phy_status == -EOPNOTSUPP)
705e90dd264SMark Rustad return phy_status;
706*03c5b6d4SJedrzej Jagielski if (phy_status == -ENOENT)
707ff9d1a5aSEmil Tantilov goto mac_reset_top;
708dee1ad47SJeff Kirsher
709dee1ad47SJeff Kirsher hw->phy.ops.reset(hw);
710dee1ad47SJeff Kirsher }
711dee1ad47SJeff Kirsher
712dee1ad47SJeff Kirsher mac_reset_top:
713dee1ad47SJeff Kirsher /*
714dee1ad47SJeff Kirsher * Issue global reset to the MAC. This needs to be a SW reset.
715dee1ad47SJeff Kirsher * If link reset is used, it might reset the MAC when mng is using it
716dee1ad47SJeff Kirsher */
7178132b54eSAlexander Duyck ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
7188132b54eSAlexander Duyck IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
719dee1ad47SJeff Kirsher IXGBE_WRITE_FLUSH(hw);
720efff2e02SMark Rustad usleep_range(1000, 1200);
721dee1ad47SJeff Kirsher
722dee1ad47SJeff Kirsher /* Poll for reset bit to self-clear indicating reset is complete */
723dee1ad47SJeff Kirsher for (i = 0; i < 10; i++) {
724dee1ad47SJeff Kirsher ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
725dee1ad47SJeff Kirsher if (!(ctrl & IXGBE_CTRL_RST))
726dee1ad47SJeff Kirsher break;
727efff2e02SMark Rustad udelay(1);
728dee1ad47SJeff Kirsher }
729dee1ad47SJeff Kirsher if (ctrl & IXGBE_CTRL_RST) {
730*03c5b6d4SJedrzej Jagielski status = -EIO;
731dee1ad47SJeff Kirsher hw_dbg(hw, "Reset polling failed to complete.\n");
732dee1ad47SJeff Kirsher }
733dee1ad47SJeff Kirsher
7348132b54eSAlexander Duyck msleep(50);
7358132b54eSAlexander Duyck
736dee1ad47SJeff Kirsher /*
737dee1ad47SJeff Kirsher * Double resets are required for recovery from certain error
738dee1ad47SJeff Kirsher * conditions. Between resets, it is necessary to stall to allow time
7398132b54eSAlexander Duyck * for any pending HW events to complete.
740dee1ad47SJeff Kirsher */
741dee1ad47SJeff Kirsher if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
742dee1ad47SJeff Kirsher hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
743dee1ad47SJeff Kirsher goto mac_reset_top;
744dee1ad47SJeff Kirsher }
745dee1ad47SJeff Kirsher
746dee1ad47SJeff Kirsher gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
747b4f47a48SJacob Keller gheccr &= ~(BIT(21) | BIT(18) | BIT(9) | BIT(6));
748dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
749dee1ad47SJeff Kirsher
750dee1ad47SJeff Kirsher /*
751dee1ad47SJeff Kirsher * Store the original AUTOC value if it has not been
752dee1ad47SJeff Kirsher * stored off yet. Otherwise restore the stored original
753dee1ad47SJeff Kirsher * AUTOC value since the reset operation sets back to deaults.
754dee1ad47SJeff Kirsher */
755dee1ad47SJeff Kirsher autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
756dee1ad47SJeff Kirsher if (hw->mac.orig_link_settings_stored == false) {
757dee1ad47SJeff Kirsher hw->mac.orig_autoc = autoc;
758dee1ad47SJeff Kirsher hw->mac.orig_link_settings_stored = true;
759dee1ad47SJeff Kirsher } else if (autoc != hw->mac.orig_autoc) {
760dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
761dee1ad47SJeff Kirsher }
762dee1ad47SJeff Kirsher
763dee1ad47SJeff Kirsher /* Store the permanent mac address */
764dee1ad47SJeff Kirsher hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
765dee1ad47SJeff Kirsher
766dee1ad47SJeff Kirsher /*
767dee1ad47SJeff Kirsher * Store MAC address from RAR0, clear receive address registers, and
768dee1ad47SJeff Kirsher * clear the multicast table
769dee1ad47SJeff Kirsher */
770dee1ad47SJeff Kirsher hw->mac.ops.init_rx_addrs(hw);
771dee1ad47SJeff Kirsher
772dee1ad47SJeff Kirsher if (phy_status)
773dee1ad47SJeff Kirsher status = phy_status;
774dee1ad47SJeff Kirsher
775dee1ad47SJeff Kirsher return status;
776dee1ad47SJeff Kirsher }
777dee1ad47SJeff Kirsher
778dee1ad47SJeff Kirsher /**
779dee1ad47SJeff Kirsher * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
780dee1ad47SJeff Kirsher * @hw: pointer to hardware struct
781dee1ad47SJeff Kirsher * @rar: receive address register index to associate with a VMDq index
782dee1ad47SJeff Kirsher * @vmdq: VMDq set index
783dee1ad47SJeff Kirsher **/
ixgbe_set_vmdq_82598(struct ixgbe_hw * hw,u32 rar,u32 vmdq)784dee1ad47SJeff Kirsher static s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
785dee1ad47SJeff Kirsher {
786dee1ad47SJeff Kirsher u32 rar_high;
787dee1ad47SJeff Kirsher u32 rar_entries = hw->mac.num_rar_entries;
788dee1ad47SJeff Kirsher
789dee1ad47SJeff Kirsher /* Make sure we are using a valid rar index range */
790dee1ad47SJeff Kirsher if (rar >= rar_entries) {
791dee1ad47SJeff Kirsher hw_dbg(hw, "RAR index %d is out of range.\n", rar);
792*03c5b6d4SJedrzej Jagielski return -EINVAL;
793dee1ad47SJeff Kirsher }
794dee1ad47SJeff Kirsher
795dee1ad47SJeff Kirsher rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
796dee1ad47SJeff Kirsher rar_high &= ~IXGBE_RAH_VIND_MASK;
797dee1ad47SJeff Kirsher rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
798dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
799dee1ad47SJeff Kirsher return 0;
800dee1ad47SJeff Kirsher }
801dee1ad47SJeff Kirsher
802dee1ad47SJeff Kirsher /**
803dee1ad47SJeff Kirsher * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
804dee1ad47SJeff Kirsher * @hw: pointer to hardware struct
805dee1ad47SJeff Kirsher * @rar: receive address register index to associate with a VMDq index
806dee1ad47SJeff Kirsher * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
807dee1ad47SJeff Kirsher **/
ixgbe_clear_vmdq_82598(struct ixgbe_hw * hw,u32 rar,u32 vmdq)808dee1ad47SJeff Kirsher static s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
809dee1ad47SJeff Kirsher {
810dee1ad47SJeff Kirsher u32 rar_high;
811dee1ad47SJeff Kirsher u32 rar_entries = hw->mac.num_rar_entries;
812dee1ad47SJeff Kirsher
813dee1ad47SJeff Kirsher
814dee1ad47SJeff Kirsher /* Make sure we are using a valid rar index range */
815dee1ad47SJeff Kirsher if (rar >= rar_entries) {
816dee1ad47SJeff Kirsher hw_dbg(hw, "RAR index %d is out of range.\n", rar);
817*03c5b6d4SJedrzej Jagielski return -EINVAL;
818dee1ad47SJeff Kirsher }
819dee1ad47SJeff Kirsher
820dee1ad47SJeff Kirsher rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
821dee1ad47SJeff Kirsher if (rar_high & IXGBE_RAH_VIND_MASK) {
822dee1ad47SJeff Kirsher rar_high &= ~IXGBE_RAH_VIND_MASK;
823dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
824dee1ad47SJeff Kirsher }
825dee1ad47SJeff Kirsher
826dee1ad47SJeff Kirsher return 0;
827dee1ad47SJeff Kirsher }
828dee1ad47SJeff Kirsher
829dee1ad47SJeff Kirsher /**
830dee1ad47SJeff Kirsher * ixgbe_set_vfta_82598 - Set VLAN filter table
831dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
832dee1ad47SJeff Kirsher * @vlan: VLAN id to write to VLAN filter
833dee1ad47SJeff Kirsher * @vind: VMDq output index that maps queue to VLAN id in VFTA
834dee1ad47SJeff Kirsher * @vlan_on: boolean flag to turn on/off VLAN in VFTA
835b6488b66SAlexander Duyck * @vlvf_bypass: boolean flag - unused
836dee1ad47SJeff Kirsher *
837dee1ad47SJeff Kirsher * Turn on/off specified VLAN in the VLAN filter table.
838dee1ad47SJeff Kirsher **/
ixgbe_set_vfta_82598(struct ixgbe_hw * hw,u32 vlan,u32 vind,bool vlan_on,bool vlvf_bypass)839dee1ad47SJeff Kirsher static s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
840b6488b66SAlexander Duyck bool vlan_on, bool vlvf_bypass)
841dee1ad47SJeff Kirsher {
842dee1ad47SJeff Kirsher u32 regindex;
843dee1ad47SJeff Kirsher u32 bitindex;
844dee1ad47SJeff Kirsher u32 bits;
845dee1ad47SJeff Kirsher u32 vftabyte;
846dee1ad47SJeff Kirsher
847dee1ad47SJeff Kirsher if (vlan > 4095)
848*03c5b6d4SJedrzej Jagielski return -EINVAL;
849dee1ad47SJeff Kirsher
850dee1ad47SJeff Kirsher /* Determine 32-bit word position in array */
851dee1ad47SJeff Kirsher regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
852dee1ad47SJeff Kirsher
853dee1ad47SJeff Kirsher /* Determine the location of the (VMD) queue index */
854dee1ad47SJeff Kirsher vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
855dee1ad47SJeff Kirsher bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
856dee1ad47SJeff Kirsher
857dee1ad47SJeff Kirsher /* Set the nibble for VMD queue index */
858dee1ad47SJeff Kirsher bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
859dee1ad47SJeff Kirsher bits &= (~(0x0F << bitindex));
860dee1ad47SJeff Kirsher bits |= (vind << bitindex);
861dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
862dee1ad47SJeff Kirsher
863dee1ad47SJeff Kirsher /* Determine the location of the bit for this VLAN id */
864dee1ad47SJeff Kirsher bitindex = vlan & 0x1F; /* lower five bits */
865dee1ad47SJeff Kirsher
866dee1ad47SJeff Kirsher bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
867dee1ad47SJeff Kirsher if (vlan_on)
868dee1ad47SJeff Kirsher /* Turn on this VLAN id */
869b4f47a48SJacob Keller bits |= BIT(bitindex);
870dee1ad47SJeff Kirsher else
871dee1ad47SJeff Kirsher /* Turn off this VLAN id */
872b4f47a48SJacob Keller bits &= ~BIT(bitindex);
873dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
874dee1ad47SJeff Kirsher
875dee1ad47SJeff Kirsher return 0;
876dee1ad47SJeff Kirsher }
877dee1ad47SJeff Kirsher
878dee1ad47SJeff Kirsher /**
879dee1ad47SJeff Kirsher * ixgbe_clear_vfta_82598 - Clear VLAN filter table
880dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
881dee1ad47SJeff Kirsher *
882c2f1e80fSJiaqing Zhao * Clears the VLAN filter table, and the VMDq index associated with the filter
883dee1ad47SJeff Kirsher **/
ixgbe_clear_vfta_82598(struct ixgbe_hw * hw)884dee1ad47SJeff Kirsher static s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
885dee1ad47SJeff Kirsher {
886dee1ad47SJeff Kirsher u32 offset;
887dee1ad47SJeff Kirsher u32 vlanbyte;
888dee1ad47SJeff Kirsher
889dee1ad47SJeff Kirsher for (offset = 0; offset < hw->mac.vft_size; offset++)
890dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
891dee1ad47SJeff Kirsher
892dee1ad47SJeff Kirsher for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
893dee1ad47SJeff Kirsher for (offset = 0; offset < hw->mac.vft_size; offset++)
894dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
895dee1ad47SJeff Kirsher 0);
896dee1ad47SJeff Kirsher
897dee1ad47SJeff Kirsher return 0;
898dee1ad47SJeff Kirsher }
899dee1ad47SJeff Kirsher
900dee1ad47SJeff Kirsher /**
901dee1ad47SJeff Kirsher * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
902dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
903dee1ad47SJeff Kirsher * @reg: analog register to read
904dee1ad47SJeff Kirsher * @val: read value
905dee1ad47SJeff Kirsher *
906dee1ad47SJeff Kirsher * Performs read operation to Atlas analog register specified.
907dee1ad47SJeff Kirsher **/
ixgbe_read_analog_reg8_82598(struct ixgbe_hw * hw,u32 reg,u8 * val)908dee1ad47SJeff Kirsher static s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
909dee1ad47SJeff Kirsher {
910dee1ad47SJeff Kirsher u32 atlas_ctl;
911dee1ad47SJeff Kirsher
912dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
913dee1ad47SJeff Kirsher IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
914dee1ad47SJeff Kirsher IXGBE_WRITE_FLUSH(hw);
915dee1ad47SJeff Kirsher udelay(10);
916dee1ad47SJeff Kirsher atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
917dee1ad47SJeff Kirsher *val = (u8)atlas_ctl;
918dee1ad47SJeff Kirsher
919dee1ad47SJeff Kirsher return 0;
920dee1ad47SJeff Kirsher }
921dee1ad47SJeff Kirsher
922dee1ad47SJeff Kirsher /**
923dee1ad47SJeff Kirsher * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
924dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
925dee1ad47SJeff Kirsher * @reg: atlas register to write
926dee1ad47SJeff Kirsher * @val: value to write
927dee1ad47SJeff Kirsher *
928dee1ad47SJeff Kirsher * Performs write operation to Atlas analog register specified.
929dee1ad47SJeff Kirsher **/
ixgbe_write_analog_reg8_82598(struct ixgbe_hw * hw,u32 reg,u8 val)930dee1ad47SJeff Kirsher static s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
931dee1ad47SJeff Kirsher {
932dee1ad47SJeff Kirsher u32 atlas_ctl;
933dee1ad47SJeff Kirsher
934dee1ad47SJeff Kirsher atlas_ctl = (reg << 8) | val;
935dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
936dee1ad47SJeff Kirsher IXGBE_WRITE_FLUSH(hw);
937dee1ad47SJeff Kirsher udelay(10);
938dee1ad47SJeff Kirsher
939dee1ad47SJeff Kirsher return 0;
940dee1ad47SJeff Kirsher }
941dee1ad47SJeff Kirsher
942dee1ad47SJeff Kirsher /**
94307ce870bSEmil Tantilov * ixgbe_read_i2c_phy_82598 - Reads 8 bit word over I2C interface.
944dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
94507ce870bSEmil Tantilov * @dev_addr: address to read from
94607ce870bSEmil Tantilov * @byte_offset: byte offset to read from dev_addr
947dee1ad47SJeff Kirsher * @eeprom_data: value read
948dee1ad47SJeff Kirsher *
94907ce870bSEmil Tantilov * Performs 8 byte read operation to SFP module's data over I2C interface.
950dee1ad47SJeff Kirsher **/
ixgbe_read_i2c_phy_82598(struct ixgbe_hw * hw,u8 dev_addr,u8 byte_offset,u8 * eeprom_data)95107ce870bSEmil Tantilov static s32 ixgbe_read_i2c_phy_82598(struct ixgbe_hw *hw, u8 dev_addr,
95207ce870bSEmil Tantilov u8 byte_offset, u8 *eeprom_data)
953dee1ad47SJeff Kirsher {
954dee1ad47SJeff Kirsher s32 status = 0;
955dee1ad47SJeff Kirsher u16 sfp_addr = 0;
956dee1ad47SJeff Kirsher u16 sfp_data = 0;
957dee1ad47SJeff Kirsher u16 sfp_stat = 0;
9583dcc2f41SEmil Tantilov u16 gssr;
959dee1ad47SJeff Kirsher u32 i;
960dee1ad47SJeff Kirsher
9613dcc2f41SEmil Tantilov if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
9623dcc2f41SEmil Tantilov gssr = IXGBE_GSSR_PHY1_SM;
9633dcc2f41SEmil Tantilov else
9643dcc2f41SEmil Tantilov gssr = IXGBE_GSSR_PHY0_SM;
9653dcc2f41SEmil Tantilov
9663dcc2f41SEmil Tantilov if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
967*03c5b6d4SJedrzej Jagielski return -EBUSY;
9683dcc2f41SEmil Tantilov
969dee1ad47SJeff Kirsher if (hw->phy.type == ixgbe_phy_nl) {
970dee1ad47SJeff Kirsher /*
971dee1ad47SJeff Kirsher * phy SDA/SCL registers are at addresses 0xC30A to
972dee1ad47SJeff Kirsher * 0xC30D. These registers are used to talk to the SFP+
973dee1ad47SJeff Kirsher * module's EEPROM through the SDA/SCL (I2C) interface.
974dee1ad47SJeff Kirsher */
97507ce870bSEmil Tantilov sfp_addr = (dev_addr << 8) + byte_offset;
976dee1ad47SJeff Kirsher sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
9773dcc2f41SEmil Tantilov hw->phy.ops.write_reg_mdi(hw,
978dee1ad47SJeff Kirsher IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
979dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD,
980dee1ad47SJeff Kirsher sfp_addr);
981dee1ad47SJeff Kirsher
982dee1ad47SJeff Kirsher /* Poll status */
983dee1ad47SJeff Kirsher for (i = 0; i < 100; i++) {
9843dcc2f41SEmil Tantilov hw->phy.ops.read_reg_mdi(hw,
985dee1ad47SJeff Kirsher IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
986dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD,
987dee1ad47SJeff Kirsher &sfp_stat);
988dee1ad47SJeff Kirsher sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
989dee1ad47SJeff Kirsher if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
990dee1ad47SJeff Kirsher break;
991dee1ad47SJeff Kirsher usleep_range(10000, 20000);
992dee1ad47SJeff Kirsher }
993dee1ad47SJeff Kirsher
994dee1ad47SJeff Kirsher if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
995dee1ad47SJeff Kirsher hw_dbg(hw, "EEPROM read did not pass.\n");
996*03c5b6d4SJedrzej Jagielski status = -ENOENT;
997dee1ad47SJeff Kirsher goto out;
998dee1ad47SJeff Kirsher }
999dee1ad47SJeff Kirsher
1000dee1ad47SJeff Kirsher /* Read data */
10013dcc2f41SEmil Tantilov hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1002dee1ad47SJeff Kirsher MDIO_MMD_PMAPMD, &sfp_data);
1003dee1ad47SJeff Kirsher
1004dee1ad47SJeff Kirsher *eeprom_data = (u8)(sfp_data >> 8);
1005dee1ad47SJeff Kirsher } else {
1006*03c5b6d4SJedrzej Jagielski status = -EIO;
1007dee1ad47SJeff Kirsher }
1008dee1ad47SJeff Kirsher
1009dee1ad47SJeff Kirsher out:
10103dcc2f41SEmil Tantilov hw->mac.ops.release_swfw_sync(hw, gssr);
1011dee1ad47SJeff Kirsher return status;
1012dee1ad47SJeff Kirsher }
1013dee1ad47SJeff Kirsher
1014dee1ad47SJeff Kirsher /**
101507ce870bSEmil Tantilov * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
101607ce870bSEmil Tantilov * @hw: pointer to hardware structure
101707ce870bSEmil Tantilov * @byte_offset: EEPROM byte offset to read
101807ce870bSEmil Tantilov * @eeprom_data: value read
101907ce870bSEmil Tantilov *
102007ce870bSEmil Tantilov * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
102107ce870bSEmil Tantilov **/
ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw * hw,u8 byte_offset,u8 * eeprom_data)102207ce870bSEmil Tantilov static s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
102307ce870bSEmil Tantilov u8 *eeprom_data)
102407ce870bSEmil Tantilov {
102507ce870bSEmil Tantilov return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR,
102607ce870bSEmil Tantilov byte_offset, eeprom_data);
102707ce870bSEmil Tantilov }
102807ce870bSEmil Tantilov
102907ce870bSEmil Tantilov /**
103007ce870bSEmil Tantilov * ixgbe_read_i2c_sff8472_82598 - Reads 8 bit word over I2C interface.
103107ce870bSEmil Tantilov * @hw: pointer to hardware structure
103207ce870bSEmil Tantilov * @byte_offset: byte offset at address 0xA2
10335ba643c6STony Nguyen * @sff8472_data: value read
103407ce870bSEmil Tantilov *
103507ce870bSEmil Tantilov * Performs 8 byte read operation to SFP module's SFF-8472 data over I2C
103607ce870bSEmil Tantilov **/
ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw * hw,u8 byte_offset,u8 * sff8472_data)103707ce870bSEmil Tantilov static s32 ixgbe_read_i2c_sff8472_82598(struct ixgbe_hw *hw, u8 byte_offset,
103807ce870bSEmil Tantilov u8 *sff8472_data)
103907ce870bSEmil Tantilov {
104007ce870bSEmil Tantilov return ixgbe_read_i2c_phy_82598(hw, IXGBE_I2C_EEPROM_DEV_ADDR2,
104107ce870bSEmil Tantilov byte_offset, sff8472_data);
104207ce870bSEmil Tantilov }
104307ce870bSEmil Tantilov
104407ce870bSEmil Tantilov /**
1045dee1ad47SJeff Kirsher * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1046dee1ad47SJeff Kirsher * port devices.
1047dee1ad47SJeff Kirsher * @hw: pointer to the HW structure
1048dee1ad47SJeff Kirsher *
1049dee1ad47SJeff Kirsher * Calls common function and corrects issue with some single port devices
1050dee1ad47SJeff Kirsher * that enable LAN1 but not LAN0.
1051dee1ad47SJeff Kirsher **/
ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw * hw)1052dee1ad47SJeff Kirsher static void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1053dee1ad47SJeff Kirsher {
1054dee1ad47SJeff Kirsher struct ixgbe_bus_info *bus = &hw->bus;
1055dee1ad47SJeff Kirsher u16 pci_gen = 0;
1056dee1ad47SJeff Kirsher u16 pci_ctrl2 = 0;
1057dee1ad47SJeff Kirsher
1058dee1ad47SJeff Kirsher ixgbe_set_lan_id_multi_port_pcie(hw);
1059dee1ad47SJeff Kirsher
1060dee1ad47SJeff Kirsher /* check if LAN0 is disabled */
1061dee1ad47SJeff Kirsher hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1062dee1ad47SJeff Kirsher if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1063dee1ad47SJeff Kirsher
1064dee1ad47SJeff Kirsher hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1065dee1ad47SJeff Kirsher
1066dee1ad47SJeff Kirsher /* if LAN0 is completely disabled force function to 0 */
1067dee1ad47SJeff Kirsher if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1068dee1ad47SJeff Kirsher !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1069dee1ad47SJeff Kirsher !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1070dee1ad47SJeff Kirsher
1071dee1ad47SJeff Kirsher bus->func = 0;
1072dee1ad47SJeff Kirsher }
1073dee1ad47SJeff Kirsher }
1074dee1ad47SJeff Kirsher }
1075dee1ad47SJeff Kirsher
1076dee1ad47SJeff Kirsher /**
107744834700SJacob Keller * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1078dee1ad47SJeff Kirsher * @hw: pointer to hardware structure
107944834700SJacob Keller * @num_pb: number of packet buffers to allocate
108044834700SJacob Keller * @headroom: reserve n KB of headroom
108144834700SJacob Keller * @strategy: packet buffer allocation strategy
108244834700SJacob Keller **/
ixgbe_set_rxpba_82598(struct ixgbe_hw * hw,int num_pb,u32 headroom,int strategy)108344834700SJacob Keller static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
108444834700SJacob Keller u32 headroom, int strategy)
1085dee1ad47SJeff Kirsher {
1086dee1ad47SJeff Kirsher u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1087dee1ad47SJeff Kirsher u8 i = 0;
1088dee1ad47SJeff Kirsher
1089dee1ad47SJeff Kirsher if (!num_pb)
1090dee1ad47SJeff Kirsher return;
1091dee1ad47SJeff Kirsher
1092dee1ad47SJeff Kirsher /* Setup Rx packet buffer sizes */
1093dee1ad47SJeff Kirsher switch (strategy) {
1094dee1ad47SJeff Kirsher case PBA_STRATEGY_WEIGHTED:
1095dee1ad47SJeff Kirsher /* Setup the first four at 80KB */
1096dee1ad47SJeff Kirsher rxpktsize = IXGBE_RXPBSIZE_80KB;
1097dee1ad47SJeff Kirsher for (; i < 4; i++)
1098dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1099dee1ad47SJeff Kirsher /* Setup the last four at 48KB...don't re-init i */
1100dee1ad47SJeff Kirsher rxpktsize = IXGBE_RXPBSIZE_48KB;
11015463fce6SJeff Kirsher fallthrough;
1102dee1ad47SJeff Kirsher case PBA_STRATEGY_EQUAL:
1103dee1ad47SJeff Kirsher default:
1104dee1ad47SJeff Kirsher /* Divide the remaining Rx packet buffer evenly among the TCs */
1105dee1ad47SJeff Kirsher for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1106dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1107dee1ad47SJeff Kirsher break;
1108dee1ad47SJeff Kirsher }
1109dee1ad47SJeff Kirsher
1110dee1ad47SJeff Kirsher /* Setup Tx packet buffer sizes */
1111dee1ad47SJeff Kirsher for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1112dee1ad47SJeff Kirsher IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);
1113dee1ad47SJeff Kirsher }
1114dee1ad47SJeff Kirsher
111537689010SMark Rustad static const struct ixgbe_mac_operations mac_ops_82598 = {
1116dee1ad47SJeff Kirsher .init_hw = &ixgbe_init_hw_generic,
1117dee1ad47SJeff Kirsher .reset_hw = &ixgbe_reset_hw_82598,
1118dee1ad47SJeff Kirsher .start_hw = &ixgbe_start_hw_82598,
1119dee1ad47SJeff Kirsher .clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic,
1120dee1ad47SJeff Kirsher .get_media_type = &ixgbe_get_media_type_82598,
1121dee1ad47SJeff Kirsher .enable_rx_dma = &ixgbe_enable_rx_dma_generic,
1122dee1ad47SJeff Kirsher .get_mac_addr = &ixgbe_get_mac_addr_generic,
1123dee1ad47SJeff Kirsher .stop_adapter = &ixgbe_stop_adapter_generic,
1124dee1ad47SJeff Kirsher .get_bus_info = &ixgbe_get_bus_info_generic,
1125dee1ad47SJeff Kirsher .set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598,
1126dee1ad47SJeff Kirsher .read_analog_reg8 = &ixgbe_read_analog_reg8_82598,
1127dee1ad47SJeff Kirsher .write_analog_reg8 = &ixgbe_write_analog_reg8_82598,
1128dee1ad47SJeff Kirsher .setup_link = &ixgbe_setup_mac_link_82598,
1129dee1ad47SJeff Kirsher .set_rxpba = &ixgbe_set_rxpba_82598,
1130dee1ad47SJeff Kirsher .check_link = &ixgbe_check_mac_link_82598,
1131dee1ad47SJeff Kirsher .get_link_capabilities = &ixgbe_get_link_capabilities_82598,
1132dee1ad47SJeff Kirsher .led_on = &ixgbe_led_on_generic,
1133dee1ad47SJeff Kirsher .led_off = &ixgbe_led_off_generic,
1134805cedd6SDon Skidmore .init_led_link_act = ixgbe_init_led_link_act_generic,
1135dee1ad47SJeff Kirsher .blink_led_start = &ixgbe_blink_led_start_generic,
1136dee1ad47SJeff Kirsher .blink_led_stop = &ixgbe_blink_led_stop_generic,
1137dee1ad47SJeff Kirsher .set_rar = &ixgbe_set_rar_generic,
1138dee1ad47SJeff Kirsher .clear_rar = &ixgbe_clear_rar_generic,
1139dee1ad47SJeff Kirsher .set_vmdq = &ixgbe_set_vmdq_82598,
1140dee1ad47SJeff Kirsher .clear_vmdq = &ixgbe_clear_vmdq_82598,
1141dee1ad47SJeff Kirsher .init_rx_addrs = &ixgbe_init_rx_addrs_generic,
1142dee1ad47SJeff Kirsher .update_mc_addr_list = &ixgbe_update_mc_addr_list_generic,
1143dee1ad47SJeff Kirsher .enable_mc = &ixgbe_enable_mc_generic,
1144dee1ad47SJeff Kirsher .disable_mc = &ixgbe_disable_mc_generic,
1145dee1ad47SJeff Kirsher .clear_vfta = &ixgbe_clear_vfta_82598,
1146dee1ad47SJeff Kirsher .set_vfta = &ixgbe_set_vfta_82598,
1147dee1ad47SJeff Kirsher .fc_enable = &ixgbe_fc_enable_82598,
1148afdc71e4SMark Rustad .setup_fc = ixgbe_setup_fc_generic,
11492916500dSDon Skidmore .fc_autoneg = ixgbe_fc_autoneg,
1150dee1ad47SJeff Kirsher .set_fw_drv_ver = NULL,
1151dee1ad47SJeff Kirsher .acquire_swfw_sync = &ixgbe_acquire_swfw_sync,
1152dee1ad47SJeff Kirsher .release_swfw_sync = &ixgbe_release_swfw_sync,
1153dbd15b8fSDon Skidmore .init_swfw_sync = NULL,
11543ca8bc6dSDon Skidmore .get_thermal_sensor_data = NULL,
11553ca8bc6dSDon Skidmore .init_thermal_sensor_thresh = NULL,
1156429d6a3bSDon Skidmore .prot_autoc_read = &prot_autoc_read_generic,
1157429d6a3bSDon Skidmore .prot_autoc_write = &prot_autoc_write_generic,
11581f9ac57cSDon Skidmore .enable_rx = &ixgbe_enable_rx_generic,
11591f9ac57cSDon Skidmore .disable_rx = &ixgbe_disable_rx_generic,
1160dee1ad47SJeff Kirsher };
1161dee1ad47SJeff Kirsher
116237689010SMark Rustad static const struct ixgbe_eeprom_operations eeprom_ops_82598 = {
1163dee1ad47SJeff Kirsher .init_params = &ixgbe_init_eeprom_params_generic,
1164dee1ad47SJeff Kirsher .read = &ixgbe_read_eerd_generic,
11652fa5eef4SEmil Tantilov .write = &ixgbe_write_eeprom_generic,
11662fa5eef4SEmil Tantilov .write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic,
1167dee1ad47SJeff Kirsher .read_buffer = &ixgbe_read_eerd_buffer_generic,
1168dee1ad47SJeff Kirsher .calc_checksum = &ixgbe_calc_eeprom_checksum_generic,
1169dee1ad47SJeff Kirsher .validate_checksum = &ixgbe_validate_eeprom_checksum_generic,
1170dee1ad47SJeff Kirsher .update_checksum = &ixgbe_update_eeprom_checksum_generic,
1171dee1ad47SJeff Kirsher };
1172dee1ad47SJeff Kirsher
117337689010SMark Rustad static const struct ixgbe_phy_operations phy_ops_82598 = {
1174dee1ad47SJeff Kirsher .identify = &ixgbe_identify_phy_generic,
11758f58332bSDon Skidmore .identify_sfp = &ixgbe_identify_module_generic,
1176dee1ad47SJeff Kirsher .init = &ixgbe_init_phy_ops_82598,
1177dee1ad47SJeff Kirsher .reset = &ixgbe_reset_phy_generic,
1178dee1ad47SJeff Kirsher .read_reg = &ixgbe_read_phy_reg_generic,
1179dee1ad47SJeff Kirsher .write_reg = &ixgbe_write_phy_reg_generic,
11803dcc2f41SEmil Tantilov .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
11813dcc2f41SEmil Tantilov .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
1182dee1ad47SJeff Kirsher .setup_link = &ixgbe_setup_phy_link_generic,
1183dee1ad47SJeff Kirsher .setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
118407ce870bSEmil Tantilov .read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598,
1185dee1ad47SJeff Kirsher .read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598,
1186dee1ad47SJeff Kirsher .check_overtemp = &ixgbe_tn_check_overtemp,
1187dee1ad47SJeff Kirsher };
1188dee1ad47SJeff Kirsher
118937689010SMark Rustad const struct ixgbe_info ixgbe_82598_info = {
1190dee1ad47SJeff Kirsher .mac = ixgbe_mac_82598EB,
1191dee1ad47SJeff Kirsher .get_invariants = &ixgbe_get_invariants_82598,
1192dee1ad47SJeff Kirsher .mac_ops = &mac_ops_82598,
1193dee1ad47SJeff Kirsher .eeprom_ops = &eeprom_ops_82598,
1194dee1ad47SJeff Kirsher .phy_ops = &phy_ops_82598,
11959a900ecaSDon Skidmore .mvals = ixgbe_mvals_8259X,
1196dee1ad47SJeff Kirsher };
1197