net/usb/smsc95xx.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4  * Copyright (C) 2007-2008 SMSC
38 /* SCSRs - System Control and Status Registers */
52 #define INT_STS_MAC_RTO_	(0x00040000)	/* MAC Reset Time Out */
55 #define INT_STS_PHY_INT_	(0x00008000)	/* PHY Interrupt */
84 #define HW_CFG_PSEL_		(0x00000004)	/* External PHY Select */
106 #define PM_CTL_PHY_RST_		(0x00000010)	/* PHY Reset */
126 #define AFC_CFG_HI_		(0x00FF0000)	/* Auto Flow Ctrl High Level */
127 #define AFC_CFG_LO_		(0x0000FF00)	/* Auto Flow Ctrl Low Level */
129 #define AFC_CFG_FC_MULT_	(0x00000008)	/* Flow Ctrl on Mcast Frame */
130 #define AFC_CFG_FC_BRD_		(0x00000004)	/* Flow Ctrl on Bcast Frame */
131 #define AFC_CFG_FC_ADD_		(0x00000002)	/* Flow Ctrl on Addr. Decode */
132 #define AFC_CFG_FC_ANY_		(0x00000001)	/* Flow Ctrl on Any Frame */
167 #define	STRAP_STATUS_PWR_SEL_		(0x00000020) /* Device self-powered */
168 #define	STRAP_STATUS_AMDIX_EN_		(0x00000010) /* Auto-MDIX Enabled */
169 #define	STRAP_STATUS_PORT_SWAP_		(0x00000008) /* USBD+/USBD- Swapped */
195 #define INT_EP_CTL_MAC_RTO_	(0x00080000)	/* MAC Reset Time Out */
199 #define INT_EP_CTL_PHY_INT_	(0x00008000)	/* PHY Interrupt */
209 /* MAC CSRs - MAC Control and Status Registers */
210 /* MAC Control Register */
231 /* MAC Address High Register */
234 /* MAC Address Low Register */
285 /* Vendor-specific PHY Definitions (via MII access) */
329 /* PHY Special Control/Status Register */
343 #define INT_ENP_MAC_RTO_		((u32)BIT(18))	/* MAC Reset Time Out */
346 #define INT_ENP_PHY_INT_		((u32)BIT(15))	/* PHY Interrupt */