Lines Matching +full:mac +full:- +full:phy +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0+
3 Intel Pro 1000 for ppcboot/das-u-boot
4 Drivers are port from Intel's Linux driver e1000-4.3.15
11 Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
16 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
60 * Normally U-Boot does not support this anyway. To fix it in this driver,
160 * hw - Struct containing variables accessed by shared code
161 * eecd - EECD's current value
177 * hw - Struct containing variables accessed by shared code
178 * eecd - EECD's current value
194 * hw - Struct containing variables accessed by shared code
195 * data - data to send to the EEPROM
196 * count - number of bits to shift out
208 mask = 0x01 << (count - 1); in e1000_shift_out_ee_bits()
242 * hw - Struct containing variables accessed by shared code
282 * hw - Struct containing variables accessed by shared code
286 struct e1000_eeprom_info *eeprom = &hw->eeprom; in e1000_standby_eeprom()
291 if (eeprom->type == e1000_eeprom_microwire) { in e1000_standby_eeprom()
295 udelay(eeprom->delay_usec); in e1000_standby_eeprom()
301 udelay(eeprom->delay_usec); in e1000_standby_eeprom()
307 udelay(eeprom->delay_usec); in e1000_standby_eeprom()
313 udelay(eeprom->delay_usec); in e1000_standby_eeprom()
314 } else if (eeprom->type == e1000_eeprom_spi) { in e1000_standby_eeprom()
319 udelay(eeprom->delay_usec); in e1000_standby_eeprom()
323 udelay(eeprom->delay_usec); in e1000_standby_eeprom()
330 * hw - Struct containing variables accessed by shared code
338 if (hw->mac_type == e1000_ich8lan) in e1000_is_onboard_nvm_eeprom()
341 if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) { in e1000_is_onboard_nvm_eeprom()
357 * hw - Struct containing variables accessed by shared code
364 struct e1000_eeprom_info *eeprom = &hw->eeprom; in e1000_acquire_eeprom()
370 return -E1000_ERR_SWFW_SYNC; in e1000_acquire_eeprom()
373 if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) { in e1000_acquire_eeprom()
375 if (hw->mac_type > e1000_82544) { in e1000_acquire_eeprom()
389 return -E1000_ERR_EEPROM; in e1000_acquire_eeprom()
396 if (eeprom->type == e1000_eeprom_microwire) { in e1000_acquire_eeprom()
404 } else if (eeprom->type == e1000_eeprom_spi) { in e1000_acquire_eeprom()
419 * hw - Struct containing variables accessed by shared code
423 struct e1000_eeprom_info *eeprom = &hw->eeprom; in e1000_init_eeprom_params()
428 if (hw->mac_type == e1000_igb) in e1000_init_eeprom_params()
435 switch (hw->mac_type) { in e1000_init_eeprom_params()
440 eeprom->type = e1000_eeprom_microwire; in e1000_init_eeprom_params()
441 eeprom->word_size = 64; in e1000_init_eeprom_params()
442 eeprom->opcode_bits = 3; in e1000_init_eeprom_params()
443 eeprom->address_bits = 6; in e1000_init_eeprom_params()
444 eeprom->delay_usec = 50; in e1000_init_eeprom_params()
445 eeprom->use_eerd = false; in e1000_init_eeprom_params()
446 eeprom->use_eewr = false; in e1000_init_eeprom_params()
453 eeprom->type = e1000_eeprom_microwire; in e1000_init_eeprom_params()
454 eeprom->opcode_bits = 3; in e1000_init_eeprom_params()
455 eeprom->delay_usec = 50; in e1000_init_eeprom_params()
457 eeprom->word_size = 256; in e1000_init_eeprom_params()
458 eeprom->address_bits = 8; in e1000_init_eeprom_params()
460 eeprom->word_size = 64; in e1000_init_eeprom_params()
461 eeprom->address_bits = 6; in e1000_init_eeprom_params()
463 eeprom->use_eerd = false; in e1000_init_eeprom_params()
464 eeprom->use_eewr = false; in e1000_init_eeprom_params()
471 eeprom->type = e1000_eeprom_spi; in e1000_init_eeprom_params()
472 eeprom->opcode_bits = 8; in e1000_init_eeprom_params()
473 eeprom->delay_usec = 1; in e1000_init_eeprom_params()
475 eeprom->page_size = 32; in e1000_init_eeprom_params()
476 eeprom->address_bits = 16; in e1000_init_eeprom_params()
478 eeprom->page_size = 8; in e1000_init_eeprom_params()
479 eeprom->address_bits = 8; in e1000_init_eeprom_params()
482 eeprom->type = e1000_eeprom_microwire; in e1000_init_eeprom_params()
483 eeprom->opcode_bits = 3; in e1000_init_eeprom_params()
484 eeprom->delay_usec = 50; in e1000_init_eeprom_params()
486 eeprom->word_size = 256; in e1000_init_eeprom_params()
487 eeprom->address_bits = 8; in e1000_init_eeprom_params()
489 eeprom->word_size = 64; in e1000_init_eeprom_params()
490 eeprom->address_bits = 6; in e1000_init_eeprom_params()
493 eeprom->use_eerd = false; in e1000_init_eeprom_params()
494 eeprom->use_eewr = false; in e1000_init_eeprom_params()
498 eeprom->type = e1000_eeprom_spi; in e1000_init_eeprom_params()
499 eeprom->opcode_bits = 8; in e1000_init_eeprom_params()
500 eeprom->delay_usec = 1; in e1000_init_eeprom_params()
502 eeprom->page_size = 32; in e1000_init_eeprom_params()
503 eeprom->address_bits = 16; in e1000_init_eeprom_params()
505 eeprom->page_size = 8; in e1000_init_eeprom_params()
506 eeprom->address_bits = 8; in e1000_init_eeprom_params()
508 eeprom->use_eerd = false; in e1000_init_eeprom_params()
509 eeprom->use_eewr = false; in e1000_init_eeprom_params()
513 eeprom->type = e1000_eeprom_spi; in e1000_init_eeprom_params()
514 eeprom->opcode_bits = 8; in e1000_init_eeprom_params()
515 eeprom->delay_usec = 1; in e1000_init_eeprom_params()
517 eeprom->page_size = 32; in e1000_init_eeprom_params()
518 eeprom->address_bits = 16; in e1000_init_eeprom_params()
520 eeprom->page_size = 8; in e1000_init_eeprom_params()
521 eeprom->address_bits = 8; in e1000_init_eeprom_params()
524 eeprom->use_eerd = true; in e1000_init_eeprom_params()
525 eeprom->use_eewr = true; in e1000_init_eeprom_params()
527 eeprom->type = e1000_eeprom_flash; in e1000_init_eeprom_params()
528 eeprom->word_size = 2048; in e1000_init_eeprom_params()
537 eeprom->type = e1000_eeprom_spi; in e1000_init_eeprom_params()
538 eeprom->opcode_bits = 8; in e1000_init_eeprom_params()
539 eeprom->delay_usec = 1; in e1000_init_eeprom_params()
541 eeprom->page_size = 32; in e1000_init_eeprom_params()
542 eeprom->address_bits = 16; in e1000_init_eeprom_params()
544 eeprom->page_size = 8; in e1000_init_eeprom_params()
545 eeprom->address_bits = 8; in e1000_init_eeprom_params()
547 eeprom->use_eerd = true; in e1000_init_eeprom_params()
548 eeprom->use_eewr = false; in e1000_init_eeprom_params()
552 eeprom->type = e1000_eeprom_invm; in e1000_init_eeprom_params()
553 eeprom->opcode_bits = 8; in e1000_init_eeprom_params()
554 eeprom->delay_usec = 1; in e1000_init_eeprom_params()
555 eeprom->page_size = 32; in e1000_init_eeprom_params()
556 eeprom->address_bits = 16; in e1000_init_eeprom_params()
557 eeprom->use_eerd = true; in e1000_init_eeprom_params()
558 eeprom->use_eewr = false; in e1000_init_eeprom_params()
564 if (eeprom->type == e1000_eeprom_spi || in e1000_init_eeprom_params()
565 eeprom->type == e1000_eeprom_invm) { in e1000_init_eeprom_params()
570 if (hw->mac_type <= e1000_82547_rev_2) { in e1000_init_eeprom_params()
572 eeprom->word_size = 64; in e1000_init_eeprom_params()
591 eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT); in e1000_init_eeprom_params()
599 * hw - Struct containing variables accessed by shared code
610 if (hw->mac_type == e1000_igb) in e1000_poll_eerd_eewr_done()
615 if (hw->mac_type == e1000_igb) in e1000_poll_eerd_eewr_done()
634 * hw - Struct containing variables accessed by shared code
635 * offset - offset of word in the EEPROM to read
636 * data - word read from the EEPROM
637 * words - number of words to read
652 if (hw->mac_type == e1000_igb) in e1000_read_eeprom_eerd()
662 if (hw->mac_type == e1000_igb) { in e1000_read_eeprom_eerd()
683 if (hw->eeprom.type == e1000_eeprom_spi) { in e1000_release_eeprom()
689 udelay(hw->eeprom.delay_usec); in e1000_release_eeprom()
690 } else if (hw->eeprom.type == e1000_eeprom_microwire) { in e1000_release_eeprom()
693 /* CS on Microwire is active-high */ in e1000_release_eeprom()
702 udelay(hw->eeprom.delay_usec); in e1000_release_eeprom()
708 udelay(hw->eeprom.delay_usec); in e1000_release_eeprom()
712 if (hw->mac_type > e1000_82544) { in e1000_release_eeprom()
723 * hw - Struct containing variables accessed by shared code
741 hw->eeprom.opcode_bits); in e1000_spi_eeprom_ready()
752 /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and in e1000_spi_eeprom_ready()
753 * only 0-5mSec on 5V devices) in e1000_spi_eeprom_ready()
757 return -E1000_ERR_EEPROM; in e1000_spi_eeprom_ready()
766 * hw - Struct containing variables accessed by shared code
767 * offset - offset of word in the EEPROM to read
768 * data - word read from the EEPROM
774 struct e1000_eeprom_info *eeprom = &hw->eeprom; in e1000_read_eeprom()
780 if (eeprom->word_size == 0) in e1000_read_eeprom()
786 if ((offset >= eeprom->word_size) || in e1000_read_eeprom()
787 (words > eeprom->word_size - offset) || in e1000_read_eeprom()
790 "Words = %d, size = %d\n", offset, eeprom->word_size); in e1000_read_eeprom()
791 return -E1000_ERR_EEPROM; in e1000_read_eeprom()
794 /* EEPROM's that don't use EERD to read require us to bit-bang the SPI in e1000_read_eeprom()
799 hw->eeprom.use_eerd == false) { in e1000_read_eeprom()
801 /* Prepare the EEPROM for bit-bang reading */ in e1000_read_eeprom()
803 return -E1000_ERR_EEPROM; in e1000_read_eeprom()
807 if (eeprom->use_eerd == true) in e1000_read_eeprom()
810 /* Set up the SPI or Microwire EEPROM for bit-bang reading. We have in e1000_read_eeprom()
812 if (eeprom->type == e1000_eeprom_spi) { in e1000_read_eeprom()
818 return -E1000_ERR_EEPROM; in e1000_read_eeprom()
825 if ((eeprom->address_bits == 8) && (offset >= 128)) in e1000_read_eeprom()
829 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits); in e1000_read_eeprom()
831 eeprom->address_bits); in e1000_read_eeprom()
835 * overhead of eeprom setup and tear-down. The address in e1000_read_eeprom()
843 } else if (eeprom->type == e1000_eeprom_microwire) { in e1000_read_eeprom()
848 eeprom->opcode_bits); in e1000_read_eeprom()
850 eeprom->address_bits); in e1000_read_eeprom()
853 * the overhead of eeprom setup and tear-down. */ in e1000_read_eeprom()
867 * e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
881 struct e1000_eeprom_info *eeprom = &hw->eeprom; in e1000_write_eeprom_srwr()
889 if ((offset >= eeprom->word_size) || in e1000_write_eeprom_srwr()
890 (words > (eeprom->word_size - offset)) || (words == 0)) { in e1000_write_eeprom_srwr()
892 ret_val = -E1000_ERR_EEPROM; in e1000_write_eeprom_srwr()
923 * e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
929 int32_t ret_val = -E1000_ERR_EEPROM; in e1000_pool_flash_update_done_i210()
945 * e1000_update_flash_i210 - Commit EEPROM to the flash
955 if (ret_val == -E1000_ERR_EEPROM) { in e1000_update_flash_i210()
974 * e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
998 /* Do not use hw->nvm.ops.write, hw->nvm.ops.read in e1000_update_eeprom_checksum_i210()
1012 checksum = (uint16_t)EEPROM_SUM - checksum; in e1000_update_eeprom_checksum_i210()
1025 ret_val = -E1000_ERR_SWFW_SYNC; in e1000_update_eeprom_checksum_i210()
1036 * hw - Struct containing variables accessed by shared code
1052 return -E1000_ERR_EEPROM; in e1000_validate_eeprom_checksum()
1058 return -E1000_ERR_EEPROM; in e1000_validate_eeprom_checksum()
1065 checksum = ((uint16_t)EEPROM_SUM) - checksum; in e1000_validate_eeprom_checksum()
1077 return -E1000_ERR_EEPROM; in e1000_validate_eeprom_checksum()
1082 * Set PHY to class A mode
1084 * 1. Do a PHY soft reset
1085 * 2. Restart auto-negotiation or force link.
1087 * hw - Struct containing variables accessed by shared code
1098 if ((hw->mac_type == e1000_82545_rev_3) && in e1000_set_phy_mode()
1099 (hw->media_type == e1000_media_type_copper)) { in e1000_set_phy_mode()
1116 hw->phy_reset_disable = false; in e1000_set_phy_mode()
1126 * Obtaining software semaphore bit (SMBI) before resetting PHY.
1130 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
1137 int32_t timeout = hw->eeprom.word_size + 1; in e1000_get_software_semaphore()
1142 if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb) in e1000_get_software_semaphore()
1152 timeout--; in e1000_get_software_semaphore()
1156 DEBUGOUT("Driver can't access device - SMBI bit is set.\n"); in e1000_get_software_semaphore()
1157 return -E1000_ERR_RESET; in e1000_get_software_semaphore()
1169 * returns: - None.
1180 if (!hw->eeprom_semaphore_present) in e1000_put_hw_eeprom_semaphore()
1184 if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) { in e1000_put_hw_eeprom_semaphore()
1200 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
1213 if (!hw->eeprom_semaphore_present) in e1000_get_hw_eeprom_semaphore()
1216 if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) { in e1000_get_hw_eeprom_semaphore()
1219 return -E1000_ERR_EEPROM; in e1000_get_hw_eeprom_semaphore()
1223 timeout = hw->eeprom.word_size + 1; in e1000_get_hw_eeprom_semaphore()
1234 timeout--; in e1000_get_hw_eeprom_semaphore()
1240 DEBUGOUT("Driver can't access the Eeprom - " in e1000_get_hw_eeprom_semaphore()
1242 return -E1000_ERR_EEPROM; in e1000_get_hw_eeprom_semaphore()
1248 /* Take ownership of the PHY */
1260 return -E1000_ERR_SWFW_SYNC; in e1000_swfw_sync_acquire()
1270 timeout--; in e1000_swfw_sync_acquire()
1275 return -E1000_ERR_SWFW_SYNC; in e1000_swfw_sync_acquire()
1302 switch (hw->mac_type) { in e1000_is_second_port()
1316 * Reads the adapter's MAC address from the EEPROM
1318 * hw - Struct containing variables accessed by shared code
1319 * enetaddr - buffering where the MAC address will be stored
1332 return -E1000_ERR_EEPROM; in e1000_read_mac_addr_from_eeprom()
1342 * Reads the adapter's MAC address from the RAL/RAH registers
1344 * hw - Struct containing variables accessed by shared code
1345 * enetaddr - buffering where the MAC address will be stored
1354 if (hw->mac_type != e1000_igb) in e1000_read_mac_addr_from_regs()
1355 return -E1000_ERR_MAC_TYPE; in e1000_read_mac_addr_from_regs()
1376 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
1379 * hw - Struct containing variables accessed by shared code
1380 * enetaddr - buffering where the MAC address will be stored
1386 if (hw->mac_type == e1000_igb) { in e1000_read_mac_addr()
1387 /* i210 preloads MAC address into RAL/RAH registers */ in e1000_read_mac_addr()
1406 * hw - Struct containing variables accessed by shared code
1408 * Places the MAC address in receive address register 0 and clears the rest
1422 DEBUGOUT("Programming MAC Address into RAR[0]\n"); in e1000_init_rx_addrs()
1433 DEBUGOUT("Clearing RAR[1-15]\n"); in e1000_init_rx_addrs()
1443 * hw - Struct containing variables accessed by shared code
1455 * Set the mac type member in the hw struct.
1457 * hw - Struct containing variables accessed by shared code
1464 switch (hw->device_id) { in e1000_set_mac_type()
1466 switch (hw->revision_id) { in e1000_set_mac_type()
1468 hw->mac_type = e1000_82542_rev2_0; in e1000_set_mac_type()
1471 hw->mac_type = e1000_82542_rev2_1; in e1000_set_mac_type()
1475 return -E1000_ERR_MAC_TYPE; in e1000_set_mac_type()
1480 hw->mac_type = e1000_82543; in e1000_set_mac_type()
1486 hw->mac_type = e1000_82544; in e1000_set_mac_type()
1493 hw->mac_type = e1000_82540; in e1000_set_mac_type()
1497 hw->mac_type = e1000_82545; in e1000_set_mac_type()
1502 hw->mac_type = e1000_82545_rev_3; in e1000_set_mac_type()
1507 hw->mac_type = e1000_82546; in e1000_set_mac_type()
1515 hw->mac_type = e1000_82546_rev_3; in e1000_set_mac_type()
1520 hw->mac_type = e1000_82541; in e1000_set_mac_type()
1526 hw->mac_type = e1000_82541_rev_2; in e1000_set_mac_type()
1530 hw->mac_type = e1000_82547; in e1000_set_mac_type()
1533 hw->mac_type = e1000_82547_rev_2; in e1000_set_mac_type()
1544 hw->mac_type = e1000_82571; in e1000_set_mac_type()
1550 hw->mac_type = e1000_82572; in e1000_set_mac_type()
1555 hw->mac_type = e1000_82573; in e1000_set_mac_type()
1558 hw->mac_type = e1000_82574; in e1000_set_mac_type()
1564 hw->mac_type = e1000_80003es2lan; in e1000_set_mac_type()
1573 hw->mac_type = e1000_ich8lan; in e1000_set_mac_type()
1583 hw->mac_type = e1000_igb; in e1000_set_mac_type()
1587 return -E1000_ERR_MAC_TYPE; in e1000_set_mac_type()
1595 * hw - Struct containing variables accessed by shared code
1600 uint32_t ctrl; in e1000_reset_hw() local
1609 if (hw->mac_type < e1000_82571) in e1000_reset_hw()
1615 if (hw->mac_type == e1000_82542_rev2_0) { in e1000_reset_hw()
1618 dm_pci_write_config16(hw->pdev, PCI_COMMAND, in e1000_reset_hw()
1619 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); in e1000_reset_hw()
1621 pci_write_config_word(hw->pdev, PCI_COMMAND, in e1000_reset_hw()
1622 hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE); in e1000_reset_hw()
1628 if (hw->mac_type == e1000_igb) in e1000_reset_hw()
1633 * any pending transactions to complete before we hit the MAC with in e1000_reset_hw()
1641 hw->tbi_compatibility_on = false; in e1000_reset_hw()
1648 /* Issue a global reset to the MAC. This will reset the chip's in e1000_reset_hw()
1650 * the current PCI configuration. The global reset bit is self- in e1000_reset_hw()
1653 DEBUGOUT("Issuing a global reset to MAC\n"); in e1000_reset_hw()
1654 ctrl = E1000_READ_REG(hw, CTRL); in e1000_reset_hw()
1656 E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST)); in e1000_reset_hw()
1659 if (hw->mac_type == e1000_igb) { in e1000_reset_hw()
1667 } else if (hw->mac_type < e1000_82540) { in e1000_reset_hw()
1687 if (hw->mac_type == e1000_igb) in e1000_reset_hw()
1695 if (hw->mac_type == e1000_82542_rev2_0) { in e1000_reset_hw()
1697 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); in e1000_reset_hw()
1699 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); in e1000_reset_hw()
1702 if (hw->mac_type != e1000_igb) in e1000_reset_hw()
1708 * Initialize a number of hardware-dependent bits
1712 * This function contains hardware limitation workarounds for PCI-E adapters
1718 if ((hw->mac_type >= e1000_82571) && in e1000_initialize_hardware_bits()
1719 (!hw->initialize_hw_bits_disable)) { in e1000_initialize_hardware_bits()
1720 /* Settings common to all PCI-express silicon */ in e1000_initialize_hardware_bits()
1730 /* Enable not-done TX descriptor counting */ in e1000_initialize_hardware_bits()
1740 switch (hw->mac_type) { in e1000_initialize_hardware_bits()
1745 /* Clear PHY TX compatible mode bits */ in e1000_initialize_hardware_bits()
1771 reg_ctrl = E1000_READ_REG(hw, CTRL); in e1000_initialize_hardware_bits()
1775 E1000_WRITE_REG(hw, CTRL, reg_ctrl); in e1000_initialize_hardware_bits()
1779 if ((hw->media_type == e1000_media_type_fiber) in e1000_initialize_hardware_bits()
1780 || (hw->media_type == in e1000_initialize_hardware_bits()
1797 if ((hw->revision_id < 3) || in e1000_initialize_hardware_bits()
1798 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && in e1000_initialize_hardware_bits()
1799 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M))) in e1000_initialize_hardware_bits()
1833 * hw - Struct containing variables accessed by shared code
1836 * post-reset uninitialized state. Initializes the receive address registers,
1838 * configuration and flow control settings. Clears all on-chip counters. Leaves
1844 uint32_t ctrl; in e1000_init_hw() local
1855 /* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */ in e1000_init_hw()
1856 if ((hw->mac_type == e1000_ich8lan) && in e1000_init_hw()
1857 ((hw->revision_id < 3) || in e1000_init_hw()
1858 ((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) && in e1000_init_hw()
1859 (hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) { in e1000_init_hw()
1876 if (hw->mac_type != e1000_ich8lan) { in e1000_init_hw()
1877 if (hw->mac_type < e1000_82545_rev_3) in e1000_init_hw()
1883 if (hw->mac_type == e1000_82542_rev2_0) { in e1000_init_hw()
1886 dm_pci_write_config16(hw->pdev, PCI_COMMAND, in e1000_init_hw()
1887 hw-> in e1000_init_hw()
1890 pci_write_config_word(hw->pdev, PCI_COMMAND, in e1000_init_hw()
1891 hw-> in e1000_init_hw()
1900 * Address Registers (RARs 0 - 15). in e1000_init_hw()
1905 if (hw->mac_type == e1000_82542_rev2_0) { in e1000_init_hw()
1910 dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); in e1000_init_hw()
1912 pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word); in e1000_init_hw()
1919 if (hw->mac_type == e1000_ich8lan) in e1000_init_hw()
1928 switch (hw->mac_type) { in e1000_init_hw()
1934 /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */ in e1000_init_hw()
1935 if (hw->bus_type == e1000_bus_type_pcix) { in e1000_init_hw()
1937 dm_pci_read_config16(hw->pdev, PCIX_COMMAND_REGISTER, in e1000_init_hw()
1939 dm_pci_read_config16(hw->pdev, PCIX_STATUS_REGISTER_HI, in e1000_init_hw()
1942 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, in e1000_init_hw()
1944 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, in e1000_init_hw()
1959 dm_pci_write_config16(hw->pdev, PCIX_COMMAND_REGISTER, in e1000_init_hw()
1962 pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, in e1000_init_hw()
1970 /* More time needed for PHY to initialize */ in e1000_init_hw()
1971 if (hw->mac_type == e1000_ich8lan) in e1000_init_hw()
1973 if (hw->mac_type == e1000_igb) in e1000_init_hw()
1979 /* Set the transmit descriptor write-back policy */ in e1000_init_hw()
1980 if (hw->mac_type > e1000_82544) { in e1000_init_hw()
1981 ctrl = E1000_READ_REG(hw, TXDCTL); in e1000_init_hw()
1982 ctrl = in e1000_init_hw()
1983 (ctrl & ~E1000_TXDCTL_WTHRESH) | in e1000_init_hw()
1985 E1000_WRITE_REG(hw, TXDCTL, ctrl); in e1000_init_hw()
1989 if (hw->mac_type >= e1000_82571) { in e1000_init_hw()
1990 ctrl = E1000_READ_REG(hw, RXDCTL); in e1000_init_hw()
1991 ctrl = in e1000_init_hw()
1992 (ctrl & ~E1000_RXDCTL_WTHRESH) | in e1000_init_hw()
1994 E1000_WRITE_REG(hw, RXDCTL, ctrl); in e1000_init_hw()
1997 switch (hw->mac_type) { in e1000_init_hw()
2012 /* Configure Transmit Inter-Packet Gap */ in e1000_init_hw()
2025 ctrl = E1000_READ_REG(hw, TXDCTL1); in e1000_init_hw()
2026 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) in e1000_init_hw()
2028 E1000_WRITE_REG(hw, TXDCTL1, ctrl); in e1000_init_hw()
2039 if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER || in e1000_init_hw()
2040 hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) { in e1000_init_hw()
2054 * hw - Struct containing variables accessed by shared code
2056 * Determines which flow control settings to use. Calls the apropriate media-
2073 /* In the case of the phy reset being blocked, we already have a link. in e1000_setup_link()
2082 * disabling auto-negotiation, and the direction of the in e1000_setup_link()
2083 * SW defined pins. If there is no SW over-ride of the flow in e1000_setup_link()
2084 * control setting, then the variable hw->fc will in e1000_setup_link()
2090 return -E1000_ERR_EEPROM; in e1000_setup_link()
2093 if (hw->fc == e1000_fc_default) { in e1000_setup_link()
2094 switch (hw->mac_type) { in e1000_setup_link()
2099 hw->fc = e1000_fc_full; in e1000_setup_link()
2107 return -E1000_ERR_EEPROM; in e1000_setup_link()
2110 hw->fc = e1000_fc_none; in e1000_setup_link()
2113 hw->fc = e1000_fc_tx_pause; in e1000_setup_link()
2116 hw->fc = e1000_fc_full; in e1000_setup_link()
2125 if (hw->mac_type == e1000_82542_rev2_0) in e1000_setup_link()
2126 hw->fc &= (~e1000_fc_tx_pause); in e1000_setup_link()
2128 if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1)) in e1000_setup_link()
2129 hw->fc &= (~e1000_fc_rx_pause); in e1000_setup_link()
2131 hw->original_fc = hw->fc; in e1000_setup_link()
2133 DEBUGOUT("After fix-ups FlowControl is now = %x\n", hw->fc); in e1000_setup_link()
2143 if (hw->mac_type == e1000_82543) { in e1000_setup_link()
2151 ret_val = (hw->media_type == e1000_media_type_fiber) ? in e1000_setup_link()
2166 if (hw->mac_type != e1000_ich8lan) { in e1000_setup_link()
2172 E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time); in e1000_setup_link()
2180 if (!(hw->fc & e1000_fc_tx_pause)) { in e1000_setup_link()
2187 if (hw->fc_send_xon) { in e1000_setup_link()
2189 (hw->fc_low_water | E1000_FCRTL_XONE)); in e1000_setup_link()
2190 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); in e1000_setup_link()
2192 E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water); in e1000_setup_link()
2193 E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water); in e1000_setup_link()
2202 * hw - Struct containing variables accessed by shared code
2211 uint32_t ctrl; in e1000_setup_fiber_link() local
2219 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be in e1000_setup_fiber_link()
2223 ctrl = E1000_READ_REG(hw, CTRL); in e1000_setup_fiber_link()
2224 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) in e1000_setup_fiber_link()
2229 printf("signal for %s is %x (ctrl %08x)!!!!\n", hw->name, signal, in e1000_setup_fiber_link()
2230 ctrl); in e1000_setup_fiber_link()
2232 ctrl &= ~(E1000_CTRL_LRST); in e1000_setup_fiber_link()
2237 * the device accordingly. If auto-negotiation is enabled, then software in e1000_setup_fiber_link()
2239 * Config Word Register (TXCW) and re-start auto-negotiation. However, if in e1000_setup_fiber_link()
2240 * auto-negotiation is disabled, then software will have to manually in e1000_setup_fiber_link()
2241 * configure the two flow control enable bits in the CTRL register. in e1000_setup_fiber_link()
2251 switch (hw->fc) { in e1000_setup_fiber_link()
2253 /* Flow control is completely disabled by a software over-ride. */ in e1000_setup_fiber_link()
2258 * software over-ride. Since there really isn't a way to advertise in e1000_setup_fiber_link()
2267 * software over-ride. in e1000_setup_fiber_link()
2272 /* Flow control (both RX and TX) is enabled by a software over-ride. */ in e1000_setup_fiber_link()
2277 return -E1000_ERR_CONFIG; in e1000_setup_fiber_link()
2281 /* Since auto-negotiation is enabled, take the link out of reset (the link in e1000_setup_fiber_link()
2283 * restart auto-negotiation. If auto-neogtiation is successful then the in e1000_setup_fiber_link()
2284 * link-up status bit will be set and the flow control enable bits (RFCE in e1000_setup_fiber_link()
2287 DEBUGOUT("Auto-negotiation enabled (%#x)\n", txcw); in e1000_setup_fiber_link()
2290 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_setup_fiber_link()
2293 hw->txcw = txcw; in e1000_setup_fiber_link()
2296 /* If we have a signal (the cable is plugged in) then poll for a "Link-Up" in e1000_setup_fiber_link()
2297 * indication in the Device Status Register. Time-out if a link isn't in e1000_setup_fiber_link()
2298 * seen in 500 milliseconds seconds (Auto-negotiation should complete in in e1000_setup_fiber_link()
2301 if ((E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) { in e1000_setup_fiber_link()
2313 * non-autonegotiating link partners. in e1000_setup_fiber_link()
2315 DEBUGOUT("Never got a valid link from auto-neg!!!\n"); in e1000_setup_fiber_link()
2316 hw->autoneg_failed = 1; in e1000_setup_fiber_link()
2322 hw->autoneg_failed = 0; in e1000_setup_fiber_link()
2324 hw->autoneg_failed = 0; in e1000_setup_fiber_link()
2329 return -E1000_ERR_NOLINK; in e1000_setup_fiber_link()
2335 * Make sure we have a valid PHY and change PHY mode before link setup.
2337 * hw - Struct containing variables accessed by shared code
2342 uint32_t ctrl; in e1000_copper_link_preconfig() local
2348 ctrl = E1000_READ_REG(hw, CTRL); in e1000_copper_link_preconfig()
2349 /* With 82543, we need to force speed and duplex on the MAC equal to what in e1000_copper_link_preconfig()
2350 * the PHY speed and duplex configuration is. In addition, we need to in e1000_copper_link_preconfig()
2351 * perform a hardware reset on the PHY to take it out of reset. in e1000_copper_link_preconfig()
2353 if (hw->mac_type > e1000_82543) { in e1000_copper_link_preconfig()
2354 ctrl |= E1000_CTRL_SLU; in e1000_copper_link_preconfig()
2355 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); in e1000_copper_link_preconfig()
2356 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_copper_link_preconfig()
2358 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX in e1000_copper_link_preconfig()
2360 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_copper_link_preconfig()
2366 /* Make sure we have a valid PHY */ in e1000_copper_link_preconfig()
2369 DEBUGOUT("Error, did not detect valid phy.\n"); in e1000_copper_link_preconfig()
2372 DEBUGOUT("Phy ID = %x\n", hw->phy_id); in e1000_copper_link_preconfig()
2374 /* Set PHY to class A mode (if necessary) */ in e1000_copper_link_preconfig()
2378 if ((hw->mac_type == e1000_82545_rev_3) || in e1000_copper_link_preconfig()
2379 (hw->mac_type == e1000_82546_rev_3)) { in e1000_copper_link_preconfig()
2387 if (hw->mac_type <= e1000_82543 || in e1000_copper_link_preconfig()
2388 hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 || in e1000_copper_link_preconfig()
2389 hw->mac_type == e1000_82541_rev_2 in e1000_copper_link_preconfig()
2390 || hw->mac_type == e1000_82547_rev_2) in e1000_copper_link_preconfig()
2391 hw->phy_reset_disable = false; in e1000_copper_link_preconfig()
2403 * active - true to enable lplu false to disable lplu.
2405 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2418 if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2 in e1000_set_d3_lplu_state()
2419 && hw->phy_type != e1000_phy_igp_3) in e1000_set_d3_lplu_state()
2425 if (hw->mac_type == e1000_82541_rev_2 in e1000_set_d3_lplu_state()
2426 || hw->mac_type == e1000_82547_rev_2) { in e1000_set_d3_lplu_state()
2431 } else if (hw->mac_type == e1000_ich8lan) { in e1000_set_d3_lplu_state()
2432 /* MAC writes into PHY register based on the state transition in e1000_set_d3_lplu_state()
2433 * and start auto-negotiation. SW driver can overwrite the in e1000_set_d3_lplu_state()
2434 * settings in CSR PHY power control E1000_PHY_CTRL register. */ in e1000_set_d3_lplu_state()
2444 if (hw->mac_type == e1000_82541_rev_2 || in e1000_set_d3_lplu_state()
2445 hw->mac_type == e1000_82547_rev_2) { in e1000_set_d3_lplu_state()
2452 if (hw->mac_type == e1000_ich8lan) { in e1000_set_d3_lplu_state()
2468 if (hw->smart_speed == e1000_smart_speed_on) { in e1000_set_d3_lplu_state()
2479 } else if (hw->smart_speed == e1000_smart_speed_off) { in e1000_set_d3_lplu_state()
2492 } else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) in e1000_set_d3_lplu_state()
2493 || (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL) || in e1000_set_d3_lplu_state()
2494 (hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) { in e1000_set_d3_lplu_state()
2496 if (hw->mac_type == e1000_82541_rev_2 || in e1000_set_d3_lplu_state()
2497 hw->mac_type == e1000_82547_rev_2) { in e1000_set_d3_lplu_state()
2504 if (hw->mac_type == e1000_ich8lan) { in e1000_set_d3_lplu_state()
2538 * active - true to enable lplu false to disable lplu.
2540 * returns: - E1000_ERR_PHY if fail to read/write the PHY
2553 if (hw->mac_type <= e1000_82547_rev_2) in e1000_set_d0_lplu_state()
2556 if (hw->mac_type == e1000_ich8lan) { in e1000_set_d0_lplu_state()
2558 } else if (hw->mac_type == e1000_igb) { in e1000_set_d0_lplu_state()
2568 if (hw->mac_type == e1000_ich8lan) { in e1000_set_d0_lplu_state()
2571 } else if (hw->mac_type == e1000_igb) { in e1000_set_d0_lplu_state()
2582 if (hw->mac_type == e1000_igb) in e1000_set_d0_lplu_state()
2589 if (hw->smart_speed == e1000_smart_speed_on) { in e1000_set_d0_lplu_state()
2600 } else if (hw->smart_speed == e1000_smart_speed_off) { in e1000_set_d0_lplu_state()
2616 if (hw->mac_type == e1000_ich8lan) { in e1000_set_d0_lplu_state()
2619 } else if (hw->mac_type == e1000_igb) { in e1000_set_d0_lplu_state()
2630 if (hw->mac_type == e1000_igb) in e1000_set_d0_lplu_state()
2652 * hw - Struct containing variables accessed by shared code
2663 if (hw->phy_reset_disable) in e1000_copper_link_igp_setup()
2668 DEBUGOUT("Error Resetting the PHY\n"); in e1000_copper_link_igp_setup()
2672 /* Wait 15ms for MAC to configure PHY from eeprom settings */ in e1000_copper_link_igp_setup()
2674 if (hw->mac_type != e1000_ich8lan) { in e1000_copper_link_igp_setup()
2675 /* Configure activity LED after PHY reset */ in e1000_copper_link_igp_setup()
2683 if (hw->phy_type == e1000_phy_igp) { in e1000_copper_link_igp_setup()
2698 /* Configure mdi-mdix settings */ in e1000_copper_link_igp_setup()
2703 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { in e1000_copper_link_igp_setup()
2704 hw->dsp_config_state = e1000_dsp_config_disabled; in e1000_copper_link_igp_setup()
2705 /* Force MDI for earlier revs of the IGP PHY */ in e1000_copper_link_igp_setup()
2708 hw->mdix = 1; in e1000_copper_link_igp_setup()
2711 hw->dsp_config_state = e1000_dsp_config_enabled; in e1000_copper_link_igp_setup()
2714 switch (hw->mdix) { in e1000_copper_link_igp_setup()
2731 /* set auto-master slave resolution settings */ in e1000_copper_link_igp_setup()
2732 if (hw->autoneg) { in e1000_copper_link_igp_setup()
2733 e1000_ms_type phy_ms_setting = hw->master_slave; in e1000_copper_link_igp_setup()
2735 if (hw->ffe_config_state == e1000_ffe_config_active) in e1000_copper_link_igp_setup()
2736 hw->ffe_config_state = e1000_ffe_config_enabled; in e1000_copper_link_igp_setup()
2738 if (hw->dsp_config_state == e1000_dsp_config_activated) in e1000_copper_link_igp_setup()
2739 hw->dsp_config_state = e1000_dsp_config_enabled; in e1000_copper_link_igp_setup()
2744 if (hw->autoneg_advertised == ADVERTISE_1000_FULL) { in e1000_copper_link_igp_setup()
2772 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ? in e1000_copper_link_igp_setup()
2802 * returns - true when the mode is IAMT or false.
2812 if (hw->mac_type == e1000_ich8lan) { in e1000_check_mng_mode()
2834 return -E1000_ERR_SWFW_SYNC; in e1000_write_kmrn_reg()
2856 return -E1000_ERR_SWFW_SYNC; in e1000_read_kmrn_reg()
2875 * hw - Struct containing variables accessed by shared code
2886 if (!hw->phy_reset_disable) { in e1000_copper_link_ggp_setup()
2887 /* Enable CRS on TX for half-duplex operation. */ in e1000_copper_link_ggp_setup()
2894 /* Use 25MHz for both link down and 1000BASE-T for Tx clock */ in e1000_copper_link_ggp_setup()
2903 * MDI/MDI-X = 0 (default) in e1000_copper_link_ggp_setup()
2904 * 0 - Auto for all speeds in e1000_copper_link_ggp_setup()
2905 * 1 - MDI mode in e1000_copper_link_ggp_setup()
2906 * 2 - MDI-X mode in e1000_copper_link_ggp_setup()
2907 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) in e1000_copper_link_ggp_setup()
2916 switch (hw->mdix) { in e1000_copper_link_ggp_setup()
2932 * 0 - Disabled in e1000_copper_link_ggp_setup()
2933 * 1 - Enabled in e1000_copper_link_ggp_setup()
2942 /* SW Reset the PHY so all changes take effect */ in e1000_copper_link_ggp_setup()
2945 DEBUGOUT("Error Resetting the PHY\n"); in e1000_copper_link_ggp_setup()
2950 if (hw->mac_type == e1000_80003es2lan) { in e1000_copper_link_ggp_setup()
2985 /* Enable Electrical Idle on the PHY */ in e1000_copper_link_ggp_setup()
3005 /* Workaround: Disable padding in Kumeran interface in the MAC in e1000_copper_link_ggp_setup()
3006 * and in the PHY to avoid CRC errors. in e1000_copper_link_ggp_setup()
3024 * hw - Struct containing variables accessed by shared code
3034 if (hw->phy_reset_disable) in e1000_copper_link_mgp_setup()
3037 /* Enable CRS on TX. This must be set for half-duplex operation. */ in e1000_copper_link_mgp_setup()
3045 * MDI/MDI-X = 0 (default) in e1000_copper_link_mgp_setup()
3046 * 0 - Auto for all speeds in e1000_copper_link_mgp_setup()
3047 * 1 - MDI mode in e1000_copper_link_mgp_setup()
3048 * 2 - MDI-X mode in e1000_copper_link_mgp_setup()
3049 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes) in e1000_copper_link_mgp_setup()
3053 switch (hw->mdix) { in e1000_copper_link_mgp_setup()
3072 * 0 - Disabled in e1000_copper_link_mgp_setup()
3073 * 1 - Enabled in e1000_copper_link_mgp_setup()
3080 if (hw->phy_revision < M88E1011_I_REV_4) { in e1000_copper_link_mgp_setup()
3081 /* Force TX_CLK in the Extended PHY Specific Control Register in e1000_copper_link_mgp_setup()
3091 if ((hw->phy_revision == E1000_REVISION_2) && in e1000_copper_link_mgp_setup()
3092 (hw->phy_id == M88E1111_I_PHY_ID)) { in e1000_copper_link_mgp_setup()
3093 /* Vidalia Phy, set the downshift counter to 5x */ in e1000_copper_link_mgp_setup()
3113 /* SW Reset the PHY so all changes take effect */ in e1000_copper_link_mgp_setup()
3116 DEBUGOUT("Error Resetting the PHY\n"); in e1000_copper_link_mgp_setup()
3124 * Setup auto-negotiation and flow control advertisements,
3125 * and then perform auto-negotiation.
3127 * hw - Struct containing variables accessed by shared code
3137 /* Perform some bounds checking on the hw->autoneg_advertised in e1000_copper_link_autoneg()
3140 hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_copper_link_autoneg()
3145 if (hw->autoneg_advertised == 0) in e1000_copper_link_autoneg()
3146 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT; in e1000_copper_link_autoneg()
3148 /* IFE phy only supports 10/100 */ in e1000_copper_link_autoneg()
3149 if (hw->phy_type == e1000_phy_ife) in e1000_copper_link_autoneg()
3150 hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL; in e1000_copper_link_autoneg()
3152 DEBUGOUT("Reconfiguring auto-neg advertisement params\n"); in e1000_copper_link_autoneg()
3155 DEBUGOUT("Error Setting up Auto-Negotiation\n"); in e1000_copper_link_autoneg()
3158 DEBUGOUT("Restarting Auto-Neg\n"); in e1000_copper_link_autoneg()
3160 /* Restart auto-negotiation by setting the Auto Neg Enable bit and in e1000_copper_link_autoneg()
3161 * the Auto Neg Restart bit in the PHY control register. in e1000_copper_link_autoneg()
3172 /* Does the user want to wait for Auto-Neg to complete here, or in e1000_copper_link_autoneg()
3179 if (hw->wait_autoneg_complete) { in e1000_copper_link_autoneg()
3188 hw->get_link_status = true; in e1000_copper_link_autoneg()
3194 * Config the MAC and the PHY after link is up.
3195 * 1) Set up the MAC to the current PHY speed/duplex
3199 * 2) Set up flow control on the MAC to that established with
3201 * 3) Config DSP to improve Gigabit link quality for some PHY revisions.
3203 * hw - Struct containing variables accessed by shared code
3211 if (hw->mac_type >= e1000_82544) { in e1000_copper_link_postconfig()
3216 DEBUGOUT("Error configuring MAC to PHY settings\n"); in e1000_copper_link_postconfig()
3229 * Detects which PHY is present and setup the speed and duplex
3231 * hw - Struct containing variables accessed by shared code
3243 switch (hw->mac_type) { in e1000_setup_copper_link()
3246 /* Set the mac to wait the maximum time between each in e1000_setup_copper_link()
3248 * polling the phy; this fixes erroneous timeouts at 10Mbps. */ in e1000_setup_copper_link()
3266 /* Check if it is a valid PHY and set PHY mode if necessary. */ in e1000_setup_copper_link()
3270 switch (hw->mac_type) { in e1000_setup_copper_link()
3272 /* Kumeran registers are written-only */ in e1000_setup_copper_link()
3285 if (hw->phy_type == e1000_phy_igp || in e1000_setup_copper_link()
3286 hw->phy_type == e1000_phy_igp_3 || in e1000_setup_copper_link()
3287 hw->phy_type == e1000_phy_igp_2) { in e1000_setup_copper_link()
3291 } else if (hw->phy_type == e1000_phy_m88 || in e1000_setup_copper_link()
3292 hw->phy_type == e1000_phy_igb) { in e1000_setup_copper_link()
3296 } else if (hw->phy_type == e1000_phy_gg82563) { in e1000_setup_copper_link()
3321 /* Config the MAC and PHY after link is up */ in e1000_setup_copper_link()
3337 * Configures PHY autoneg and flow control advertisement settings
3339 * hw - Struct containing variables accessed by shared code
3350 /* Read the MII Auto-Neg Advertisement Register (Address 4). */ in e1000_phy_setup_autoneg()
3355 if (hw->phy_type != e1000_phy_ife) { in e1000_phy_setup_autoneg()
3356 /* Read the MII 1000Base-T Control Register (Address 9). */ in e1000_phy_setup_autoneg()
3365 * the appropriate PHY registers. First we will parse for in e1000_phy_setup_autoneg()
3371 /* First we clear all the 10/100 mb speed bits in the Auto-Neg in e1000_phy_setup_autoneg()
3373 * the 1000Base-T Control Register (Address 9). in e1000_phy_setup_autoneg()
3378 DEBUGOUT("autoneg_advertised %x\n", hw->autoneg_advertised); in e1000_phy_setup_autoneg()
3381 if (hw->autoneg_advertised & ADVERTISE_10_HALF) { in e1000_phy_setup_autoneg()
3387 if (hw->autoneg_advertised & ADVERTISE_10_FULL) { in e1000_phy_setup_autoneg()
3393 if (hw->autoneg_advertised & ADVERTISE_100_HALF) { in e1000_phy_setup_autoneg()
3399 if (hw->autoneg_advertised & ADVERTISE_100_FULL) { in e1000_phy_setup_autoneg()
3404 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */ in e1000_phy_setup_autoneg()
3405 if (hw->autoneg_advertised & ADVERTISE_1000_HALF) { in e1000_phy_setup_autoneg()
3411 if (hw->autoneg_advertised & ADVERTISE_1000_FULL) { in e1000_phy_setup_autoneg()
3417 * setup the PHY advertisement registers accordingly. If in e1000_phy_setup_autoneg()
3418 * auto-negotiation is enabled, then software will have to set the in e1000_phy_setup_autoneg()
3419 * "PAUSE" bits to the correct value in the Auto-Negotiation in e1000_phy_setup_autoneg()
3420 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation. in e1000_phy_setup_autoneg()
3432 switch (hw->fc) { in e1000_phy_setup_autoneg()
3435 * software over-ride. in e1000_phy_setup_autoneg()
3441 * disabled, by a software over-ride. in e1000_phy_setup_autoneg()
3453 * disabled, by a software over-ride. in e1000_phy_setup_autoneg()
3460 * over-ride. in e1000_phy_setup_autoneg()
3466 return -E1000_ERR_CONFIG; in e1000_phy_setup_autoneg()
3473 DEBUGOUT("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg); in e1000_phy_setup_autoneg()
3475 if (hw->phy_type != e1000_phy_ife) { in e1000_phy_setup_autoneg()
3488 * hw - Struct containing variables accessed by shared code
3500 if (hw->mac_type < e1000_82543) in e1000_config_collision_dist()
3515 * Sets MAC speed and duplex settings to reflect the those in the PHY
3517 * hw - Struct containing variables accessed by shared code
3518 * mii_reg - data to write to the MII control register
3520 * The contents of the PHY register containing the needed information need to
3526 uint32_t ctrl; in e1000_config_mac_to_phy() local
3534 ctrl = E1000_READ_REG(hw, CTRL); in e1000_config_mac_to_phy()
3535 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); in e1000_config_mac_to_phy()
3536 ctrl &= ~(E1000_CTRL_ILOS); in e1000_config_mac_to_phy()
3537 ctrl |= (E1000_CTRL_SPD_SEL); in e1000_config_mac_to_phy()
3543 DEBUGOUT("PHY Read Error\n"); in e1000_config_mac_to_phy()
3544 return -E1000_ERR_PHY; in e1000_config_mac_to_phy()
3547 ctrl |= E1000_CTRL_FD; in e1000_config_mac_to_phy()
3549 ctrl &= ~E1000_CTRL_FD; in e1000_config_mac_to_phy()
3557 ctrl |= E1000_CTRL_SPD_1000; in e1000_config_mac_to_phy()
3559 ctrl |= E1000_CTRL_SPD_100; in e1000_config_mac_to_phy()
3561 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_config_mac_to_phy()
3566 * Forces the MAC's flow control settings.
3568 * hw - Struct containing variables accessed by shared code
3572 * software when a Copper PHY is used because autonegotiation is managed
3573 * by the PHY rather than the MAC. Software must also configure these
3579 uint32_t ctrl; in e1000_force_mac_fc() local
3584 ctrl = E1000_READ_REG(hw, CTRL); in e1000_force_mac_fc()
3586 /* Because we didn't get link via the internal auto-negotiation in e1000_force_mac_fc()
3587 * mechanism (we either forced link or we got link via PHY in e1000_force_mac_fc()
3588 * auto-neg), we have to manually enable/disable transmit an in e1000_force_mac_fc()
3592 * according to the "hw->fc" parameter. in e1000_force_mac_fc()
3604 switch (hw->fc) { in e1000_force_mac_fc()
3606 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE)); in e1000_force_mac_fc()
3609 ctrl &= (~E1000_CTRL_TFCE); in e1000_force_mac_fc()
3610 ctrl |= E1000_CTRL_RFCE; in e1000_force_mac_fc()
3613 ctrl &= (~E1000_CTRL_RFCE); in e1000_force_mac_fc()
3614 ctrl |= E1000_CTRL_TFCE; in e1000_force_mac_fc()
3617 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE); in e1000_force_mac_fc()
3621 return -E1000_ERR_CONFIG; in e1000_force_mac_fc()
3625 if (hw->mac_type == e1000_82542_rev2_0) in e1000_force_mac_fc()
3626 ctrl &= (~E1000_CTRL_TFCE); in e1000_force_mac_fc()
3628 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_force_mac_fc()
3635 * hw - Struct containing variables accessed by shared code
3638 * Forces MAC flow control settings if link was forced. When in MII/GMII mode
3639 * and autonegotiation is enabled, the MAC flow control settings will be set
3640 * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
3655 /* Check for the case where we have fiber media and auto-neg failed in e1000_config_fc_after_link_up()
3657 * configuration of the MAC to match the "fc" parameter. in e1000_config_fc_after_link_up()
3659 if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) in e1000_config_fc_after_link_up()
3660 || ((hw->media_type == e1000_media_type_internal_serdes) in e1000_config_fc_after_link_up()
3661 && (hw->autoneg_failed)) in e1000_config_fc_after_link_up()
3662 || ((hw->media_type == e1000_media_type_copper) in e1000_config_fc_after_link_up()
3663 && (!hw->autoneg))) { in e1000_config_fc_after_link_up()
3671 /* Check for the case where we have copper media and auto-neg is in e1000_config_fc_after_link_up()
3672 * enabled. In this case, we need to check and see if Auto-Neg in e1000_config_fc_after_link_up()
3673 * has completed, and if so, how the PHY and link partner has in e1000_config_fc_after_link_up()
3676 if (hw->media_type == e1000_media_type_copper) { in e1000_config_fc_after_link_up()
3682 DEBUGOUT("PHY Read Error\n"); in e1000_config_fc_after_link_up()
3683 return -E1000_ERR_PHY; in e1000_config_fc_after_link_up()
3686 DEBUGOUT("PHY Read Error\n"); in e1000_config_fc_after_link_up()
3687 return -E1000_ERR_PHY; in e1000_config_fc_after_link_up()
3699 DEBUGOUT("PHY Read Error\n"); in e1000_config_fc_after_link_up()
3700 return -E1000_ERR_PHY; in e1000_config_fc_after_link_up()
3705 DEBUGOUT("PHY Read Error\n"); in e1000_config_fc_after_link_up()
3706 return -E1000_ERR_PHY; in e1000_config_fc_after_link_up()
3712 * for both the PHY and the link partner. The following in e1000_config_fc_after_link_up()
3720 *-------|---------|-------|---------|-------------------- in e1000_config_fc_after_link_up()
3739 *-------|---------|-------|---------|-------------------- in e1000_config_fc_after_link_up()
3751 if (hw->original_fc == e1000_fc_full) { in e1000_config_fc_after_link_up()
3752 hw->fc = e1000_fc_full; in e1000_config_fc_after_link_up()
3755 hw->fc = e1000_fc_rx_pause; in e1000_config_fc_after_link_up()
3764 *-------|---------|-------|---------|-------------------- in e1000_config_fc_after_link_up()
3773 hw->fc = e1000_fc_tx_pause; in e1000_config_fc_after_link_up()
3781 *-------|---------|-------|---------|-------------------- in e1000_config_fc_after_link_up()
3790 hw->fc = e1000_fc_rx_pause; in e1000_config_fc_after_link_up()
3814 else if (hw->original_fc == e1000_fc_none || in e1000_config_fc_after_link_up()
3815 hw->original_fc == e1000_fc_tx_pause) { in e1000_config_fc_after_link_up()
3816 hw->fc = e1000_fc_none; in e1000_config_fc_after_link_up()
3819 hw->fc = e1000_fc_rx_pause; in e1000_config_fc_after_link_up()
3824 /* Now we need to do one last check... If we auto- in e1000_config_fc_after_link_up()
3831 hw->fc = e1000_fc_none; in e1000_config_fc_after_link_up()
3833 /* Now we call a subroutine to actually force the MAC in e1000_config_fc_after_link_up()
3844 ("Copper PHY and Auto Neg has not completed.\r\n"); in e1000_config_fc_after_link_up()
3853 * hw - Struct containing variables accessed by shared code
3861 uint32_t ctrl; in e1000_check_for_link() local
3871 /* On adapters with a MAC newer that 82544, SW Defineable pin 1 will be in e1000_check_for_link()
3875 ctrl = E1000_READ_REG(hw, CTRL); in e1000_check_for_link()
3876 if ((hw->mac_type > e1000_82544) && !(ctrl & E1000_CTRL_ILOS)) in e1000_check_for_link()
3883 DEBUGOUT("ctrl: %#08x status %#08x rxcw %#08x\n", ctrl, status, rxcw); in e1000_check_for_link()
3885 /* If we have a copper PHY then we only want to go out to the PHY in e1000_check_for_link()
3886 * registers to see if Auto-Neg has completed and/or if our link in e1000_check_for_link()
3891 if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) { in e1000_check_for_link()
3894 * of the PHY. in e1000_check_for_link()
3898 DEBUGOUT("PHY Read Error\n"); in e1000_check_for_link()
3899 return -E1000_ERR_PHY; in e1000_check_for_link()
3902 DEBUGOUT("PHY Read Error\n"); in e1000_check_for_link()
3903 return -E1000_ERR_PHY; in e1000_check_for_link()
3907 hw->get_link_status = false; in e1000_check_for_link()
3910 return -E1000_ERR_NOLINK; in e1000_check_for_link()
3913 /* We have a M88E1000 PHY and Auto-Neg is enabled. If we in e1000_check_for_link()
3915 * Speed Detection takes care of MAC speed/duplex in e1000_check_for_link()
3917 * Distance in the MAC. Otherwise, we need to force in e1000_check_for_link()
3918 * speed/duplex on the MAC to the current PHY speed/duplex in e1000_check_for_link()
3921 if (hw->mac_type >= e1000_82544) in e1000_check_for_link()
3927 ("Error configuring MAC to PHY settings\n"); in e1000_check_for_link()
3932 /* Configure Flow Control now that Auto-Neg has completed. First, we in e1000_check_for_link()
3934 * have had to re-autoneg with a different link partner. in e1000_check_for_link()
3943 * auto-negotiated link. These are conditions for checking the link in e1000_check_for_link()
3947 * we assume that they are GMII-based, and TBI compatibility is not in e1000_check_for_link()
3949 * partner is TBI-based, and we turn on TBI Compatibility. in e1000_check_for_link()
3951 if (hw->tbi_compatibility_en) { in e1000_check_for_link()
3954 DEBUGOUT("PHY Read Error\n"); in e1000_check_for_link()
3955 return -E1000_ERR_PHY; in e1000_check_for_link()
3965 if (hw->tbi_compatibility_on) { in e1000_check_for_link()
3970 hw->tbi_compatibility_on = false; in e1000_check_for_link()
3978 if (!hw->tbi_compatibility_on) { in e1000_check_for_link()
3979 hw->tbi_compatibility_on = true; in e1000_check_for_link()
3987 /* If we don't have link (auto-negotiation failed or link partner cannot in e1000_check_for_link()
3988 * auto-negotiate), the cable is plugged in (we have signal), and our in e1000_check_for_link()
3989 * link partner is not trying to auto-negotiate with us (we are receiving in e1000_check_for_link()
3991 * auto-negotiation time to complete, in case the cable was just plugged in e1000_check_for_link()
3994 else if ((hw->media_type == e1000_media_type_fiber) && in e1000_check_for_link()
3996 ((ctrl & E1000_CTRL_SWDPIN1) == signal) && in e1000_check_for_link()
3998 if (hw->autoneg_failed == 0) { in e1000_check_for_link()
3999 hw->autoneg_failed = 1; in e1000_check_for_link()
4004 /* Disable auto-negotiation in the TXCW register */ in e1000_check_for_link()
4005 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE)); in e1000_check_for_link()
4007 /* Force link-up and also force full-duplex. */ in e1000_check_for_link()
4008 ctrl = E1000_READ_REG(hw, CTRL); in e1000_check_for_link()
4009 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD); in e1000_check_for_link()
4010 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_check_for_link()
4019 /* If we are forcing link and we are receiving /C/ ordered sets, re-enable in e1000_check_for_link()
4020 * auto-negotiation in the TXCW register and disable forced link in the in e1000_check_for_link()
4021 * Device Control register in an attempt to auto-negotiate with our link in e1000_check_for_link()
4024 else if ((hw->media_type == e1000_media_type_fiber) && in e1000_check_for_link()
4025 (ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) { in e1000_check_for_link()
4028 E1000_WRITE_REG(hw, TXCW, hw->txcw); in e1000_check_for_link()
4029 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU)); in e1000_check_for_link()
4035 * Configure the MAC-to-PHY interface for 10/100Mbps
4037 * hw - Struct containing variables accessed by shared code
4054 /* Configure Transmit Inter-Packet Gap */ in e1000_configure_kmrn_for_10_100()
4090 /* Configure Transmit Inter-Packet Gap */ in e1000_configure_kmrn_for_1000()
4110 * hw - Struct containing variables accessed by shared code
4111 * speed - Speed of the connection
4112 * duplex - Duplex setting of the connection
4124 if (hw->mac_type >= e1000_82543) { in e1000_get_speed_and_duplex()
4150 /* IGP01 PHY may advertise full duplex operation after speed downgrade in e1000_get_speed_and_duplex()
4154 if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) { in e1000_get_speed_and_duplex()
4174 if ((hw->mac_type == e1000_80003es2lan) && in e1000_get_speed_and_duplex()
4175 (hw->media_type == e1000_media_type_copper)) { in e1000_get_speed_and_duplex()
4189 * hw - Struct containing variables accessed by shared code
4198 DEBUGOUT("Waiting for Auto-Neg to complete.\n"); in e1000_wait_autoneg()
4201 for (i = PHY_AUTO_NEG_TIME; i > 0; i--) { in e1000_wait_autoneg()
4202 /* Read the MII Status Register and wait for Auto-Neg in e1000_wait_autoneg()
4206 DEBUGOUT("PHY Read Error\n"); in e1000_wait_autoneg()
4207 return -E1000_ERR_PHY; in e1000_wait_autoneg()
4210 DEBUGOUT("PHY Read Error\n"); in e1000_wait_autoneg()
4211 return -E1000_ERR_PHY; in e1000_wait_autoneg()
4214 DEBUGOUT("Auto-Neg complete.\n"); in e1000_wait_autoneg()
4219 DEBUGOUT("Auto-Neg timedout.\n"); in e1000_wait_autoneg()
4220 return -E1000_ERR_TIMEOUT; in e1000_wait_autoneg()
4226 * hw - Struct containing variables accessed by shared code
4227 * ctrl - Device control register's current value
4230 e1000_raise_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) in e1000_raise_mdi_clk() argument
4235 E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC)); in e1000_raise_mdi_clk()
4243 * hw - Struct containing variables accessed by shared code
4244 * ctrl - Device control register's current value
4247 e1000_lower_mdi_clk(struct e1000_hw *hw, uint32_t * ctrl) in e1000_lower_mdi_clk() argument
4252 E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC)); in e1000_lower_mdi_clk()
4258 * Shifts data bits out to the PHY
4260 * hw - Struct containing variables accessed by shared code
4261 * data - Data to send out to the PHY
4262 * count - Number of bits to shift out
4269 uint32_t ctrl; in e1000_shift_out_mdi_bits() local
4272 /* We need to shift "count" number of bits out to the PHY. So, the value in e1000_shift_out_mdi_bits()
4273 * in the "data" parameter will be shifted out to the PHY one bit at a in e1000_shift_out_mdi_bits()
4277 mask <<= (count - 1); in e1000_shift_out_mdi_bits()
4279 ctrl = E1000_READ_REG(hw, CTRL); in e1000_shift_out_mdi_bits()
4282 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR); in e1000_shift_out_mdi_bits()
4285 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and in e1000_shift_out_mdi_bits()
4287 * shifted out to the PHY by setting the MDIO bit to "0" and then in e1000_shift_out_mdi_bits()
4291 ctrl |= E1000_CTRL_MDIO; in e1000_shift_out_mdi_bits()
4293 ctrl &= ~E1000_CTRL_MDIO; in e1000_shift_out_mdi_bits()
4295 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_shift_out_mdi_bits()
4300 e1000_raise_mdi_clk(hw, &ctrl); in e1000_shift_out_mdi_bits()
4301 e1000_lower_mdi_clk(hw, &ctrl); in e1000_shift_out_mdi_bits()
4308 * Shifts data bits in from the PHY
4310 * hw - Struct containing variables accessed by shared code
4317 uint32_t ctrl; in e1000_shift_in_mdi_bits() local
4321 /* In order to read a register from the PHY, we need to shift in a total in e1000_shift_in_mdi_bits()
4322 * of 18 bits from the PHY. The first two bit (turnaround) times are used in e1000_shift_in_mdi_bits()
4328 ctrl = E1000_READ_REG(hw, CTRL); in e1000_shift_in_mdi_bits()
4331 ctrl &= ~E1000_CTRL_MDIO_DIR; in e1000_shift_in_mdi_bits()
4332 ctrl &= ~E1000_CTRL_MDIO; in e1000_shift_in_mdi_bits()
4334 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_shift_in_mdi_bits()
4341 e1000_raise_mdi_clk(hw, &ctrl); in e1000_shift_in_mdi_bits()
4342 e1000_lower_mdi_clk(hw, &ctrl); in e1000_shift_in_mdi_bits()
4346 e1000_raise_mdi_clk(hw, &ctrl); in e1000_shift_in_mdi_bits()
4347 ctrl = E1000_READ_REG(hw, CTRL); in e1000_shift_in_mdi_bits()
4349 if (ctrl & E1000_CTRL_MDIO) in e1000_shift_in_mdi_bits()
4351 e1000_lower_mdi_clk(hw, &ctrl); in e1000_shift_in_mdi_bits()
4354 e1000_raise_mdi_clk(hw, &ctrl); in e1000_shift_in_mdi_bits()
4355 e1000_lower_mdi_clk(hw, &ctrl); in e1000_shift_in_mdi_bits()
4361 * Reads the value from a PHY register
4363 * hw - Struct containing variables accessed by shared code
4364 * reg_addr - address of the PHY register to read
4374 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); in e1000_read_phy_reg()
4375 return -E1000_ERR_PARAM; in e1000_read_phy_reg()
4378 if (hw->mac_type > e1000_82543) { in e1000_read_phy_reg()
4379 /* Set up Op-code, Phy Address, and register address in the MDI in e1000_read_phy_reg()
4380 * Control register. The MAC will take care of interfacing with the in e1000_read_phy_reg()
4381 * PHY to retrieve the desired data. in e1000_read_phy_reg()
4398 return -E1000_ERR_PHY; in e1000_read_phy_reg()
4402 return -E1000_ERR_PHY; in e1000_read_phy_reg()
4417 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr> in e1000_read_phy_reg()
4429 * "shift in" the 16-bit value (18 total bits) of the requested PHY in e1000_read_phy_reg()
4438 * Writes a value to a PHY register
4440 * hw - Struct containing variables accessed by shared code
4441 * reg_addr - address of the PHY register to write
4442 * data - data to write to the PHY
4452 DEBUGOUT("PHY Address %d is out of range\n", reg_addr); in e1000_write_phy_reg()
4453 return -E1000_ERR_PARAM; in e1000_write_phy_reg()
4456 if (hw->mac_type > e1000_82543) { in e1000_write_phy_reg()
4457 /* Set up Op-code, Phy Address, register address, and data intended in e1000_write_phy_reg()
4458 * for the PHY register in the MDI Control register. The MAC will take in e1000_write_phy_reg()
4459 * care of interfacing with the PHY to send the desired data. in e1000_write_phy_reg()
4477 return -E1000_ERR_PHY; in e1000_write_phy_reg()
4481 * out to the PHY. We first send a preamble to the PHY to signal the in e1000_write_phy_reg()
4491 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>. in e1000_write_phy_reg()
4504 * Checks if PHY reset is blocked due to SOL/IDER session, for example.
4508 * hw - Struct containing variables accessed by shared code
4510 * returns: - E1000_BLK_PHY_RESET
4520 if (hw->mac_type == e1000_ich8lan) { in e1000_check_phy_reset_block()
4526 if (hw->mac_type > e1000_82547_rev_2) in e1000_check_phy_reset_block()
4533 * Checks if the PHY configuration is done
4537 * returns: - E1000_ERR_RESET if fail to reset MAC
4549 switch (hw->mac_type) { in e1000_get_phy_cfg_done()
4564 if (hw->mac_type == e1000_igb) { in e1000_get_phy_cfg_done()
4572 timeout--; in e1000_get_phy_cfg_done()
4577 return -E1000_ERR_RESET; in e1000_get_phy_cfg_done()
4586 * Returns the PHY to the power-on reset state
4588 * hw - Struct containing variables accessed by shared code
4594 uint32_t ctrl, ctrl_ext; in e1000_phy_hw_reset() local
4600 /* In the case of the phy reset being blocked, it's not an error, we in e1000_phy_hw_reset()
4606 DEBUGOUT("Resetting Phy...\n"); in e1000_phy_hw_reset()
4608 if (hw->mac_type > e1000_82543) { in e1000_phy_hw_reset()
4614 return -E1000_ERR_SWFW_SYNC; in e1000_phy_hw_reset()
4620 ctrl = E1000_READ_REG(hw, CTRL); in e1000_phy_hw_reset()
4621 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST); in e1000_phy_hw_reset()
4624 if (hw->mac_type < e1000_82571) in e1000_phy_hw_reset()
4629 E1000_WRITE_REG(hw, CTRL, ctrl); in e1000_phy_hw_reset()
4632 if (hw->mac_type >= e1000_82571) in e1000_phy_hw_reset()
4637 * bit to put the PHY into reset. Then, take it out of reset. in e1000_phy_hw_reset()
4651 if ((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) { in e1000_phy_hw_reset()
4652 /* Configure activity LED after PHY reset */ in e1000_phy_hw_reset()
4661 /* Wait for FW to finish PHY configuration. */ in e1000_phy_hw_reset()
4670 * IGP phy init script - initializes the GbE PHY
4672 * hw - Struct containing variables accessed by shared code
4681 if (hw->phy_init_script) { in e1000_phy_init_script()
4688 /* Disabled the PHY transmitter */ in e1000_phy_init_script()
4697 switch (hw->mac_type) { in e1000_phy_init_script()
4735 if (hw->mac_type == e1000_82547) { in e1000_phy_init_script()
4752 coarse -= in e1000_phy_init_script()
4754 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; in e1000_phy_init_script()
4757 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; in e1000_phy_init_script()
4777 * Resets the PHY
4779 * hw - Struct containing variables accessed by shared code
4791 /* In the case of the phy reset being blocked, it's not an error, we in e1000_phy_reset()
4797 switch (hw->phy_type) { in e1000_phy_reset()
4821 if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_igp_2) in e1000_phy_reset()
4831 if (hw->mac_type == e1000_undefined) in e1000_set_phy_type()
4832 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()
4834 switch (hw->phy_id) { in e1000_set_phy_type()
4839 hw->phy_type = e1000_phy_m88; in e1000_set_phy_type()
4842 if (hw->mac_type == e1000_82541 || in e1000_set_phy_type()
4843 hw->mac_type == e1000_82541_rev_2 || in e1000_set_phy_type()
4844 hw->mac_type == e1000_82547 || in e1000_set_phy_type()
4845 hw->mac_type == e1000_82547_rev_2) { in e1000_set_phy_type()
4846 hw->phy_type = e1000_phy_igp; in e1000_set_phy_type()
4850 hw->phy_type = e1000_phy_igp_3; in e1000_set_phy_type()
4855 hw->phy_type = e1000_phy_ife; in e1000_set_phy_type()
4858 if (hw->mac_type == e1000_80003es2lan) { in e1000_set_phy_type()
4859 hw->phy_type = e1000_phy_gg82563; in e1000_set_phy_type()
4863 hw->phy_type = e1000_phy_bm; in e1000_set_phy_type()
4866 hw->phy_type = e1000_phy_igb; in e1000_set_phy_type()
4871 hw->phy_type = e1000_phy_undefined; in e1000_set_phy_type()
4872 return -E1000_ERR_PHY_TYPE; in e1000_set_phy_type()
4879 * Probes the expected PHY address for known PHY IDs
4881 * hw - Struct containing variables accessed by shared code
4892 /* The 82571 firmware may still be configuring the PHY. In this in e1000_detect_gig_phy()
4893 * case, we cannot access the PHY until the configuration is done. So in e1000_detect_gig_phy()
4894 * we explicitly set the PHY values. */ in e1000_detect_gig_phy()
4895 if (hw->mac_type == e1000_82571 || in e1000_detect_gig_phy()
4896 hw->mac_type == e1000_82572) { in e1000_detect_gig_phy()
4897 hw->phy_id = IGP01E1000_I_PHY_ID; in e1000_detect_gig_phy()
4898 hw->phy_type = e1000_phy_igp_2; in e1000_detect_gig_phy()
4902 /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a in e1000_detect_gig_phy()
4903 * work- around that forces PHY page 0 to be set or the reads fail. in e1000_detect_gig_phy()
4905 * read the PHY ID. So for ESB-2 we need to have this set so our in e1000_detect_gig_phy()
4906 * reads won't fail. If the attached PHY is not a e1000_phy_gg82563, in e1000_detect_gig_phy()
4908 if (hw->mac_type == e1000_80003es2lan) in e1000_detect_gig_phy()
4909 hw->phy_type = e1000_phy_gg82563; in e1000_detect_gig_phy()
4911 /* Read the PHY ID Registers to identify which PHY is onboard. */ in e1000_detect_gig_phy()
4916 hw->phy_id = (uint32_t) (phy_id_high << 16); in e1000_detect_gig_phy()
4922 hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK); in e1000_detect_gig_phy()
4923 hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK; in e1000_detect_gig_phy()
4925 switch (hw->mac_type) { in e1000_detect_gig_phy()
4927 if (hw->phy_id == M88E1000_E_PHY_ID) in e1000_detect_gig_phy()
4931 if (hw->phy_id == M88E1000_I_PHY_ID) in e1000_detect_gig_phy()
4939 if (hw->phy_id == M88E1011_I_PHY_ID) in e1000_detect_gig_phy()
4946 if(hw->phy_id == IGP01E1000_I_PHY_ID) in e1000_detect_gig_phy()
4951 if (hw->phy_id == M88E1111_I_PHY_ID) in e1000_detect_gig_phy()
4955 if (hw->phy_id == BME1000_E_PHY_ID) in e1000_detect_gig_phy()
4959 if (hw->phy_id == GG82563_E_PHY_ID) in e1000_detect_gig_phy()
4963 if (hw->phy_id == IGP03E1000_E_PHY_ID) in e1000_detect_gig_phy()
4965 if (hw->phy_id == IFE_E_PHY_ID) in e1000_detect_gig_phy()
4967 if (hw->phy_id == IFE_PLUS_E_PHY_ID) in e1000_detect_gig_phy()
4969 if (hw->phy_id == IFE_C_E_PHY_ID) in e1000_detect_gig_phy()
4973 if (hw->phy_id == I210_I_PHY_ID) in e1000_detect_gig_phy()
4977 DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); in e1000_detect_gig_phy()
4978 return -E1000_ERR_CONFIG; in e1000_detect_gig_phy()
4984 DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); in e1000_detect_gig_phy()
4987 DEBUGOUT("Invalid PHY ID 0x%X\n", hw->phy_id); in e1000_detect_gig_phy()
4988 return -E1000_ERR_PHY; in e1000_detect_gig_phy()
4994 * hw - Struct containing variables accessed by shared code
5003 if (hw->mac_type != e1000_82543) { in e1000_set_media_type()
5005 hw->tbi_compatibility_en = false; in e1000_set_media_type()
5008 switch (hw->device_id) { in e1000_set_media_type()
5016 hw->media_type = e1000_media_type_internal_serdes; in e1000_set_media_type()
5019 switch (hw->mac_type) { in e1000_set_media_type()
5022 hw->media_type = e1000_media_type_fiber; in e1000_set_media_type()
5031 hw->media_type = e1000_media_type_copper; in e1000_set_media_type()
5036 hw->media_type = e1000_media_type_fiber; in e1000_set_media_type()
5038 hw->tbi_compatibility_en = false; in e1000_set_media_type()
5040 hw->media_type = e1000_media_type_copper; in e1000_set_media_type()
5048 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
5062 dm_pci_read_config16(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); in e1000_sw_init()
5063 dm_pci_read_config16(hw->pdev, PCI_DEVICE_ID, &hw->device_id); in e1000_sw_init()
5064 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, in e1000_sw_init()
5065 &hw->subsystem_vendor_id); in e1000_sw_init()
5066 dm_pci_read_config16(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); in e1000_sw_init()
5068 dm_pci_read_config8(hw->pdev, PCI_REVISION_ID, &hw->revision_id); in e1000_sw_init()
5069 dm_pci_read_config16(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); in e1000_sw_init()
5071 pci_read_config_word(hw->pdev, PCI_VENDOR_ID, &hw->vendor_id); in e1000_sw_init()
5072 pci_read_config_word(hw->pdev, PCI_DEVICE_ID, &hw->device_id); in e1000_sw_init()
5073 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_VENDOR_ID, in e1000_sw_init()
5074 &hw->subsystem_vendor_id); in e1000_sw_init()
5075 pci_read_config_word(hw->pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id); in e1000_sw_init()
5077 pci_read_config_byte(hw->pdev, PCI_REVISION_ID, &hw->revision_id); in e1000_sw_init()
5078 pci_read_config_word(hw->pdev, PCI_COMMAND, &hw->pci_cmd_word); in e1000_sw_init()
5081 /* identify the MAC */ in e1000_sw_init()
5084 E1000_ERR(hw, "Unknown MAC Type\n"); in e1000_sw_init()
5088 switch (hw->mac_type) { in e1000_sw_init()
5095 hw->phy_init_script = 1; in e1000_sw_init()
5100 hw->fc_high_water = E1000_FC_HIGH_THRESH; in e1000_sw_init()
5101 hw->fc_low_water = E1000_FC_LOW_THRESH; in e1000_sw_init()
5102 hw->fc_pause_time = E1000_FC_PAUSE_TIME; in e1000_sw_init()
5103 hw->fc_send_xon = 1; in e1000_sw_init()
5105 /* Media type - copper or fiber */ in e1000_sw_init()
5106 hw->tbi_compatibility_en = true; in e1000_sw_init()
5109 if (hw->mac_type >= e1000_82543) { in e1000_sw_init()
5114 hw->media_type = e1000_media_type_fiber; in e1000_sw_init()
5117 hw->media_type = e1000_media_type_copper; in e1000_sw_init()
5120 hw->media_type = e1000_media_type_fiber; in e1000_sw_init()
5123 hw->wait_autoneg_complete = true; in e1000_sw_init()
5124 if (hw->mac_type < e1000_82543) in e1000_sw_init()
5125 hw->report_tx_early = 0; in e1000_sw_init()
5127 hw->report_tx_early = 1; in e1000_sw_init()
5142 rd->buffer_addr = cpu_to_le64((unsigned long)packet); in fill_rx()
5152 flush_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); in fill_rx()
5160 * e1000_configure_tx - Configure 8254x Transmit Unit after Reset
5163 * Configure the Tx unit of the MAC after a reset.
5184 if (hw->mac_type <= e1000_82547_rev_2 && in e1000_configure_tx()
5185 (hw->media_type == e1000_media_type_fiber || in e1000_configure_tx()
5186 hw->media_type == e1000_media_type_internal_serdes)) in e1000_configure_tx()
5192 switch (hw->mac_type) { in e1000_configure_tx()
5217 if (hw->mac_type == e1000_82571 || hw->mac_type == e1000_82572) { in e1000_configure_tx()
5222 } else if (hw->mac_type == e1000_80003es2lan) { in e1000_configure_tx()
5234 hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS; in e1000_configure_tx()
5237 if (hw->mac_type < e1000_82543) in e1000_configure_tx()
5238 hw->txd_cmd |= E1000_TXD_CMD_RPS; in e1000_configure_tx()
5240 hw->txd_cmd |= E1000_TXD_CMD_RS; in e1000_configure_tx()
5243 if (hw->mac_type == e1000_igb) { in e1000_configure_tx()
5260 * e1000_setup_rctl - configure the receive control register
5276 if (hw->tbi_compatibility_on == 1) in e1000_setup_rctl()
5288 * e1000_configure_rx - Configure 8254x Receive Unit after Reset
5291 * Configure the Rx unit of the MAC after a reset.
5302 if (hw->mac_type >= e1000_82540) { in e1000_configure_rx()
5310 if (hw->mac_type >= e1000_82571) { in e1000_configure_rx()
5328 if (hw->mac_type == e1000_igb) { in e1000_configure_rx()
5342 POLL - Wait for a frame
5354 /* Re-load the descriptor from RAM. */ in _e1000_poll()
5355 inval_start = ((unsigned long)rd) & ~(ARCH_DMA_MINALIGN - 1); in _e1000_poll()
5359 if (!(rd->status & E1000_RXD_STAT_DD)) in _e1000_poll()
5361 /* DEBUGOUT("recv: packet len=%d\n", rd->length); */ in _e1000_poll()
5362 /* Packet received, make sure the data are re-loaded from RAM. */ in _e1000_poll()
5363 len = le16_to_cpu(rd->length); in _e1000_poll()
5380 txp->buffer_addr = cpu_to_le64(virt_to_bus(hw->pdev, nv_packet)); in _e1000_transmit()
5381 txp->lower.data = cpu_to_le32(hw->txd_cmd | length); in _e1000_transmit()
5382 txp->upper.data = 0; in _e1000_transmit()
5389 flush_start = ((unsigned long)txp) & ~(ARCH_DMA_MINALIGN - 1); in _e1000_transmit()
5398 if (le32_to_cpu(txp->upper.data) & E1000_TXD_STAT_DD) in _e1000_transmit()
5432 if (hw->mac_type >= e1000_82544) in e1000_reset()
5445 if ((ret_val == -E1000_ERR_NOLINK) || in _e1000_init()
5446 (ret_val == -E1000_ERR_TIMEOUT)) { in _e1000_init()
5462 * hw - Struct containing variables accessed by shared code
5468 switch (hw->mac_type) { in e1000_get_bus_type()
5471 hw->bus_type = e1000_bus_type_pci; in e1000_get_bus_type()
5480 hw->bus_type = e1000_bus_type_pci_express; in e1000_get_bus_type()
5484 hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ? in e1000_get_bus_type()
5505 /* Assign the passed-in values */ in e1000_init_one()
5507 hw->pdev = devno; in e1000_init_one()
5509 hw->pdev = devno; in e1000_init_one()
5511 hw->cardnum = cardnum; in e1000_init_one()
5521 /* Try to enable I/O accesses and bus-mastering */ in e1000_init_one()
5537 return -ENOSPC; in e1000_init_one()
5540 E1000_ERR(hw, "Can't enable bus-mastering\n"); in e1000_init_one()
5541 return -EPERM; in e1000_init_one()
5545 hw->fc = e1000_fc_default; in e1000_init_one()
5546 hw->original_fc = e1000_fc_default; in e1000_init_one()
5547 hw->autoneg_failed = 0; in e1000_init_one()
5548 hw->autoneg = 1; in e1000_init_one()
5549 hw->get_link_status = true; in e1000_init_one()
5551 hw->eeprom_semaphore_present = true; in e1000_init_one()
5554 hw->hw_addr = dm_pci_map_bar(devno, PCI_BASE_ADDRESS_0, in e1000_init_one()
5557 hw->hw_addr = pci_map_bar(devno, PCI_BASE_ADDRESS_0, in e1000_init_one()
5560 hw->mac_type = e1000_undefined; in e1000_init_one()
5562 /* MAC and Phy settings */ in e1000_init_one()
5565 return -EIO; in e1000_init_one()
5568 E1000_ERR(hw, "PHY Reset is blocked!\n"); in e1000_init_one()
5577 return -EINVAL; in e1000_init_one()
5581 return -ENXIO; in e1000_init_one()
5606 TRANSMIT - Transmit a frame
5610 struct e1000_hw *hw = nic->priv; in e1000_transmit()
5616 DISABLE - Turn off ethernet interface
5621 struct e1000_hw *hw = nic->priv; in e1000_disable()
5627 INIT - set up ethernet interface(s)
5632 struct e1000_hw *hw = nic->priv; in e1000_init()
5634 return _e1000_init(hw, nic->enetaddr); in e1000_init()
5640 struct e1000_hw *hw = nic->priv; in e1000_poll()
5655 unsigned char *mac = dev->enetaddr; in e1000_write_hwaddr() local
5657 struct e1000_hw *hw = dev->priv; in e1000_write_hwaddr()
5661 DEBUGOUT("%s: mac=%pM\n", __func__, mac); in e1000_write_hwaddr()
5669 DEBUGOUT("%s: current mac=%pM\n", __func__, current_mac); in e1000_write_hwaddr()
5674 if (!ret_val && memcmp(current_mac, mac, 6) == 0) in e1000_write_hwaddr()
5678 data[i] = mac[i * 2 + 1] << 8 | mac[i * 2]; in e1000_write_hwaddr()
5692 PROBE - Look for an adapter, this routine's visible to the outside
5693 You should omit the last argument struct pci_device * for a non-PCI NIC
5708 * perform SPI EEPROM programming from U-Boot, for example. in e1000_initialize()
5722 nic->priv = hw; in e1000_initialize()
5725 e1000_name(nic->name, i); in e1000_initialize()
5726 hw->name = nic->name; in e1000_initialize()
5728 ret = e1000_init_one(hw, i, devno, nic->enetaddr); in e1000_initialize()
5731 list_add_tail(&hw->list_node, &e1000_hw_list); in e1000_initialize()
5733 hw->nic = nic; in e1000_initialize()
5736 nic->init = e1000_init; in e1000_initialize()
5737 nic->recv = e1000_poll; in e1000_initialize()
5738 nic->send = e1000_transmit; in e1000_initialize()
5739 nic->halt = e1000_disable; in e1000_initialize()
5740 nic->write_hwaddr = e1000_write_hwaddr; in e1000_initialize()
5752 if (hw->cardnum == cardnum) in e1000_find_card()
5763 unsigned char *mac = NULL; in do_e1000() local
5787 mac = plat->enetaddr; in do_e1000()
5792 mac = hw->nic->enetaddr; in do_e1000()
5794 if (!mac) { in do_e1000()
5799 if (!strcmp(argv[2], "print-mac-address")) { in do_e1000()
5801 mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); in do_e1000()
5811 return do_e1000_spi(cmdtp, hw, argc - 3, argv + 3); in do_e1000()
5821 /* */"<card#> print-mac-address\n"
5828 " - Manage the Intel E1000 PCI device"
5838 return _e1000_init(hw, plat->enetaddr); in e1000_eth_start()
5855 return ret ? 0 : -ETIMEDOUT; in e1000_eth_send()
5867 return len ? len : -EAGAIN; in e1000_eth_recv()
5885 hw->name = dev->name; in e1000_eth_probe()
5886 ret = e1000_init_one(hw, trailing_strtol(dev->name), in e1000_eth_probe()
5887 dev, plat->enetaddr); in e1000_eth_probe()