| /openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
| H A D | analogix,anx7625.yaml | 72 analogix,lane1-swing:
77 an array of swing register setting for DP tx lane1 PHY.
78 DP TX lane1 swing register setting same with lane0
150 analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
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| /openbmc/u-boot/board/freescale/ls1046ardb/ |
| H A D | README | 18 - Lane1: XFI Cage
23 - Lane1: PCIe2 with PCIe x2 slot
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| /openbmc/ipmitool/include/ipmitool/ |
| H A D | ipmi_picmg.h | 187 unsigned short lane1 : 1; member
199 unsigned short lane1 : 1;
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | pci-armada8k.txt | 25 Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | zynqmp-zc1232-revA.dts | 82 phys = <&lane0 PHY_TYPE_SATA 0 0 125000000>, <&lane1 PHY_TYPE_SATA 1 1 125000000>;
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| H A D | zynqmp.dtsi | 680 lane1: lane1 { label
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| /openbmc/linux/Documentation/devicetree/bindings/phy/ |
| H A D | qcom,msm8996-qmp-pcie-phy.yaml | 88 - lane1
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| /openbmc/linux/drivers/phy/marvell/ |
| H A D | phy-mvebu-a3700-comphy.c | 188 * lane1: PCIe/GbE0 PHY Configuration 1
209 * lane1: PCIe/GbE0 PHY Status 1
219 /* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */
501 /* PCIE must be in Lane1 */ in mvebu_a3700_comphy_set_phy_selector()
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| /openbmc/u-boot/board/freescale/p1010rdb/ |
| H A D | README.P1010RDB-PA | 24 - Lane1: x1 PCIe standard slot
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| /openbmc/linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3568.dtsi | 104 /* bifurcation; lane1 when using 1+1 */
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| /openbmc/linux/drivers/gpu/drm/amd/display/include/ |
| H A D | grph_object_ctrl_defs.h | 243 uint8_t lane1:2; /* Mapping for lane 1 */ member
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| /openbmc/linux/arch/arm64/boot/dts/marvell/ |
| H A D | armada-8040-mcbin.dtsi | 188 phy-names = "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy",
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| H A D | armada-8040-puzzle-m801.dts | 521 phy-names = "cp1-pcie0-x2-lane0-phy", "cp1-pcie0-x2-lane1-phy";
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| /openbmc/linux/drivers/phy/rockchip/ |
| H A D | phy-rockchip-dphy-rx0.c | 212 /* HS RX Control of lane1 */ in rk_dphy_enable()
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| /openbmc/linux/drivers/net/ethernet/ti/ |
| H A D | netcp_xgbepcsr.c | 258 /* For 2 lane Phy-B, lane0 is actually lane1 */ in netcp_xgbe_serdes_write_tbus_addr()
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| /openbmc/linux/drivers/ufs/host/ |
| H A D | ufs-hisi.c | 62 dev_err(hba->dev, "%s: invalid TX_FSM_STATE, lane0 = %d, lane1 = %d\n", in ufs_hisi_check_hibern8()
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| H A D | ufs-qcom.c | 312 /* In case of single lane per direction, don't read lane1 clocks */ in ufs_qcom_init_lane_clks()
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| /openbmc/linux/drivers/gpu/drm/bridge/analogix/ |
| H A D | anx7625.c | 1658 "analogix,lane1-swing", &num_regs)) { in anx7625_get_swing_setting()
1663 of_property_read_u8_array(dev->of_node, "analogix,lane1-swing", in anx7625_get_swing_setting()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_training.c | 116 lt_result = "CR failed lane1"; in dp_log_training_result()
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| /openbmc/linux/arch/arm64/boot/dts/qcom/ |
| H A D | msm8996.dtsi | 722 reset-names = "lane1";
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| /openbmc/linux/drivers/gpu/drm/radeon/ |
| H A D | atombios.h | 4113 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
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| /openbmc/linux/drivers/gpu/drm/amd/include/ |
| H A D | atombios.h | 4605 //Bit[3:2]: Define which pin connect to DVI connector data Lane1, =0: source from GPU pin TX0, =1: …
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