| /openbmc/linux/drivers/phy/freescale/ |
| H A D | phy-fsl-lynx-28g.c | 24 #define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1)) argument
45 /* Per SerDes lane registers */
46 /* Lane a General Control Register */
47 #define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0) argument
55 /* Lane a Tx Reset Control Register */
56 #define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20) argument
61 /* Lane a Tx General Control Register */
62 #define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24) argument
71 #define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30) argument
73 /* Lane a Rx Reset Control Register */
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| /openbmc/linux/drivers/phy/marvell/ |
| H A D | phy-mvebu-cp110-comphy.c | 129 * A lane is described by the following bitfields:
182 unsigned lane; member
190 .lane = _lane, \
200 .lane = _lane, \
209 /* lane 0 */
214 /* lane 1 */
221 /* lane 2 */
230 /* lane 3 */
237 /* lane 4 */
250 /* lane 5 */
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| H A D | phy-mvebu-a3700-comphy.c | 40 * When accessing common PHY lane registers directly, we need to shift by 1,
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f)) argument
227 unsigned int lane; member
234 .lane = _lane, \
246 /* lane 0 */
251 /* lane 1 */
256 /* lane 2 */
387 /* Used for accessing lane 2 registers (SATA/USB3 PHY) */
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| H A D | phy-armada38x-comphy.c | 47 struct a38x_comphy_lane lane[MAX_A38X_COMPHY]; member
59 static void a38x_set_conf(struct a38x_comphy_lane *lane, bool enable) in a38x_set_conf() argument
61 struct a38x_comphy *priv = lane->priv; in a38x_set_conf()
67 conf |= BIT(lane->port); in a38x_set_conf()
69 conf &= ~BIT(lane->port); in a38x_set_conf()
74 static void a38x_comphy_set_reg(struct a38x_comphy_lane *lane, in a38x_comphy_set_reg() argument
79 val = readl_relaxed(lane->base + offset) & ~mask; in a38x_comphy_set_reg()
80 writel(val | value, lane->base + offset); in a38x_comphy_set_reg()
83 static void a38x_comphy_set_speed(struct a38x_comphy_lane *lane, in a38x_comphy_set_speed() argument
86 a38x_comphy_set_reg(lane, COMPHY_CFG1, in a38x_comphy_set_speed()
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| /openbmc/linux/drivers/net/dsa/b53/ |
| H A D | b53_serdes.c | 42 static void b53_serdes_set_lane(struct b53_device *dev, u8 lane) in b53_serdes_set_lane() argument
44 if (dev->serdes_lane == lane) in b53_serdes_set_lane()
47 WARN_ON(lane > 1); in b53_serdes_set_lane()
50 SERDES_XGXSBLK0_BLOCKADDRESS, lane); in b53_serdes_set_lane()
51 dev->serdes_lane = lane; in b53_serdes_set_lane()
54 static void b53_serdes_write(struct b53_device *dev, u8 lane, in b53_serdes_write() argument
57 b53_serdes_set_lane(dev, lane); in b53_serdes_write()
61 static u16 b53_serdes_read(struct b53_device *dev, u8 lane, in b53_serdes_read() argument
64 b53_serdes_set_lane(dev, lane); in b53_serdes_read()
74 u8 lane = pcs_to_b53_pcs(pcs)->lane; in b53_serdes_config() local
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| /openbmc/u-boot/drivers/phy/marvell/ |
| H A D | comphy_mux.c | 15 * is valid for specific lane. If the type is not valid,
16 * the function update the struct and set the type of the lane as
23 int lane, opt, valid; in comphy_mux_check_config() local
27 for (lane = 0; lane < comphy_max_lanes; in comphy_mux_check_config()
28 lane++, comphy_map_data++, mux_data++) { in comphy_mux_check_config()
42 debug("lane number %d, had invalid type %d\n", in comphy_mux_check_config()
43 lane, comphy_map_data->type); in comphy_mux_check_config()
44 debug("set lane %d as type %d\n", lane, in comphy_mux_check_config()
48 debug("lane number %d, has type %d\n", in comphy_mux_check_config()
49 lane, comphy_map_data->type); in comphy_mux_check_config()
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| H A D | comphy_core.c | 54 u32 lane; in comphy_print() local
56 for (lane = 0; lane < chip_cfg->comphy_lanes_count; in comphy_print()
57 lane++, comphy_map_data++) { in comphy_print()
59 printf("Comphy-%d: %-13s\n", lane, in comphy_print()
62 printf("Comphy-%d: %-13s %-10s\n", lane, in comphy_print()
81 int lane; in comphy_probe() local
110 fdtdec_locate_array(blob, node, "mux-lane-order", in comphy_probe()
128 lane = 0; in comphy_probe()
134 comphy_map_data[lane].speed = fdtdec_get_int( in comphy_probe()
136 comphy_map_data[lane].type = fdtdec_get_int( in comphy_probe()
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| H A D | comphy_a3700.c | 17 /* Lane 0 */
27 /* Lane 1 */
36 /* Lane 2 */
339 static void usb3_reg_set16(u32 reg, u16 data, u16 mask, u32 lane) in usb3_reg_set16() argument
342 * When Lane 2 PHY is for USB3, access the PHY registers in usb3_reg_set16()
345 * within the SATA Host Controller registers, Lane 2 base register in usb3_reg_set16()
349 if (lane == 2) in usb3_reg_set16()
361 static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert) in comphy_usb3_power_up() argument
381 usb3_reg_set16(LANE_CFG0, 0x1, 0xFF, lane); in comphy_usb3_power_up()
395 | gen2_tx_data_dly_mask | tx_elec_idle_mode_en, lane); in comphy_usb3_power_up()
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| /openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/ |
| H A D | link_dp_training_fixed_vs_pe_retimer.c | 52 uint8_t lane; in dp_fixed_vs_pe_read_lane_adjust() local
54 /* W/A to read lane settings requested by DPRX */ in dp_fixed_vs_pe_read_lane_adjust()
65 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in dp_fixed_vs_pe_read_lane_adjust()
66 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET = (dprx_vs >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
67 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET = (dprx_pe >> (2 * lane)) & 0x3; in dp_fixed_vs_pe_read_lane_adjust()
80 uint8_t lane = 0; in dp_fixed_vs_pe_set_retimer_lane_settings() local
82 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
84 dpcd_lane_adjust[lane].bits.VOLTAGE_SWING_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
86 dpcd_lane_adjust[lane].bits.PRE_EMPHASIS_SET << (2 * lane); in dp_fixed_vs_pe_set_retimer_lane_settings()
106 uint8_t lane = 0; in perform_fixed_vs_pe_nontransparent_training_sequence() local
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| H A D | link_dp_training.c | 305 uint32_t lane; in maximize_lane_settings() local
313 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) { in maximize_lane_settings()
314 if (lane_settings[lane].VOLTAGE_SWING > max_requested.VOLTAGE_SWING) in maximize_lane_settings()
315 max_requested.VOLTAGE_SWING = lane_settings[lane].VOLTAGE_SWING; in maximize_lane_settings()
317 if (lane_settings[lane].PRE_EMPHASIS > max_requested.PRE_EMPHASIS) in maximize_lane_settings()
318 max_requested.PRE_EMPHASIS = lane_settings[lane].PRE_EMPHASIS; in maximize_lane_settings()
319 if (lane_settings[lane].FFE_PRESET.settings.level > in maximize_lane_settings()
322 lane_settings[lane].FFE_PRESET.settings.level; in maximize_lane_settings()
343 for (lane = 0; lane < LANE_COUNT_DP_MAX; lane++) { in maximize_lane_settings()
344 lane_settings[lane].VOLTAGE_SWING = max_requested.VOLTAGE_SWING; in maximize_lane_settings()
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| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | fsl_corenet_serdes.c | 61 unsigned int lpd; /* RCW lane powerdown bit */
95 int serdes_get_lane_idx(int lane) in serdes_get_lane_idx() argument
97 return lanes[lane].idx; in serdes_get_lane_idx()
100 int serdes_get_bank_by_lane(int lane) in serdes_get_bank_by_lane() argument
102 return lanes[lane].bank; in serdes_get_bank_by_lane()
105 int serdes_lane_enabled(int lane) in serdes_lane_enabled() argument
110 int bank = lanes[lane].bank; in serdes_lane_enabled()
111 int word = lanes[lane].lpd / 32; in serdes_lane_enabled()
112 int bit = lanes[lane].lpd % 32; in serdes_lane_enabled()
124 return !(srds_lpd_b[bank] & (8 >> (lane - (6 + 4 * bank)))); in serdes_lane_enabled()
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| H A D | mpc8536_serdes.c | 96 int lane; in fsl_serdes_init() local
113 case 1: /* Lane A - SATA1, Lane E - SATA2 */ in fsl_serdes_init()
141 case 3: /* Lane A - SATA1, Lane E - disabled */ in fsl_serdes_init()
163 case 4: /* Lane A - eTSEC1 SGMII, Lane E - eTSEC3 SGMII */ in fsl_serdes_init()
191 case 6: /* Lane A - eTSEC1 SGMII, Lane E - disabled */ in fsl_serdes_init()
213 case 7: /* Lane A - disabled, Lane E - disabled */ in fsl_serdes_init()
230 for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { in fsl_serdes_init()
231 enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_io_sel][lane]; in fsl_serdes_init()
243 for (lane = 0; lane < SRDS2_MAX_LANES; lane++) { in fsl_serdes_init()
244 enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane]; in fsl_serdes_init()
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| /openbmc/u-boot/board/highbank/ |
| H A D | ahci.c | 81 static void cphy_spread_spectrum_override(u8 phy, u8 lane, u32 val) in cphy_spread_spectrum_override() argument
84 tmp = combo_phy_read(phy, CPHY_RX_INPUT_STS + lane * SPHY_LANE); in cphy_spread_spectrum_override()
86 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
89 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
93 combo_phy_write(phy, CPHY_RX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_spread_spectrum_override()
96 static void cphy_tx_attenuation_override(u8 phy, u8 lane) in cphy_tx_attenuation_override() argument
102 shift = ((phy == 5) ? 4 : lane) * 4; in cphy_tx_attenuation_override()
109 tmp = combo_phy_read(phy, CPHY_TX_INPUT_STS + lane * SPHY_LANE); in cphy_tx_attenuation_override()
111 combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_tx_attenuation_override()
114 combo_phy_write(phy, CPHY_TX_INPUT_OVERRIDE + lane * SPHY_LANE, tmp); in cphy_tx_attenuation_override()
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| /openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/ |
| H A D | high_speed_env_spec.h | 68 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
69 {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
70 {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
71 {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
72 {0, 1, 2 , -1, -1, 3, -1, -1, 4}, /* Lane 4 */ \
73 {0, 1, 2 , -1, 3, -1, -1, 4, -1}, /* Lane 5 */ \
74 {0, 1, 2 , 4, -1, 3, -1, -1, -1}, /* Lane 6 */ \
75 {0, 1, -1 , 2, -1, -1, 3, -1, 4}, /* Lane 7*/ \
76 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 8 */ \
77 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 9 */ \
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| /openbmc/linux/drivers/platform/x86/intel/pmc/ |
| H A D | spt.c | 22 {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
23 {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
24 {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
25 {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
26 {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
27 {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
28 {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
29 {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
30 {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
31 {"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
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| /openbmc/linux/drivers/phy/tegra/ |
| H A D | xusb.c | 115 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane, in tegra_xusb_lane_parse_dt() argument
118 struct device *dev = &lane->pad->dev; in tegra_xusb_lane_parse_dt()
126 err = match_string(lane->soc->funcs, lane->soc->num_funcs, function); in tegra_xusb_lane_parse_dt()
128 dev_err(dev, "invalid function \"%s\" for lane \"%pOFn\"\n", in tegra_xusb_lane_parse_dt()
133 lane->function = err; in tegra_xusb_lane_parse_dt()
141 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra_xusb_lane_destroy() local
143 lane->pad->ops->remove(lane); in tegra_xusb_lane_destroy()
191 struct phy *lane; in tegra_xusb_pad_register() local
199 pad->lanes = devm_kcalloc(&pad->dev, pad->soc->num_lanes, sizeof(lane), in tegra_xusb_pad_register()
208 struct tegra_xusb_lane *lane; in tegra_xusb_pad_register() local
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| H A D | xusb-tegra124.c | 292 struct tegra_xusb_lane *lane; in tegra124_usb3_save_context() local
300 lane = port->base.lane; in tegra124_usb3_save_context()
302 if (lane->pad == padctl->pcie) in tegra124_usb3_save_context()
303 offset = XUSB_PADCTL_IOPHY_MISC_PAD_PX_CTL6(lane->index); in tegra124_usb3_save_context()
452 static void tegra124_usb2_lane_remove(struct tegra_xusb_lane *lane) in tegra124_usb2_lane_remove() argument
454 struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane); in tegra124_usb2_lane_remove()
466 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_init() local
468 return tegra124_xusb_padctl_enable(lane->pad->padctl); in tegra124_usb2_phy_init()
473 struct tegra_xusb_lane *lane = phy_get_drvdata(phy); in tegra124_usb2_phy_exit() local
475 return tegra124_xusb_padctl_disable(lane->pad->padctl); in tegra124_usb2_phy_exit()
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| H A D | xusb-tegra210.c | 447 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane) in tegra210_usb3_lane_map() argument
452 if (map->index == lane->index && in tegra210_usb3_lane_map()
453 strcmp(map->type, lane->pad->soc->name) == 0) { in tegra210_usb3_lane_map()
454 dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n", in tegra210_usb3_lane_map()
455 lane->pad->soc->lanes[lane->index].name, map->port); in tegra210_usb3_lane_map()
706 struct tegra_xusb_lane *lane = tegra_xusb_find_lane(padctl, "sata", 0); in tegra210_sata_uphy_enable() local
716 if (IS_ERR(lane)) in tegra210_sata_uphy_enable()
722 usb = tegra_xusb_lane_check(lane, "usb3-ss"); in tegra210_sata_uphy_enable()
1058 static int tegra210_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane, in tegra210_usb3_enable_phy_sleepwalk() argument
1061 struct tegra_xusb_padctl *padctl = lane->pad->padctl; in tegra210_usb3_enable_phy_sleepwalk()
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| H A D | xusb.h | 55 int tegra_xusb_lane_parse_dt(struct tegra_xusb_lane *lane,
63 to_usb3_lane(struct tegra_xusb_lane *lane) in to_usb3_lane() argument
65 return container_of(lane, struct tegra_xusb_usb3_lane, base); in to_usb3_lane()
76 to_usb2_lane(struct tegra_xusb_lane *lane) in to_usb2_lane() argument
78 return container_of(lane, struct tegra_xusb_usb2_lane, base); in to_usb2_lane()
86 to_ulpi_lane(struct tegra_xusb_lane *lane) in to_ulpi_lane() argument
88 return container_of(lane, struct tegra_xusb_ulpi_lane, base); in to_ulpi_lane()
105 to_hsic_lane(struct tegra_xusb_lane *lane) in to_hsic_lane() argument
107 return container_of(lane, struct tegra_xusb_hsic_lane, base); in to_hsic_lane()
115 to_pcie_lane(struct tegra_xusb_lane *lane) in to_pcie_lane() argument
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| /openbmc/linux/Documentation/devicetree/bindings/usb/ |
| H A D | onnn,nb7vpq904m.yaml | 54 An array of physical data lane indexes. Position determines how
57 Lane number represents the following
58 - 0 is RX2 lane
59 - 1 is TX2 lane
60 - 2 is TX1 lane
61 - 3 is RX1 lane
72 - Port A to RX2 lane
73 - Port B to TX2 lane
74 - Port C to TX1 lane
75 - Port D to RX1 lane
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| /openbmc/linux/drivers/net/dsa/mv88e6xxx/ |
| H A D | serdes.c | 37 int lane, int device, int reg, u16 *val) in mv88e6390_serdes_read() argument
39 return mv88e6xxx_phy_read_c45(chip, lane, device, reg, val); in mv88e6390_serdes_read()
244 int lane = -ENODEV; in mv88e6341_serdes_get_lane() local
251 lane = MV88E6341_PORT5_LANE; in mv88e6341_serdes_get_lane()
255 return lane; in mv88e6341_serdes_get_lane()
261 int lane = -ENODEV; in mv88e6390_serdes_get_lane() local
268 lane = MV88E6390_PORT9_LANE0; in mv88e6390_serdes_get_lane()
274 lane = MV88E6390_PORT10_LANE0; in mv88e6390_serdes_get_lane()
278 return lane; in mv88e6390_serdes_get_lane()
286 int lane = -ENODEV; in mv88e6390x_serdes_get_lane() local
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| /openbmc/linux/drivers/phy/ |
| H A D | phy-xgene.c | 268 /* PHY lane CSR accessing from SDS indirectly */
520 u32 speed[MAX_LANE]; /* Index for override parameter per lane */
658 static void serdes_wr(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 data) in serdes_wr() argument
664 reg += lane * SERDES_LANE_STRIDE; in serdes_wr()
673 static void serdes_rd(struct xgene_phy_ctx *ctx, int lane, u32 reg, u32 *data) in serdes_rd() argument
678 reg += lane * SERDES_LANE_STRIDE; in serdes_rd()
684 static void serdes_clrbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_clrbits() argument
689 serdes_rd(ctx, lane, reg, &val); in serdes_clrbits()
691 serdes_wr(ctx, lane, reg, val); in serdes_clrbits()
694 static void serdes_setbits(struct xgene_phy_ctx *ctx, int lane, u32 reg, in serdes_setbits() argument
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| /openbmc/linux/drivers/gpu/drm/i915/display/ |
| H A D | intel_cx0_phy_regs.h | 15 #define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
19 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
30 #define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \ argument
34 _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
84 #define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30)) argument
85 #define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28)) argument
86 #define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24)) argument
91 #define XELPDP_LANE_POWERDOWN_NEW_STATE(lane, val) _PICK(lane, \ argument
122 #define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4)) argument
123 #define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4)) argument
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| /openbmc/u-boot/arch/arm/mach-tegra/ |
| H A D | xusb-padctl-common.c | 129 const struct tegra_xusb_padctl_lane *lane, in tegra_xusb_padctl_lane_find_function() argument
139 for (i = 0; i < lane->num_funcs; i++) in tegra_xusb_padctl_lane_find_function()
140 if (lane->funcs[i] == func) in tegra_xusb_padctl_lane_find_function()
153 const struct tegra_xusb_padctl_lane *lane; in tegra_xusb_padctl_group_apply() local
157 lane = tegra_xusb_padctl_find_lane(padctl, group->pins[i]); in tegra_xusb_padctl_group_apply()
158 if (!lane) { in tegra_xusb_padctl_group_apply()
159 pr_err("no lane for pin %s", group->pins[i]); in tegra_xusb_padctl_group_apply()
163 func = tegra_xusb_padctl_lane_find_function(padctl, lane, in tegra_xusb_padctl_group_apply()
166 pr_err("function %s invalid for lane %s: %d", in tegra_xusb_padctl_group_apply()
167 group->func, lane->name, func); in tegra_xusb_padctl_group_apply()
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| /openbmc/linux/Documentation/devicetree/bindings/media/ |
| H A D | video-interfaces.yaml | 164 # Assume up to 9 physical lane indices
167 An array of physical data lane indexes. Position of an entry determines
168 the logical lane number, while the value of an entry indicates physical
169 lane, e.g. for 2-lane MIPI CSI-2 bus we could have "data-lanes = <1 2>;",
170 assuming the clock lane is on hardware lane 0. If the hardware does not
171 support lane reordering, monotonically incremented values shall be used
173 lane. This property is valid for serial busses only (e.g. MIPI CSI-2).
177 # Assume up to 9 physical lane indices
180 Physical clock lane index. Position of an entry determines the logical
181 lane number, while the value of an entry indicates physical lane, e.g. for
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