17 /* Lane 0 */
27 /* Lane 1 */
36 /* Lane 2 */
339 static void usb3_reg_set16(u32 reg, u16 data, u16 mask, u32 lane)  in usb3_reg_set16()  argument
342 	 * When Lane 2 PHY is for USB3, access the PHY registers  in usb3_reg_set16()
345 	 * within the SATA Host Controller registers, Lane 2 base register  in usb3_reg_set16()
349 	if (lane == 2)  in usb3_reg_set16()
361 static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)  in comphy_usb3_power_up()  argument
381 	usb3_reg_set16(LANE_CFG0, 0x1, 0xFF, lane);  in comphy_usb3_power_up()
395 		       | gen2_tx_data_dly_mask | tx_elec_idle_mode_en, lane);  in comphy_usb3_power_up()
398 	usb3_reg_set16(LANE_CFG4, bf_spread_spectrum_clock_en, 0x80, lane);  in comphy_usb3_power_up()
402 	 * from lane configuration  in comphy_usb3_power_up()
404 	usb3_reg_set16(TEST_MODE_CTRL, rb_mode_margin_override, 0xFFFF, lane);  in comphy_usb3_power_up()
406 	/* set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles */  in comphy_usb3_power_up()
408 	usb3_reg_set16(GLOB_CLK_SRC_LO, 0x0, 0xFF, lane);  in comphy_usb3_power_up()
411 	usb3_reg_set16(GEN2_SETTINGS_2, g2_tx_ssc_amp, 0xF000, lane);  in comphy_usb3_power_up()
417 	usb3_reg_set16(GEN2_SETTINGS_3, 0x0, 0xFFFF, lane);  in comphy_usb3_power_up()
426 		usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF, lane);  in comphy_usb3_power_up()
427 		usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF, lane);  in comphy_usb3_power_up()
430 		usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF, lane);  in comphy_usb3_power_up()
431 		usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF, lane);  in comphy_usb3_power_up()
437 	usb3_reg_set16(UNIT_CTRL, 0x60 | rb_idle_sync_en, 0xFFFF, lane);  in comphy_usb3_power_up()
442 	usb3_reg_set16(MISC_REG0, 0xA00D | rb_clk500m_en, 0xFFFF, lane);  in comphy_usb3_power_up()
447 	usb3_reg_set16(DIG_LB_EN, 0x0400, 0xFFFF, lane);  in comphy_usb3_power_up()
453 		       lane);  in comphy_usb3_power_up()
459 		usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);  in comphy_usb3_power_up()
462 		usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);  in comphy_usb3_power_up()
467 	usb3_reg_set16(SYNC_MASK_GEN, 0x0400, 0x0C00, lane);  in comphy_usb3_power_up()
472 	usb3_reg_set16(GEN3_SETTINGS_3, 0xF, 0xF, lane);  in comphy_usb3_power_up()
479 		       | 0x20, 0xFFFF, lane);  in comphy_usb3_power_up()
485 	if (lane == 2) {  in comphy_usb3_power_up()
663 static void comphy_sgmii_phy_init(u32 lane, u32 speed)  in comphy_sgmii_phy_init()  argument
688 		reg_set16(sgmiiphy_addr(lane, addr), val, 0xFFFF);  in comphy_sgmii_phy_init()
697 static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)  in comphy_sgmii_power_up()  argument
716 	reg_set(COMPHY_PHY_CFG1_ADDR(lane),  in comphy_sgmii_power_up()
724 	reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0, rb_pin_reset_comphy);  in comphy_sgmii_power_up()
731 		reg_set(COMPHY_PHY_CFG1_ADDR(lane),  in comphy_sgmii_power_up()
737 		reg_set(COMPHY_PHY_CFG1_ADDR(lane),  in comphy_sgmii_power_up()
753 	reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),  in comphy_sgmii_power_up()
760 	reg_set16(sgmiiphy_addr(lane, MISC_REG0), 0, rb_ref_clk_sel);  in comphy_sgmii_power_up()
767 		reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),  in comphy_sgmii_power_up()
771 		reg_set16(sgmiiphy_addr(lane, PWR_PLL_CTRL),  in comphy_sgmii_power_up()
788 	reg_set16(sgmiiphy_addr(lane, DIG_LB_EN), 0, rf_data_width_mask);  in comphy_sgmii_power_up()
814 		comphy_sgmii_phy_init(lane, speed);  in comphy_sgmii_power_up()
831 		reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);  in comphy_sgmii_power_up()
834 		reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);  in comphy_sgmii_power_up()
842 	reg_set(COMPHY_PHY_CFG1_ADDR(lane),  in comphy_sgmii_power_up()
850 	ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane),	/* address */  in comphy_sgmii_power_up()
855 		printf("Failed to lock PLL for SGMII PHY %d\n", lane);  in comphy_sgmii_power_up()
860 	reg_set(COMPHY_PHY_CFG1_ADDR(lane), 0x0, rb_pin_tx_idle);  in comphy_sgmii_power_up()
870 	reg_set(COMPHY_PHY_CFG1_ADDR(lane), rb_phy_rx_init, 0x0);  in comphy_sgmii_power_up()
872 	ret = comphy_poll_reg(COMPHY_PHY_STAT1_ADDR(lane), /* address */  in comphy_sgmii_power_up()
877 		printf("Failed to init RX of SGMII PHY %d\n", lane);  in comphy_sgmii_power_up()
970 	u32 lane, ret = 0;  in comphy_a3700_init()  local
978 	for (lane = 0, comphy_map = serdes_map; lane < comphy_max_count;  in comphy_a3700_init()
979 	     lane++, comphy_map++) {  in comphy_a3700_init()
980 		debug("Initialize serdes number %d\n", lane);  in comphy_a3700_init()
996 			ret = comphy_usb3_power_up(lane,  in comphy_a3700_init()
1004 			ret = comphy_sgmii_power_up(lane, comphy_map->speed,  in comphy_a3700_init()
1010 			      lane);  in comphy_a3700_init()
1015 			printf("PLL is not locked - Failed to initialize lane %d\n",  in comphy_a3700_init()
1016 			       lane);  in comphy_a3700_init()