129  * A lane is described by the following bitfields:
182 	unsigned lane;  member
190 		.lane = _lane,				\
200 		.lane = _lane,				\
209 	/* lane 0 */
214 	/* lane 1 */
221 	/* lane 2 */
230 	/* lane 3 */
237 	/* lane 4 */
250 	/* lane 5 */
277 			    unsigned long lane, unsigned long mode)  in mvebu_comphy_smc()  argument
282 	arm_smccc_smc(function, phys, lane, mode, 0, 0, 0, 0, &res);  in mvebu_comphy_smc()
295 static int mvebu_comphy_get_mode(bool fw_mode, int lane, int port,  in mvebu_comphy_get_mode()  argument
309 		if (conf->lane == lane &&  in mvebu_comphy_get_mode()
325 static inline int mvebu_comphy_get_mux(int lane, int port,  in mvebu_comphy_get_mux()  argument
328 	return mvebu_comphy_get_mode(false, lane, port, mode, submode);  in mvebu_comphy_get_mux()
331 static inline int mvebu_comphy_get_fw_mode(int lane, int port,  in mvebu_comphy_get_fw_mode()  argument
334 	return mvebu_comphy_get_mode(true, lane, port, mode, submode);  in mvebu_comphy_get_fw_mode()
337 static int mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane)  in mvebu_comphy_ethernet_init_reset()  argument
339 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_ethernet_init_reset()
342 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);  in mvebu_comphy_ethernet_init_reset()
345 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);  in mvebu_comphy_ethernet_init_reset()
348 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_ethernet_init_reset()
357 	switch (lane->submode) {  in mvebu_comphy_ethernet_init_reset()
379 			"unsupported comphy submode (%d) on lane %d\n",  in mvebu_comphy_ethernet_init_reset()
380 			lane->submode,  in mvebu_comphy_ethernet_init_reset()
381 			lane->id);  in mvebu_comphy_ethernet_init_reset()
385 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_ethernet_init_reset()
387 	if (lane->submode == PHY_INTERFACE_MODE_RXAUI) {  in mvebu_comphy_ethernet_init_reset()
390 		switch (lane->id) {  in mvebu_comphy_ethernet_init_reset()
401 				"RXAUI is not supported on comphy lane %d\n",  in mvebu_comphy_ethernet_init_reset()
402 				lane->id);  in mvebu_comphy_ethernet_init_reset()
410 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
414 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
417 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
420 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_ethernet_init_reset()
426 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), &val);  in mvebu_comphy_ethernet_init_reset()
428 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF6(lane->id), val);  in mvebu_comphy_ethernet_init_reset()
431 	val = readl(priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));  in mvebu_comphy_ethernet_init_reset()
433 	if (lane->submode == PHY_INTERFACE_MODE_10GBASER)  in mvebu_comphy_ethernet_init_reset()
435 	writel(val, priv->base + MVEBU_COMPHY_MISC_CTRL0(lane->id));  in mvebu_comphy_ethernet_init_reset()
438 	val = readl(priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));  in mvebu_comphy_ethernet_init_reset()
443 	writel(val, priv->base + MVEBU_COMPHY_PWRPLL_CTRL(lane->id));  in mvebu_comphy_ethernet_init_reset()
445 	val = readl(priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));  in mvebu_comphy_ethernet_init_reset()
448 	writel(val, priv->base + MVEBU_COMPHY_LOOPBACK(lane->id));  in mvebu_comphy_ethernet_init_reset()
453 static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane)  in mvebu_comphy_init_plls()  argument
455 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_init_plls()
459 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_init_plls()
463 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG0(lane->id));  in mvebu_comphy_init_plls()
466 	readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),  in mvebu_comphy_init_plls()
476 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
478 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
481 	readl_poll_timeout(priv->base + MVEBU_COMPHY_SERDES_STATUS0(lane->id),  in mvebu_comphy_init_plls()
487 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
489 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_init_plls()
496 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_set_mode_sgmii()  local
497 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_set_mode_sgmii()
501 	err = mvebu_comphy_ethernet_init_reset(lane);  in mvebu_comphy_set_mode_sgmii()
505 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_sgmii()
508 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_sgmii()
510 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_sgmii()
512 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_sgmii()
514 	regmap_read(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), &val);  in mvebu_comphy_set_mode_sgmii()
517 	regmap_write(priv->regmap, MVEBU_COMPHY_CONF1(lane->id), val);  in mvebu_comphy_set_mode_sgmii()
519 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_sgmii()
522 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_sgmii()
524 	return mvebu_comphy_init_plls(lane);  in mvebu_comphy_set_mode_sgmii()
529 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_set_mode_rxaui()  local
530 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_set_mode_rxaui()
534 	err = mvebu_comphy_ethernet_init_reset(lane);  in mvebu_comphy_set_mode_rxaui()
538 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_rxaui()
541 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_rxaui()
543 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_rxaui()
545 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_rxaui()
547 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_rxaui()
549 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_rxaui()
551 	val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_rxaui()
553 	writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_rxaui()
555 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_rxaui()
558 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_rxaui()
560 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_rxaui()
566 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_rxaui()
568 	val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_rxaui()
570 	writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_rxaui()
572 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_rxaui()
575 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_rxaui()
577 	return mvebu_comphy_init_plls(lane);  in mvebu_comphy_set_mode_rxaui()
582 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_set_mode_10gbaser()  local
583 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_set_mode_10gbaser()
587 	err = mvebu_comphy_ethernet_init_reset(lane);  in mvebu_comphy_set_mode_10gbaser()
591 	val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
594 	writel(val, priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
596 	val = readl(priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
598 	writel(val, priv->base + MVEBU_COMPHY_DTL_CTRL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
601 	val = readl(priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
603 	writel(val, priv->base + MVEBU_COMPHY_SPEED_DIV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
605 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
607 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
610 	val = readl(priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_10gbaser()
612 	writel(val, priv->base + MVEBU_COMPHY_DFE_RES(lane->id));  in mvebu_comphy_set_mode_10gbaser()
614 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
619 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
621 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
624 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S2(lane->id));  in mvebu_comphy_set_mode_10gbaser()
626 	val = readl(priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));  in mvebu_comphy_set_mode_10gbaser()
629 	writel(val, priv->base + MVEBU_COMPHY_TX_SLEW_RATE(lane->id));  in mvebu_comphy_set_mode_10gbaser()
632 	val = readl(priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
636 	writel(val, priv->base + MVEBU_COMPHY_IMP_CAL(lane->id));  in mvebu_comphy_set_mode_10gbaser()
638 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
640 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
642 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
652 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S1(lane->id));  in mvebu_comphy_set_mode_10gbaser()
654 	val = readl(priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_10gbaser()
656 	writel(val, priv->base + MVEBU_COMPHY_COEF(lane->id));  in mvebu_comphy_set_mode_10gbaser()
658 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_10gbaser()
661 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S4(lane->id));  in mvebu_comphy_set_mode_10gbaser()
663 	val = readl(priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
665 	writel(val, priv->base + MVEBU_COMPHY_GEN1_S3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
668 	val = readl(priv->base + MVEBU_COMPHY_TRAINING5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
671 	writel(val, priv->base + MVEBU_COMPHY_TRAINING5(lane->id));  in mvebu_comphy_set_mode_10gbaser()
674 	val = readl(priv->base + MVEBU_COMPHY_TRAINING0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
676 	writel(val, priv->base + MVEBU_COMPHY_TRAINING0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
678 	val = readl(priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
681 	writel(val, priv->base + MVEBU_COMPHY_TX_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
683 	val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
685 	writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT3(lane->id));  in mvebu_comphy_set_mode_10gbaser()
687 	val = readl(priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
690 	writel(val, priv->base + MVEBU_COMPHY_TX_TRAIN_PRESET(lane->id));  in mvebu_comphy_set_mode_10gbaser()
692 	val = readl(priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
695 	writel(val, priv->base + MVEBU_COMPHY_FRAME_DETECT0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
697 	val = readl(priv->base + MVEBU_COMPHY_DME(lane->id));  in mvebu_comphy_set_mode_10gbaser()
699 	writel(val, priv->base + MVEBU_COMPHY_DME(lane->id));  in mvebu_comphy_set_mode_10gbaser()
701 	val = readl(priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
703 	writel(val, priv->base + MVEBU_COMPHY_VDD_CAL0(lane->id));  in mvebu_comphy_set_mode_10gbaser()
705 	val = readl(priv->base + MVEBU_SP_CALIB(lane->id));  in mvebu_comphy_set_mode_10gbaser()
709 	writel(val, priv->base + MVEBU_SP_CALIB(lane->id));  in mvebu_comphy_set_mode_10gbaser()
711 	writel(val, priv->base + MVEBU_SP_CALIB(lane->id));  in mvebu_comphy_set_mode_10gbaser()
714 	val = readl(priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
717 	writel(val, priv->base + MVEBU_COMPHY_EXT_SELV(lane->id));  in mvebu_comphy_set_mode_10gbaser()
719 	return mvebu_comphy_init_plls(lane);  in mvebu_comphy_set_mode_10gbaser()
724 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_power_on_legacy()  local
725 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_on_legacy()
729 	mux = mvebu_comphy_get_mux(lane->id, lane->port,  in mvebu_comphy_power_on_legacy()
730 				   lane->mode, lane->submode);  in mvebu_comphy_power_on_legacy()
735 	val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));  in mvebu_comphy_power_on_legacy()
739 	val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));  in mvebu_comphy_power_on_legacy()
740 	val |= mux << MVEBU_COMPHY_SELECTOR_PHY(lane->id);  in mvebu_comphy_power_on_legacy()
743 	switch (lane->submode) {  in mvebu_comphy_power_on_legacy()
759 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_on_legacy()
761 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_on_legacy()
768 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_power_on()  local
769 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_on()
774 	fw_mode = mvebu_comphy_get_fw_mode(lane->id, lane->port,  in mvebu_comphy_power_on()
775 					   lane->mode, lane->submode);  in mvebu_comphy_power_on()
780 	switch (lane->mode) {  in mvebu_comphy_power_on()
782 		switch (lane->submode) {  in mvebu_comphy_power_on()
784 			dev_dbg(priv->dev, "set lane %d to RXAUI mode\n",  in mvebu_comphy_power_on()
785 				lane->id);  in mvebu_comphy_power_on()
789 			dev_dbg(priv->dev, "set lane %d to 1000BASE-X mode\n",  in mvebu_comphy_power_on()
790 				lane->id);  in mvebu_comphy_power_on()
794 			dev_dbg(priv->dev, "set lane %d to 2500BASE-X mode\n",  in mvebu_comphy_power_on()
795 				lane->id);  in mvebu_comphy_power_on()
799 			dev_dbg(priv->dev, "set lane %d to 5GBASE-R mode\n",  in mvebu_comphy_power_on()
800 				lane->id);  in mvebu_comphy_power_on()
804 			dev_dbg(priv->dev, "set lane %d to 10GBASE-R mode\n",  in mvebu_comphy_power_on()
805 				lane->id);  in mvebu_comphy_power_on()
810 				lane->submode);  in mvebu_comphy_power_on()
813 		fw_param = COMPHY_FW_PARAM_ETH(fw_mode, lane->port, fw_speed);  in mvebu_comphy_power_on()
817 		dev_dbg(priv->dev, "set lane %d to USB3 mode\n", lane->id);  in mvebu_comphy_power_on()
818 		fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);  in mvebu_comphy_power_on()
821 		dev_dbg(priv->dev, "set lane %d to SATA mode\n", lane->id);  in mvebu_comphy_power_on()
822 		fw_param = COMPHY_FW_PARAM(fw_mode, lane->port);  in mvebu_comphy_power_on()
825 		dev_dbg(priv->dev, "set lane %d to PCIe mode (x%d)\n", lane->id,  in mvebu_comphy_power_on()
826 			lane->submode);  in mvebu_comphy_power_on()
827 		fw_param = COMPHY_FW_PARAM_PCIE(fw_mode, lane->port,  in mvebu_comphy_power_on()
828 						lane->submode);  in mvebu_comphy_power_on()
831 		dev_err(priv->dev, "unsupported PHY mode (%d)\n", lane->mode);  in mvebu_comphy_power_on()
835 	ret = mvebu_comphy_smc(COMPHY_SIP_POWER_ON, priv->cp_phys, lane->id,  in mvebu_comphy_power_on()
846 		 lane->id, lane->mode, ret);  in mvebu_comphy_power_on()
856 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_set_mode()  local
861 	if (mvebu_comphy_get_fw_mode(lane->id, lane->port, mode, submode) < 0)  in mvebu_comphy_set_mode()
864 	lane->mode = mode;  in mvebu_comphy_set_mode()
865 	lane->submode = submode;  in mvebu_comphy_set_mode()
868 	if (mode == PHY_MODE_PCIE && !lane->submode)  in mvebu_comphy_set_mode()
869 		lane->submode = 1;  in mvebu_comphy_set_mode()
876 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_power_off_legacy()  local
877 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_off_legacy()
880 	val = readl(priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_off_legacy()
884 	writel(val, priv->base + MVEBU_COMPHY_SERDES_CFG1(lane->id));  in mvebu_comphy_power_off_legacy()
887 	val &= ~(0xf << MVEBU_COMPHY_SELECTOR_PHY(lane->id));  in mvebu_comphy_power_off_legacy()
891 	val &= ~(0xf << MVEBU_COMPHY_PIPE_SELECTOR_PIPE(lane->id));  in mvebu_comphy_power_off_legacy()
899 	struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);  in mvebu_comphy_power_off()  local
900 	struct mvebu_comphy_priv *priv = lane->priv;  in mvebu_comphy_power_off()
904 			       lane->id, 0);  in mvebu_comphy_power_off()
922 	struct mvebu_comphy_lane *lane;  in mvebu_comphy_xlate()  local
932 	lane = phy_get_drvdata(phy);  in mvebu_comphy_xlate()
933 	lane->port = args->args[0];  in mvebu_comphy_xlate()
1037 		struct mvebu_comphy_lane *lane;  in mvebu_comphy_probe()  local
1053 		lane = devm_kzalloc(&pdev->dev, sizeof(*lane), GFP_KERNEL);  in mvebu_comphy_probe()
1054 		if (!lane) {  in mvebu_comphy_probe()
1067 		lane->priv = priv;  in mvebu_comphy_probe()
1068 		lane->mode = PHY_MODE_INVALID;  in mvebu_comphy_probe()
1069 		lane->submode = PHY_INTERFACE_MODE_NA;  in mvebu_comphy_probe()
1070 		lane->id = val;  in mvebu_comphy_probe()
1071 		lane->port = -1;  in mvebu_comphy_probe()
1072 		phy_set_drvdata(phy, lane);  in mvebu_comphy_probe()