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/openbmc/linux/Documentation/devicetree/bindings/iio/multiplexer/
H A Dio-channel-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/multiplexer/io-channel-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: I/O channel multiplexer
10 - Peter Rosin <peda@axentia.se>
14 e.g. an ADC channel, these bindings describe that situation.
16 For each non-empty string in the channels property, an io-channel will be
17 created. The number of this io-channel is the same as the index into the list
18 of strings in the channels property, and also matches the mux controller
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-ampere-mtjade.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
3 #include "aspeed-g5.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
8 compatible = "ampere,mtjade-bmc", "aspeed,ast2500";
12 * i2c bus 50-57 assigned to NVMe slot 0-7
24 * i2c bus 60-67 assigned to NVMe slot 8-15
36 * i2c bus 70-77 assigned to NVMe slot 16-23
48 * i2c bus 80-81 assigned to NVMe M2 slot 0-1
60 stdout-path = &uart5;
[all …]
H A Daspeed-bmc-ampere-mtmitchell.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/i2c/i2c.h>
8 #include <dt-bindings/gpio/aspeed-gpio.h>
12 compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600";
27 * i2c bus 30-31 assigned to OCP slot 0-1
33 * i2c bus 32-33 assigned to Riser slot 0-1
39 * i2c bus 38-39 assigned to FRU on Riser slot 0-1
82 stdout-path = &uart5;
[all …]
H A Daspeed-bmc-ampere-mtjefferson.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/i2c/i2c.h>
8 #include <dt-bindings/gpio/aspeed-gpio.h>
12 compatible = "ampere,mtjefferson-bmc", "aspeed,ast2600";
41 stdout-path = &uart5;
49 reserved-memory {
50 #address-cells = <1>;
51 #size-cells = <1>;
[all …]
H A Daspeed-bmc-ibm-system1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /dts-v1/;
5 #include "aspeed-g6.dtsi"
6 #include <dt-bindings/gpio/aspeed-gpio.h>
7 #include <dt-bindings/i2c/i2c.h>
8 #include <dt-bindings/leds/leds-pca955x.h>
12 compatible = "ibm,system1-bmc", "aspeed,ast2600";
74 stdout-path = "uart5:115200n8";
82 reserved-memory {
83 #address-cells = <1>;
[all …]
H A Daspeed-bmc-facebook-elbert.dts1 // SPDX-License-Identifier: GPL-2.0+
4 /dts-v1/;
6 #include "ast2600-facebook-netbmc-common.dtsi"
10 compatible = "facebook,elbert-bmc", "aspeed,ast2600";
19 * 8 child channels of PCA9548 2-0075.
31 * 8 child channels of PCA9548 5-0075.
44 stdout-path = &uart5;
48 num-chipselects = <1>;
49 cs-gpios = <&gpio0 ASPEED_GPIO(X, 0) GPIO_ACTIVE_LOW>;
59 aspeed,lpc-io-reg = <0xca8>;
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-natte.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-natte.dts - Device Tree include file for the Natte board
11 mux: mux-controller { label
12 compatible = "gpio-mux";
13 #mux-control-cells = <0>;
15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
20 batntc-mux {
21 compatible = "io-channel-mux";
22 io-channels = <&adc 5>;
23 io-channel-names = "parent";
[all …]
H A Dat91-tse850-3.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91-tse850-3.dts - Device Tree file for the Axentia TSE-850 3.0 board
9 /dts-v1/;
10 #include <dt-bindings/pwm/pwm.h>
11 #include "at91-linea.dtsi"
14 model = "Axentia TSE-850 3.0";
19 compatible = "fixed-clock";
21 #clock-cells = <0>;
22 clock-frequency = <16000000>;
23 clock-output-names = "sck";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mux/
H A Dadi,adg792a.txt4 - compatible : "adi,adg792a" or "adi,adg792g"
5 - #mux-control-cells : <0> if parallel (the three muxes are bound together
6 with a single mux controller controlling all three muxes), or <1> if
7 not (one mux controller for each mux).
8 * Standard mux-controller bindings as described in mux-controller.yaml
11 - gpio-controller : if present, #gpio-cells below is required.
12 - #gpio-cells : should be <2>
13 - First cell is the GPO line number, i.e. 0 or 1
14 - Second cell is used to specify active high (0)
18 - idle-state : if present, array of states that the mux controllers will have
[all …]
H A Dmux-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
13 A multiplexer (or mux) controller will have one, or several, consumer devices
14 that uses the mux controller. Thus, a mux controller can possibly control
16 multiplexer needed by each consumer, but a single mux controller can of course
19 A mux controller provides a number of states to its consumers, and the state
20 space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
[all …]
H A Dadi,adgs1408.txt1 Bindings for Analog Devices ADGS1408/1409 8:1/Dual 4:1 Mux
4 - compatible : Should be one of
7 * Standard mux-controller bindings as described in mux-controller.yaml
10 - gpio-controller : if present, #gpio-cells is required.
11 - #gpio-cells : should be <2>
12 - First cell is the GPO line number, i.e. 0 to 3
14 - Second cell is used to specify active high (0)
18 - idle-state : if present, the state that the mux controller will have
28 * One mux controller.
29 * Mux state set to idle as is (no idle-state declared)
[all …]
H A Dgpio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/gpio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
22 const: gpio-mux
24 mux-gpios:
28 '#mux-control-cells':
31 '#mux-state-cells':
[all …]
/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
[all …]
H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
[all …]
H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
[all …]
/openbmc/linux/drivers/i2c/muxes/
H A Di2c-mux-mlxcpld.c1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
3 * Mellanox i2c mux driver
5 * Copyright (C) 2016-2020 Mellanox Technologies
10 #include <linux/i2c-mux.h>
11 #include <linux/io.h>
18 /* mlxcpld_mux - mux control structure:
19 * @last_val - last selected register value or -1 if mux deselected
20 * @client - I2C device client
29 /* MUX logic description.
30 * Driver can support different mux control logic, according to CPLD
[all …]
/openbmc/linux/arch/arm64/boot/dts/rockchip/
H A Drk3326-odroid-go3.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 /dts-v1/;
9 #include "rk3326-odroid-go.dtsi"
12 model = "ODROID-GO Super";
13 compatible = "hardkernel,rk3326-odroid-go3", "rockchip,rk3326";
15 joystick_mux_controller: mux-controller {
16 compatible = "gpio-mux";
18 #mux-control-cells = <0>;
20 mux-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>,
24 joystick_mux: adc-mux {
[all …]
H A Drk3566-anbernic-rgxx3.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 /dts-v1/;
5 #include <dt-bindings/gpio/gpio.h>
6 #include <dt-bindings/input/linux-event-codes.h>
7 #include <dt-bindings/leds/common.h>
8 #include <dt-bindings/pinctrl/rockchip.h>
9 #include <dt-bindings/soc/rockchip,vop2.h>
14 stdout-path = "serial2:1500000n8";
17 adc-joystick {
18 compatible = "adc-joystick";
[all …]
/openbmc/u-boot/drivers/i2c/muxes/
H A Di2c-mux-gpio.c1 // SPDX-License-Identifier: GPL-2.0+
10 #include <asm/io.h>
11 #include <asm-generic/gpio.h>
22 * struct i2c_mux_gpio_priv - private data for i2c mux gpio
26 * @gpios: the mux-gpios array
27 * @n_gpios: num of gpios in mux-gpios
28 * @idle: the value of idle-state
40 uint channel) in i2c_mux_gpio_select() argument
45 for (i = 0; i < priv->n_gpios; i++) { in i2c_mux_gpio_select()
46 ret = dm_gpio_set_value(&priv->gpios[i], (channel >> i) & 1); in i2c_mux_gpio_select()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dqcom,pm8018-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/qcom,pm8018-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Linus Walleij <linus.walleij@linaro.org>
19 - qcom,pm8018-adc
20 - qcom,pm8038-adc
21 - qcom,pm8058-adc
22 - qcom,pm8921-adc
29 xoadc-ref-supply:
[all …]
/openbmc/linux/drivers/iio/multiplexer/
H A Diio-mux.c1 // SPDX-License-Identifier: GPL-2.0
16 #include <linux/mux/consumer.h>
29 struct mux { struct
40 static int iio_mux_select(struct mux *mux, int idx) in iio_mux_select() argument
42 struct mux_child *child = &mux->child[idx]; in iio_mux_select()
43 struct iio_chan_spec const *chan = &mux->chan[idx]; in iio_mux_select()
47 ret = mux_control_select_delay(mux->control, chan->channel, in iio_mux_select()
48 mux->delay_us); in iio_mux_select()
50 mux->cached_state = -1; in iio_mux_select()
54 if (mux->cached_state == chan->channel) in iio_mux_select()
[all …]
/openbmc/u-boot/drivers/video/sunxi/
H A Dsunxi_de2.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <asm/io.h>
20 #include <dm/device-internal.h>
21 #include <dm/uclass-internal.h>
50 clrsetbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_PLL_MASK, in sunxi_de2_composer_init()
54 setbits_le32(&ccm->ahb_reset1_cfg, 1 << AHB_RESET_OFFSET_DE); in sunxi_de2_composer_init()
55 setbits_le32(&ccm->ahb_gate1, 1 << AHB_GATE_OFFSET_DE); in sunxi_de2_composer_init()
58 setbits_le32(&ccm->de_clk_cfg, CCM_DE2_CTRL_GATE); in sunxi_de2_composer_init()
61 static void sunxi_de2_mode_set(int mux, const struct display_timing *mode, in sunxi_de2_mode_set() argument
64 ulong de_mux_base = (mux == 0) ? in sunxi_de2_mode_set()
[all …]
/openbmc/linux/drivers/pwm/
H A Dpwm-meson.c1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
13 * Setting the duty cycle will disable and re-enable the PWM output.
19 * https://dl.khadas.com/Hardware/VIM2/Datasheet/S912_Datasheet_V0.220170314publicversion-Wesion.pdf
23 * https://dn.odroid.com/S922X/ODROID-N2/Datasheet/S922X_Public_Datasheet_V0.2.pdf
33 #include <linux/clk-provider.h>
35 #include <linux/io.h>
93 struct clk_mux mux; member
124 struct meson_pwm_channel *channel = &meson->channels[pwm->hwpwm]; in meson_pwm_request() local
125 struct device *dev = chip->dev; in meson_pwm_request()
128 err = clk_prepare_enable(channel->clk); in meson_pwm_request()
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6dl-prtvt7.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6 /dts-v1/;
8 #include "imx6qdl-prti6q.dtsi"
9 #include <dt-bindings/display/sdtv-standards.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/leds/common.h>
12 #include <dt-bindings/sound/fsl-imx-audmux.h>
23 backlight_lcd: backlight-lcd {
24 compatible = "pwm-backlight";
26 brightness-levels = <0 20 81 248 1000>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra124-dpaux.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra124-dpaux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
15 pins which can be assigned to either the DPAUX channel or to an I2C
20 AUX channel.
24 pattern: "^dpaux@[0-9a-f]+$"
28 - enum:
[all …]

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