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/openbmc/linux/drivers/media/i2c/
H A Dccs-pll.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * drivers/media/i2c/ccs-pll.h
17 /* CSI-2 or CCP-2 */
22 /* op pix clock is for all lanes in total normally */
37 * struct ccs_pll_branch_fr - CCS PLL configuration (front)
39 * A single branch front-end of the CCS PLL tree.
41 * @pre_pll_clk_div: Pre-PLL clock divisor
43 * @pll_ip_clk_freq_hz: PLL input clock frequency
44 * @pll_op_clk_freq_hz: PLL output clock frequency
54 * struct ccs_pll_branch_bk - CCS PLL configuration (back)
[all …]
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-starfive-visionfive-2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include "jh7110-pinfunc.h"
10 #include <dt-bindings/gpio/gpio.h>
26 stdout-path = "serial0:115200n8";
30 timebase-frequency = <4000000>;
38 gpio-restart {
39 compatible = "gpio-restart";
46 clock-frequency = <74250000>;
50 clock-frequency = <125000000>;
[all …]
H A Djh7100-common.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/leds/common.h>
11 #include <dt-bindings/pinctrl/pinctrl-starfive-jh7100.h>
19 stdout-path = "serial0:115200n8";
23 timebase-frequency = <6250000>;
32 compatible = "gpio-leds";
34 led-ack {
38 linux,default-trigger = "heartbeat";
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8186-evb.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
5 /dts-v1/;
10 chassis-type = "embedded";
11 compatible = "mediatek,mt8186-evb", "mediatek,mt8186";
18 stdout-path = "serial0:921600n8";
30 clock-frequency = <400000>;
31 pinctrl-names = "default";
32 pinctrl-0 = <&i2c0_pins>;
38 clock-frequency = <400000>;
39 i2c-scl-internal-delay-ns = <8000>;
[all …]
H A Dmt8183-pumpkin.dts1 // SPDX-License-Identifier: GPL-2.0
7 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
16 compatible = "mediatek,mt8183-pumpkin", "mediatek,mt8183";
28 stdout-path = "serial0:921600n8";
31 reserved-memory {
32 #address-cells = <2>;
33 #size-cells = <2>;
37 compatible = "shared-dma-pool";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dqoriq-clock.txt1 * Clock Block on Freescale QorIQ Platforms
3 Freescale QorIQ chips take primary clocking input from the external
4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using
14 --------------- -------------
18 1. Clock Block Binding
21 - compatible: Should contain a chip-specific clock block compatible
22 string and (if applicable) may contain a chassis-version clock
25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as:
26 * "fsl,p2041-clockgen"
27 * "fsl,p3041-clockgen"
[all …]
/openbmc/linux/drivers/staging/sm750fb/
H A Dddk750_chip.c1 // SPDX-License-Identifier: GPL-2.0
52 * This function set up the main chip clock.
54 * Input: Frequency to be set.
56 static void set_chip_clock(unsigned int frequency) in set_chip_clock() argument
60 /* Cheok_0509: For SM750LE, the chip clock is fixed. Nothing to set. */ in set_chip_clock()
64 if (frequency) { in set_chip_clock()
68 pll.input_freq = DEFAULT_INPUT_CLOCK; /* Defined in CLOCK.H */ in set_chip_clock()
74 * up the exact clock required by the User. in set_chip_clock()
76 * possible clock. in set_chip_clock()
78 sm750_calc_pll_value(frequency, &pll); in set_chip_clock()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/i2c/
H A Daptina,mt9p031.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Aptina 1/2.5-Inch 5Mp CMOS Digital Image Sensor
10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
13 The Aptina MT9P031 is a 1/2.5-inch CMOS active pixel digital image sensor
15 simple two-wire serial interface.
20 - aptina,mt9p006
21 - aptina,mt9p031
22 - aptina,mt9p031m
[all …]
/openbmc/u-boot/drivers/firmware/
H A Dti_sci.h1 /* SPDX-License-Identifier: BSD-3-Clause */
9 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
34 /* Clock requests */
54 * struct ti_sci_msg_hdr - Generic Message Header for All messages and responses
75 * struct ti_sci_secure_msg_hdr - Header that prefixes all TISCI messages sent
86 * struct ti_sci_msg_resp_version - Response for a message
108 * struct ti_sci_msg_req_reboot - Reboot the SoC
119 * struct ti_sci_msg_board_config - Board configuration message
137 * struct ti_sci_msg_req_set_device_state - Set the desired state of the device
144 * + MSG_FLAG_DEVICE_WAKE_ENABLED - Configure the device to be a wake source.
[all …]
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-pegatron-chagall.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/input/gpio-keys.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/thermal/thermal.h>
9 #include "tegra30-cpu-opp.dtsi"
10 #include "tegra30-cpu-opp-microvolt.dtsi"
11 #include "tegra30-asus-lvds-display.dtsi"
16 chassis-type = "tablet";
35 * pre-existing /chosen node to be available to insert the
[all …]
H A Dtegra30-asus-tf300tg.dts1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include "tegra30-asus-transformer-common.dtsi"
5 #include "tegra30-asus-lvds-display.dtsi"
12 tf300tg-init-hog {
13 gpio-hog;
28 output-low;
39 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
47 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
55 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
[all …]
/openbmc/u-boot/doc/device-tree-bindings/clock/
H A Dst,stm32h7-rcc.txt1 STMicroelectronics STM32H7 Reset and Clock Controller
4 The RCC IP is both a reset and a clock controller.
6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11 "st,stm32h743-rcc"
13 - reg: should be register base and length as documented in the
16 - #reset-cells: 1, see below
18 - #clock-cells : from common clock binding; shall be set to 1
20 - clocks: External oscillator clock phandle
21 - high speed external clock signal (HSE)
[all …]
/openbmc/u-boot/drivers/clk/sifive/
H A Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
24 * The bulk of this code is primarily useful for clock configurations
25 * that must operate at arbitrary rates, as opposed to clock configurations
27 * pre-determined set of performance points.
30 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
31 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
39 #include "analogbits-wrpll-cln28hpc.h"
41 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
44 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
47 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
[all …]
/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Demac_defs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
7 * ----------------------------------------------------------------------------
11 * TI DaVinci (DM644X) EMAC peripheral driver header for DV-EVM
15 * ----------------------------------------------------------------------------
18 * ver. 1.0: Sep 2005, TI PSP Team - Created EMAC version for uBoot.
51 /* MDIO module input frequency */
53 /* MDIO clock output frequency */
56 /* MDIO module input frequency */
58 /* MDIO clock output frequency */
61 /* MDIO module input frequency */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/imu/
H A Dadi,adis16480.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Alexandru Tachici <alexandru.tachici@analog.com>
15 - adi,adis16375
16 - adi,adis16480
17 - adi,adis16485
18 - adi,adis16488
19 - adi,adis16490
20 - adi,adis16495-1
[all …]
/openbmc/linux/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
13 * The bulk of this code is primarily useful for clock configurations
14 * that must operate at arbitrary rates, as opposed to clock configurations
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
34 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dr8a7790-stout.dts1 // SPDX-License-Identifier: GPL-2.0
8 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
23 stdout-path = "serial0:115200n8";
32 compatible = "gpio-leds";
47 fixedregulator3v3: regulator-3v3 {
48 compatible = "regulator-fixed";
49 regulator-name = "fixed-3.3V";
50 regulator-min-microvolt = <3300000>;
[all …]
H A Dr8a7792-blanche.dts1 // SPDX-License-Identifier: GPL-2.0
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
25 stdout-path = "serial0:115200n8";
33 d3_3v: regulator-3v3 {
34 compatible = "regulator-fixed";
35 regulator-name = "D3.3V";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
[all …]
H A Dr8a7791-porter.dts1 // SPDX-License-Identifier: GPL-2.0
9 * SSI-AK4642
11 * JP3: 2-1: AK4642
12 * 2-3: ADV7511
19 /dts-v1/;
21 #include <dt-bindings/gpio/gpio.h>
35 stdout-path = "serial0:115200n8";
48 vcc_sdhi0: regulator-vcc-sdhi0 {
49 compatible = "regulator-fixed";
51 regulator-name = "SDHI0 Vcc";
[all …]
/openbmc/u-boot/doc/device-tree-bindings/serial/
H A Dsnps-dw-apb-uart.txt4 - compatible : "snps,dw-apb-uart"
5 - reg : offset and length of the register set for the device.
6 - interrupts : should contain uart interrupt.
8 Clock handling:
9 The clock rate of the input clock needs to be supplied by one of
10 - clock-frequency : the input clock frequency for the UART.
11 - clocks : phandle to the input clock
13 The supplying peripheral clock can also be handled, needing a second property
14 - clock-names: tuple listing input clock names.
18 - snps,uart-16550-compatible : reflects the value of UART_16550_COMPATIBLE
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Dcirrus,lochnagar.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of
25 [2] include/dt-bindings/pinctrl/lochnagar.h
26 [3] include/dt-bindings/clock/lochnagar.h
28 And these documents for the required sub-node binding details:
29 [4] Clock: ../clock/cirrus,lochnagar.yaml
35 - if:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dcc770.txt8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency of the external oscillator
20 clock in Hz. Note that the internal clock frequency used by the
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
31 - bosch,disconnect-rx0-input : see data sheet.
33 - bosch,disconnect-rx1-input : see data sheet.
35 - bosch,disconnect-tx1-output : see data sheet.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,admv1014.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,admv1014.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 24 GHz to 44 GHz frequency range.
21 - adi,admv1014
26 spi-max-frequency:
32 clock-names:
34 - const: lo_in
[all …]
H A Dadi,admv1013.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,admv1013.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 24 GHz to 44 GHz frequency range.
21 - adi,admv1013
26 spi-max-frequency:
31 Definition of the external clock.
34 clock-names:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi_oc_tiny.txt4 - compatible : should be "opencores,tiny-spi-rtlsvn2".
5 - gpios : should specify GPIOs used for chipselect.
7 - clock-frequency : input clock frequency to the core.
8 - baud-width: width, in bits, of the programmable divider used to scale
9 the input clock to SCLK.
11 The clock-frequency and baud-width properties are needed only if the divider

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