device-tree-bindings/clock/st%2Cstm32h7-rcc.txt

1 STMicroelectronics STM32H7 Reset and Clock Controller
4 The RCC IP is both a reset and a clock controller.
6 Please refer to clock-bindings.txt for common clock controller binding usage.
10 - compatible: Should be:
11   "st,stm32h743-rcc"
13 - reg: should be register base and length as documented in the
16 - #reset-cells: 1, see below
18 - #clock-cells : from common clock binding; shall be set to 1
20 - clocks: External oscillator clock phandle
21   - high speed external clock signal (HSE)
22   - low speed external clock signal (LSE)
23   - external I2S clock (I2S_CKIN)
25 - st,syscfg: phandle for pwrcfg, mandatory to disable/enable backup domain
26   write protection (RTC clock).
28 - pll x node: Allow to register a pll with specific parameters.
34 		#reset-cells = <1>;
35 		#clock-cells = <2>
36 		compatible = "st,stm32h743-rcc", "st,stm32-rcc";
42 		#address-cells = <1>;
43 		#size-cells = <0>;
46 			#clock-cells = <0>;
52 			#clock-cells = <0>;
55 			st,clock-div = <2>;
56 			st,clock-mult = <40>;
57 			st,frac-status = <0>;
66 -----------
70   Vref    ---------       --------
71     ---->| / DIVM  |---->| x DIVN | ------> VCO
72           ---------       --------
75 	                  -------
77 		          -------
80 - VCO = ( Vref / DIVM ) * DIVN
83 - VCO = ( Vref / DIVM ) * ( DIVN + FRACN / 2^13)
87 - compatible: Should be:
90 - #clock-cells: from common clock binding; shall be set to 0
91 - reg: Should be the pll number.
94 - st,clock-div:  DIVM division factor       : <1..63>
95 - st,clock-mult: DIVN multiplication factor : <4..512>
97 - st,frac-status:
98    - 0 Pll is configured in integer mode
99    - 1 Pll is configure in fractional mode
101 - st,frac: Fractional part of the multiplication factor : <0..8191>
103 - st,vcosel: VCO selection
104   - 0: Wide VCO range:192 to 836 MHz
105   - 1: Medium VCO range:150 to 420 MHz
107 - st,pllrge: PLL input frequency range
108   - 0: The PLL input (Vref / DIVM) clock range frequency is between 1 and 2 MHz
109   - 1: The PLL input (Vref / DIVM) clock range frequency is between 2 and 4 MHz
110   - 2: The PLL input (Vref / DIVM) clock range frequency is between 4 and 8 MHz
111   - 3: The PLL input (Vref / DIVM) clock range frequency is between 8 and 16 MHz
114 The peripheral clock consumer should specify the desired clock by
115 having the clock ID in its "clocks" phandle cell.
118 dt-bindings/clock/stm32h7-clks.h header and can be used in device
124 			compatible = "st,stm32-timer";
145 All available preprocessor macros for reset are defined dt-bindings//mfd/stm32h7-rcc.h