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/openbmc/linux/drivers/clk/rockchip/
H A Dclk-mmc-phase.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
58 raw_value = readl(mmc_clock->reg) >> (mmc_clock->shift); in rockchip_mmc_get_phase()
82 u32 delay; in rockchip_mmc_set_phase() local
98 return -EINVAL; in rockchip_mmc_set_phase()
105 * Due to the inexact nature of the "fine" delay, we might in rockchip_mmc_set_phase()
106 * actually go non-monotonic. We don't go _too_ monotonic in rockchip_mmc_set_phase()
113 * On one extreme (if delay is actually 44ps): in rockchip_mmc_set_phase()
115 * The other (if delay is actually 77ps): in rockchip_mmc_set_phase()
[all …]
/openbmc/linux/drivers/clk/mmp/
H A Dclk-apbc.c1 // SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/delay.h>
27 unsigned int delay; member
42 if (apbc->lock) in clk_apbc_prepare()
43 spin_lock_irqsave(apbc->lock, flags); in clk_apbc_prepare()
45 data = readl_relaxed(apbc->base); in clk_apbc_prepare()
46 if (apbc->flags & APBC_POWER_CTRL) in clk_apbc_prepare()
49 writel_relaxed(data, apbc->base); in clk_apbc_prepare()
51 if (apbc->lock) in clk_apbc_prepare()
52 spin_unlock_irqrestore(apbc->lock, flags); in clk_apbc_prepare()
[all …]
H A Dclk-gate.c1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/clk-provider.h>
13 #include <linux/delay.h>
31 if (gate->lock) in mmp_clk_gate_enable()
32 spin_lock_irqsave(gate->lock, flags); in mmp_clk_gate_enable()
34 tmp = readl(gate->reg); in mmp_clk_gate_enable()
35 tmp &= ~gate->mask; in mmp_clk_gate_enable()
36 tmp |= gate->val_enable; in mmp_clk_gate_enable()
37 writel(tmp, gate->reg); in mmp_clk_gate_enable()
39 if (gate->lock) in mmp_clk_gate_enable()
[all …]
/openbmc/openbmc/poky/meta/recipes-devtools/strace/strace/
H A Dskip-load.patch4 Subject: [PATCH] strace: skip a number of load-sensitive tests
9 Upstream-Status: Inappropriate
10 Signed-off-by: Ross Burton <ross.burton@arm.com>
11 ---
13 tests/delay.test | 1 +
14 tests/strace-r.test | 1 +
17 diff --git a/tests/clock_nanosleep.gen.test b/tests/clock_nanosleep.gen.test
19 --- a/tests/clock_nanosleep.gen.test
21 @@ -1,4 +1,5 @@
22 #!/bin/sh -efu
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/openbmc/linux/Documentation/devicetree/bindings/display/panel/
H A Dsamsung,s6e8aa0.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrzej Hajda <a.hajda@samsung.com>
13 - $ref: panel-common.yaml#
20 reset-gpios: true
21 display-timings: true
23 vdd3-supply:
26 vci-supply:
29 power-on-delay:
[all …]
/openbmc/u-boot/drivers/net/phy/
H A Dmiiphybb.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Luigi 'Comio' Mantellini <luigi.mantellini@idf-hit.com>
11 * This provides a bit-banged interface to the ethernet MII management
94 .init = bb_mii_init_wrap,
100 .delay = bb_delay_wrap,
115 BB_MII_RELOCATE(bb_miiphy_buses[i].init, gd->reloc_off); in bb_miiphy_init()
116 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_active, gd->reloc_off); in bb_miiphy_init()
117 BB_MII_RELOCATE(bb_miiphy_buses[i].mdio_tristate, gd->reloc_off); in bb_miiphy_init()
118 BB_MII_RELOCATE(bb_miiphy_buses[i].set_mdio, gd->reloc_off); in bb_miiphy_init()
119 BB_MII_RELOCATE(bb_miiphy_buses[i].get_mdio, gd->reloc_off); in bb_miiphy_init()
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/openbmc/linux/tools/testing/selftests/netfilter/
H A Dconntrack_sctp_collision.sh2 # SPDX-License-Identifier: GPL-2.0
6 # 14:35:47.655279 IP CLIENT_IP.PORT > SERVER_IP.PORT: sctp (1) [INIT] [init tag: 2017837359]
7 # 14:35:48.353250 IP SERVER_IP.PORT > CLIENT_IP.PORT: sctp (1) [INIT] [init tag: 1187206187]
8 # 14:35:48.353275 IP CLIENT_IP.PORT > SERVER_IP.PORT: sctp (1) [INIT ACK] [init tag: 2017837359]
11 # 14:35:48.855335 IP SERVER_IP.PORT > CLIENT_IP.PORT: sctp (1) [INIT ACK] [init tag: 164579970]
13 # TOPO: SERVER_NS (link0)<--->(link1) ROUTER_NS (link2)<--->(link3) CLIENT_NS
15 CLIENT_NS=$(mktemp -u client-XXXXXXXX)
19 SERVER_NS=$(mktemp -u server-XXXXXXXX)
23 ROUTER_NS=$(mktemp -u router-XXXXXXXX)
32 ip -n $SERVER_NS link add link0 type veth peer name link1 netns $ROUTER_NS
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/openbmc/openbmc/poky/meta/lib/oeqa/sdk/buildtools-cases/
H A Dbuild.py4 # SPDX-License-Identifier: MIT
18 with tempfile.TemporaryDirectory(prefix='bitbake-build-', dir=self.tc.sdk_dir) as testdir:
21 self._run('. %s/oe-init-build-env %s' % (corebase, testdir))
27 self._run('. %s/oe-init-build-env %s && bitbake virtual/libc' % (corebase, testdir))
29 delay = 10
30 …while delay and (os.path.exists(testdir + "/bitbake.lock") or os.path.exists(testdir + "/cache/has…
32 delay = delay - 1
/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/
H A Ddwmac-meson8b.c1 // SPDX-License-Identifier: GPL-2.0-only
10 #include <linux/clk-provider.h>
35 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where 8ns are exactly one
57 * the automatically delay and skew automatically (internally).
60 /* An internal counter based on the "timing-adjustment" clock. The counter is
62 * delay (= the counter value) when to start sampling RXEN and RXD[3:0].
66 * large input delay, the bit for that signal (RXEN = bit 0, RXD[3] = bit 1,
67 * ...) can be configured to be 1 to compensate for a delay of about 1ns.
73 /* Defined for adding a delay to the input RX_CLK for better timing.
112 data = readl(dwmac->regs + reg); in meson8b_dwmac_mask_bits()
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/openbmc/u-boot/drivers/usb/host/
H A Dehci-tegra.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (c) 2009-2015 NVIDIA Corporation
12 #include <asm-generic/gpio.h>
14 #include <asm/arch-tegra/usb.h>
15 #include <asm/arch-tegra/clk_rst.h>
41 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
42 PARAM_STABLE_COUNT, /* PLL-U STABLE count */
43 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
44 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
45 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
[all …]
H A Dehci-omap.c1 // SPDX-License-Identifier: GPL-2.0+
4 * (C) Copyright 2004-2008
20 #include <asm/ehci-omap.h>
33 rev = readl(&uhh->rev); in omap_uhh_reset()
36 writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc); in omap_uhh_reset()
41 while (!(readl(&uhh->syss) & 0x1)) { in omap_uhh_reset()
44 return -1; in omap_uhh_reset()
50 /* Set No-Idle, No-Standby */ in omap_uhh_reset()
51 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc); in omap_uhh_reset()
59 while ((readl(&uhh->sysc) & 0x1)) { in omap_uhh_reset()
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/openbmc/linux/drivers/clk/imx/
H A Dclk-lpcg-scu.c1 // SPDX-License-Identifier: GPL-2.0+
8 #include <linux/clk-provider.h>
9 #include <linux/delay.h>
16 #include "clk-scu.h"
25 * struct clk_lpcg_scu - Description of LPCG clock
46 /* e10858 -LPCG clock gating register synchronization errata */
54 * through the interconnect is longer than the minimum delay in lpcg_e10858_writel()
56 * Adding a readl will provide sufficient delay to prevent in lpcg_e10858_writel()
57 * back-to-back writes. in lpcg_e10858_writel()
77 reg = readl_relaxed(clk->reg); in clk_lpcg_scu_enable()
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/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_axp_training_static.h1 /* SPDX-License-Identifier: GPL-2.0 */
10 * STATIC_TRAINING - Set only if static parameters for training are set and
60 {0x0000153C, 0x0000000F}, /*Read Data Ready Delay Register */
62 /*init DRAM */
133 {0x0000153C, 0x00000011}, /*Read Data Ready Delay Register */
135 /*init DRAM */
187 {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
189 /*init DRAM */
240 {0x0000153C, 0x0000000A}, /*Read Data Ready Delay Register */
242 /*init DRAM */
[all …]
/openbmc/linux/drivers/clk/sunxi/
H A Dclk-mod0.c1 // SPDX-License-Identifier: GPL-2.0-or-later
9 #include <linux/clk-provider.h>
15 #include "clk-factors.h"
18 * sun4i_a10_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
29 if (req->rate > req->parent_rate) in sun4i_a10_get_mod0_factors()
30 req->rate = req->parent_rate; in sun4i_a10_get_mod0_factors()
32 div = DIV_ROUND_UP(req->parent_rate, req->rate); in sun4i_a10_get_mod0_factors()
45 req->rate = (req->parent_rate >> calcp) / calcm; in sun4i_a10_get_mod0_factors()
46 req->m = calcm - 1; in sun4i_a10_get_mod0_factors()
47 req->p = calcp; in sun4i_a10_get_mod0_factors()
[all …]
/openbmc/linux/arch/mips/boot/dts/cavium-octeon/
H A Docteon_3xxx.dts1 // SPDX-License-Identifier: GPL-2.0
6 * use. Because of this, it contains a super-set of the available
15 phy0: ethernet-phy@0 {
17 marvell,reg-init =
21 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
22 /* irq, blink-activity, blink-link */
23 <3 0x10 0 0x0242>; /* Reg 3,16 <- 0x0242 */
27 phy1: ethernet-phy@1 {
29 marvell,reg-init =
33 <3 0x11 0 0x442a>, /* Reg 3,17 <- 0442a */
[all …]
/openbmc/u-boot/arch/arm/mach-aspeed/ast2400/
H A Dplatform.S9 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 * EC1. Modify DQIDLY and DQSI-MCLK2X calibration algorithm
28 * EC6. Remove AST2300-A0 PCI-e workaround
31 * EC9. Add DRAM size auto-detection
36 * EC1. Add solution of LPC lock issue due to watchdog reset. (AP note A2300-11)
41 * 1. Change init value of MCR18[4] from '1' to '0'
45 * EC1. Add DQS input gating window delay tuning (1/2 T) when CBR retry
49 * EC1. Modify DDR2 init preliminary size to 1Gbit, and BL=4.
63 * EC1. Default assign X-DMA engine to VGA memory domain, MCR08[16] = 1.
67 * CONFIG_DRAM_336 // 336MHz (DDR-667)
[all …]
/openbmc/linux/drivers/clk/
H A Dclk-palmas.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (c) 2013-2014 Texas Instruments, Inc.
13 #include <linux/clk-provider.h>
30 int delay; member
57 ret = palmas_update_bits(cinfo->palmas, PALMAS_RESOURCE_BASE, in palmas_clks_prepare()
58 cinfo->clk_desc->control_reg, in palmas_clks_prepare()
59 cinfo->clk_desc->enable_mask, in palmas_clks_prepare()
60 cinfo->clk_desc->enable_mask); in palmas_clks_prepare()
62 dev_err(cinfo->dev, "Reg 0x%02x update failed, %d\n", in palmas_clks_prepare()
63 cinfo->clk_desc->control_reg, ret); in palmas_clks_prepare()
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/openbmc/openbmc/meta-ibm/recipes-phosphor/fans/fan-watchdog/
H A Dreset-fan-watchdog.service3 Wants=phosphor-fan-monitor-init@0.service
4 Before=phosphor-fan-monitor-init@0.service
5 Conflicts=obmc-chassis-poweroff@0.target
10 EnvironmentFile={envfiledir}/obmc/fan-watchdog/reset-fan-watchdog.conf
11 ExecStart=/usr/bin/gpioset --mode=time -u ${{DELAY}} ${{GPIO_PATH}} ${{GPIO}}=0
12 ExecStart=/usr/bin/gpioset --mode=time -u ${{DELAY}} ${{GPIO_PATH}} ${{GPIO}}=1
/openbmc/u-boot/cmd/
H A Dbootmenu.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2011-2013 Pali Rohár <pali.rohar@gmail.com>
34 int delay; /* delay for autoboot */ member
61 int reverse = (entry->menu->active == entry->num); in bootmenu_print_entry()
64 * Move cursor to line where the entry will be drown (entry->num) in bootmenu_print_entry()
67 printf(ANSI_CURSOR_POSITION, entry->num + 4, 1); in bootmenu_print_entry()
74 puts(entry->title); in bootmenu_print_entry()
85 if (menu->delay > 0) { in bootmenu_autoboot_loop()
86 printf(ANSI_CURSOR_POSITION, menu->count + 5, 1); in bootmenu_autoboot_loop()
87 printf(" Hit any key to stop autoboot: %2d ", menu->delay); in bootmenu_autoboot_loop()
[all …]
/openbmc/linux/drivers/media/test-drivers/vidtv/
H A Dvidtv_tuner.h1 /* SPDX-License-Identifier: GPL-2.0 */
20 * struct vidtv_tuner_config - Configuration used to init the tuner.
22 * @mock_power_up_delay_msec: Simulate a power-up delay.
23 * @mock_tune_delay_msec: Simulate a tune delay.
24 * @vidtv_valid_dvb_t_freqs: The valid DVB-T frequencies to simulate.
25 * @vidtv_valid_dvb_c_freqs: The valid DVB-C frequencies to simulate.
26 * @vidtv_valid_dvb_s_freqs: The valid DVB-S frequencies to simulate.
30 * The configuration used to init the tuner module, usually filled
/openbmc/u-boot/doc/
H A DREADME.bitbangMII1 This patch rewrites the miiphybb ( Bit-banged MII bus driver ) in order to
4 buses are implemented via bit-banging mode.
9 CONFIG_BITBANGMII - Enable the miiphybb driver
10 CONFIG_BITBANGMII_MULTI - Enable the multi bus support
15 MII_INIT - Generic code to enable the MII bus (optional)
16 MDIO_DECLARE - Declaration needed to access to the MDIO pin (optional)
17 MDIO_ACTIVE - Activate the MDIO pin as out pin
18 MDIO_TRISTATE - Activate the MDIO pin as input/tristate pin
19 MDIO_READ - Read the MDIO pin
20 MDIO(v) - Write v on the MDIO pin
[all …]
/openbmc/linux/drivers/media/i2c/
H A Dbt819.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * bt819 - BT819A VideoStream Decoder (Rockwell Part)
12 * - moved over to linux>=2.4.x i2c protocol (9/9/2002)
21 #include <linux/delay.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-ctrls.h>
29 MODULE_DESCRIPTION("Brooktree-819 video decoder driver");
35 MODULE_PARM_DESC(debug, "Debug level (0-1)");
38 /* ----------------------------------------------------------------------- */
57 return &container_of(ctrl->handler, struct bt819, hdl)->sd; in to_sd()
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/openbmc/linux/drivers/clk/actions/
H A Dowl-pll.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 // Author: David Liu <liuwei@actions-semi.com>
14 #include "owl-common.h"
32 u8 delay; member
51 .delay = _delay, \
63 .hw.init = CLK_HW_INIT(_name, \
78 .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
93 .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
99 #define mul_mask(m) ((1 << ((m)->width)) - 1)
/openbmc/linux/arch/arm/lib/
H A Ddelay.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Delay loops based on the OpenRISC implementation.
11 #include <linux/delay.h>
12 #include <linux/init.h>
18 * Default to the loop-based delay implementation.
21 .delay = __loop_delay,
33 return -ENXIO; in read_current_timer()
35 *timer_val = delay_timer->read_current_timer(); in read_current_timer()
49 while ((get_cycles() - start) < cycles) in __timer_delay()
70 clocks_calc_mult_shift(&new_mult, &new_shift, timer->freq, in register_current_timer_delay()
[all …]
/openbmc/linux/drivers/mmc/host/
H A Dsdhci-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 #include "sdhci-pltfm.h"
19 /* HRS - Host Register Set (specific to Cadence) */
39 /* SRS - Slot Register Set (SDHCI-compatible) */
57 * The tuned val register is 6 bit-wide, but not the whole of the range is
58 * available. The range 0-42 seems to be available (then 43 wraps around to 0)
85 int (*init)(struct platform_device *pdev); member
90 { "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
91 { "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
92 { "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
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