| /openbmc/linux/Documentation/devicetree/bindings/arm/mediatek/ |
| H A D | mediatek,infracfg.yaml | 4 $id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
13 The Mediatek infracfg controller provides various clocks and reset outputs
23 - mediatek,mt2701-infracfg
24 - mediatek,mt2712-infracfg
25 - mediatek,mt6765-infracfg
26 - mediatek,mt6795-infracfg
28 - mediatek,mt6797-infracfg
29 - mediatek,mt7622-infracfg
30 - mediatek,mt7629-infracfg
31 - mediatek,mt7981-infracfg
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| H A D | mediatek,mt8192-sys-clock.yaml | 21 - mediatek,mt8192-infracfg
50 infracfg: syscon@10001000 {
51 compatible = "mediatek,mt8192-infracfg", "syscon";
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| /openbmc/linux/drivers/soc/mediatek/ |
| H A D | mtk-infracfg.c | 10 #include <linux/soc/mediatek/infracfg.h>
18 * @infracfg: The infracfg regmap
28 int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_set_bus_protection() argument
35 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, in mtk_infracfg_set_bus_protection()
38 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_SET, mask); in mtk_infracfg_set_bus_protection()
40 ret = regmap_read_poll_timeout(infracfg, INFRA_TOPAXI_PROTECTSTA1, in mtk_infracfg_set_bus_protection()
49 * @infracfg: The infracfg regmap
59 int mtk_infracfg_clear_bus_protection(struct regmap *infracfg, u32 mask, in mtk_infracfg_clear_bus_protection() argument
66 regmap_update_bits(infracfg, INFRA_TOPAXI_PROTECTEN, mask, 0); in mtk_infracfg_clear_bus_protection()
68 regmap_write(infracfg, INFRA_TOPAXI_PROTECTEN_CLR, mask); in mtk_infracfg_clear_bus_protection()
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| H A D | Kconfig | 30 bool "MediaTek INFRACFG Support"
33 Say yes here to add support for the MediaTek INFRACFG controller. The
34 INFRACFG controller contains various infrastructure registers not
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| /openbmc/linux/arch/arm64/boot/dts/mediatek/ |
| H A D | mt8365.dtsi | 284 infracfg: syscon@10001000 { label
285 compatible = "mediatek,mt8365-infracfg", "syscon";
329 clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
330 <&infracfg CLK_IFR_PMIC_AP>,
331 <&infracfg CLK_IFR_PWRAP_SYS>,
332 <&infracfg CLK_IFR_PWRAP_TMR>;
361 infracfg_nao: infracfg@1020e000 {
362 compatible = "mediatek,mt8365-infracfg", "syscon";
370 clocks = <&infracfg CLK_IFR_TRNG>;
389 clocks = <&infracfg CLK_IFR_AP_DMA>;
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| H A D | mt7986a.dtsi | 143 infracfg: infracfg@10001000 { label
144 compatible = "mediatek,mt7986-infracfg", "syscon";
203 <&infracfg CLK_INFRA_PWM_STA>,
204 <&infracfg CLK_INFRA_PWM1_CK>,
205 <&infracfg CLK_INFRA_PWM2_CK>;
228 clocks = <&infracfg CLK_INFRA_TRNG_CK>;
241 clocks = <&infracfg CLK_INFRA_EIP97_CK>;
252 clocks = <&infracfg CLK_INFRA_UART0_SEL>,
253 <&infracfg CLK_INFRA_UART0_CK>;
256 <&infracfg CLK_INFRA_UART0_SEL>;
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| H A D | mt8183.dtsi | 742 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
750 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
758 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
766 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
774 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
782 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
790 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
798 clocks = <&infracfg CLK_INFRA_DEBUGSYS>;
809 infracfg: syscon@10001000 { label
810 compatible = "mediatek,mt8183-infracfg", "syscon";
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| H A D | mt8167.dtsi | 26 infracfg: infracfg@10001000 { label
27 compatible = "mediatek,mt8167-infracfg", "syscon";
54 mediatek,infracfg = <&infracfg>;
80 mediatek,infracfg = <&infracfg>;
91 mediatek,infracfg = <&infracfg>;
99 mediatek,infracfg = <&infracfg>;
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| H A D | mt8192.dtsi | 449 infracfg: syscon@10001000 { label
450 compatible = "mediatek,mt8192-infracfg", "syscon";
502 <&infracfg CLK_INFRA_AUDIO_26M_B>,
503 <&infracfg CLK_INFRA_AUDIO>;
505 mediatek,infracfg = <&infracfg>;
511 clocks = <&infracfg CLK_INFRA_PMIC_CONN>;
513 mediatek,infracfg = <&infracfg>;
528 mediatek,infracfg = <&infracfg>;
569 mediatek,infracfg = <&infracfg>;
583 mediatek,infracfg = <&infracfg>;
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| H A D | mt7622.dtsi | 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
213 infracfg: infracfg@10000000 { label
214 compatible = "mediatek,mt7622-infracfg",
225 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
227 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
250 infracfg = <&infracfg>;
259 clocks = <&infracfg CLK_INFRA_IRRX_PD>,
302 clocks = <&infracfg CLK_INFRA_TRNG>;
621 clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
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| H A D | mt8173.dtsi | 159 clocks = <&infracfg CLK_INFRA_CA53SEL>,
174 clocks = <&infracfg CLK_INFRA_CA53SEL>,
189 clocks = <&infracfg CLK_INFRA_CA72SEL>,
204 clocks = <&infracfg CLK_INFRA_CA72SEL>,
355 infracfg: power-controller@10001000 { label
356 compatible = "mediatek,mt8173-infracfg", "syscon";
481 mediatek,infracfg = <&infracfg>;
515 mediatek,infracfg = <&infracfg>;
533 clocks = <&infracfg CLK_INFRA_CLK_13M>,
542 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>;
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| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | mt8192-afe-pcm.yaml | 30 mediatek,infracfg:
32 description: The phandle of the mediatek infracfg controller
63 - mediatek,infracfg
85 mediatek,infracfg = <&infracfg>;
91 <&infracfg CLK_INFRA_AUDIO>,
92 <&infracfg CLK_INFRA_AUDIO_26M_B>;
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| H A D | mt8186-afe-pcm.yaml | 32 mediatek,infracfg:
34 description: The phandle of the mediatek infracfg controller
102 - mediatek,infracfg
121 mediatek,infracfg = <&infracfg>;
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| H A D | mtk-btcvsd-snd.txt | 7 - mediatek,infracfg: the phandles of INFRASYS
22 mediatek,infracfg = <&infrasys>;
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| /openbmc/u-boot/drivers/power/domain/ |
| H A D | mtk-power-domain.c | 80 void __iomem *infracfg; member
167 static int mtk_infracfg_set_bus_protection(void __iomem *infracfg, in mtk_infracfg_set_bus_protection() argument
172 clrsetbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask, mask); in mtk_infracfg_set_bus_protection()
174 return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val, in mtk_infracfg_set_bus_protection()
178 static int mtk_infracfg_clear_bus_protection(void __iomem *infracfg, in mtk_infracfg_clear_bus_protection() argument
183 clrbits_le32(infracfg + INFRA_TOPAXI_PROT_EN, mask); in mtk_infracfg_clear_bus_protection()
185 return readl_poll_timeout(infracfg + INFRA_TOPAXI_PROT_STA1, val, in mtk_infracfg_clear_bus_protection()
249 ret = mtk_infracfg_clear_bus_protection(scpd->infracfg, in scpsys_power_on()
268 ret = mtk_infracfg_set_bus_protection(scpd->infracfg, in scpsys_power_off()
358 err = dev_read_phandle_with_args(dev, "infracfg", NULL, 0, 0, &args); in mtk_power_domain_probe()
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| /openbmc/linux/drivers/net/wireless/mediatek/mt76/mt7615/ |
| H A D | soc.c | 23 dev->infracfg = syscon_regmap_lookup_by_phandle(np, "mediatek,infracfg"); in mt7622_wmac_init()
24 if (IS_ERR(dev->infracfg)) { in mt7622_wmac_init()
25 dev_err(dev->mt76.dev, "Cannot find infracfg controller\n"); in mt7622_wmac_init()
26 return PTR_ERR(dev->infracfg); in mt7622_wmac_init()
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | mt7623.dtsi | 31 clocks = <&infracfg CLK_INFRA_CPUSEL>,
41 clocks = <&infracfg CLK_INFRA_CPUSEL>,
51 clocks = <&infracfg CLK_INFRA_CPUSEL>,
61 clocks = <&infracfg CLK_INFRA_CPUSEL>,
106 infracfg: syscon@10001000 { label
107 compatible = "mediatek,mt7623-infracfg", "syscon";
134 infracfg = <&infracfg>;
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| H A D | mt7629.dtsi | 67 infracfg: syscon@10000000 { label
68 compatible = "mediatek,mt7629-infracfg", "syscon";
99 infracfg = <&infracfg>;
270 mediatek,infracfg = <&infracfg>;
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | mediatek-pcie-gen3.yaml | 212 clocks = <&infracfg 44>,
213 <&infracfg 40>,
214 <&infracfg 43>,
215 <&infracfg 97>,
216 <&infracfg 99>,
217 <&infracfg 111>;
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| /openbmc/linux/Documentation/devicetree/bindings/power/ |
| H A D | mediatek,power-controller.yaml | 114 mediatek,infracfg:
116 description: phandle to the device containing the INFRACFG register range.
174 mediatek,infracfg = <&infracfg>;
208 mediatek,infracfg = <&infracfg>;
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| /openbmc/linux/Documentation/devicetree/bindings/iommu/ |
| H A D | mediatek,iommu.yaml | 109 mediatek,infracfg:
111 description: The phandle to the mediatek infracfg syscon
198 - mediatek,infracfg
224 clocks = <&infracfg CLK_INFRA_M4U>;
226 mediatek,infracfg = <&infracfg>;
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| /openbmc/linux/Documentation/devicetree/bindings/soc/mediatek/ |
| H A D | scpsys.txt | 32 - infracfg: must contain a phandle to the infracfg controller
65 infracfg = <&infracfg>;
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| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt8173-infracfg.c | 74 { .compatible = "mediatek,mt8173-infracfg" },
95 CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg",
145 .name = "clk-mt8173-infracfg",
153 MODULE_DESCRIPTION("MediaTek MT8173 infracfg clocks driver");
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| H A D | clk-mt7622-infracfg.c | 55 { .compatible = "mediatek,mt7622-infracfg" },
117 .name = "clk-mt7622-infracfg",
125 MODULE_DESCRIPTION("MediaTek MT7622 infracfg clocks driver");
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| /openbmc/linux/Documentation/devicetree/bindings/cpufreq/ |
| H A D | cpufreq-mediatek.txt | 70 clocks = <&infracfg CLK_INFRA_CPUSEL>,
192 clocks = <&infracfg CLK_INFRA_CA53SEL>,
204 clocks = <&infracfg CLK_INFRA_CA53SEL>,
216 clocks = <&infracfg CLK_INFRA_CA72SEL>,
228 clocks = <&infracfg CLK_INFRA_CA72SEL>,
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