1425da20aSKaiChieh ChuangMediatek ALSA BT SCO CVSD/MSBC Driver 2425da20aSKaiChieh Chuang 3425da20aSKaiChieh ChuangRequired properties: 4425da20aSKaiChieh Chuang- compatible = "mediatek,mtk-btcvsd-snd"; 5425da20aSKaiChieh Chuang- reg: register location and size of PKV and SRAM_BANK2 6425da20aSKaiChieh Chuang- interrupts: should contain BTSCO interrupt 7425da20aSKaiChieh Chuang- mediatek,infracfg: the phandles of INFRASYS 8425da20aSKaiChieh Chuang- mediatek,offset: Array contains of register offset and mask 9425da20aSKaiChieh Chuang infra_misc_offset, 10425da20aSKaiChieh Chuang infra_conn_bt_cvsd_mask, 11425da20aSKaiChieh Chuang cvsd_mcu_read_offset, 12425da20aSKaiChieh Chuang cvsd_mcu_write_offset, 13425da20aSKaiChieh Chuang cvsd_packet_indicator_offset 14425da20aSKaiChieh Chuang 15425da20aSKaiChieh ChuangExample: 16425da20aSKaiChieh Chuang 17425da20aSKaiChieh Chuang mtk-btcvsd-snd@18000000 { 18425da20aSKaiChieh Chuang compatible = "mediatek,mtk-btcvsd-snd"; 19425da20aSKaiChieh Chuang reg=<0 0x18000000 0 0x1000>, 20425da20aSKaiChieh Chuang <0 0x18080000 0 0x8000>; 21425da20aSKaiChieh Chuang interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>; 22425da20aSKaiChieh Chuang mediatek,infracfg = <&infrasys>; 23425da20aSKaiChieh Chuang mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>; 24425da20aSKaiChieh Chuang }; 25