1344afef6SJiaxin Yu# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2344afef6SJiaxin Yu%YAML 1.2 3344afef6SJiaxin Yu--- 4344afef6SJiaxin Yu$id: http://devicetree.org/schemas/sound/mt8186-afe-pcm.yaml# 5344afef6SJiaxin Yu$schema: http://devicetree.org/meta-schemas/core.yaml# 6344afef6SJiaxin Yu 7344afef6SJiaxin Yutitle: Mediatek AFE PCM controller for mt8186 8344afef6SJiaxin Yu 9344afef6SJiaxin Yumaintainers: 10344afef6SJiaxin Yu - Jiaxin Yu <jiaxin.yu@mediatek.com> 11344afef6SJiaxin Yu 12344afef6SJiaxin Yuproperties: 13344afef6SJiaxin Yu compatible: 14344afef6SJiaxin Yu const: mediatek,mt8186-sound 15344afef6SJiaxin Yu 16344afef6SJiaxin Yu reg: 17344afef6SJiaxin Yu maxItems: 1 18344afef6SJiaxin Yu 19344afef6SJiaxin Yu interrupts: 20344afef6SJiaxin Yu maxItems: 1 21344afef6SJiaxin Yu 22344afef6SJiaxin Yu resets: 23344afef6SJiaxin Yu maxItems: 1 24344afef6SJiaxin Yu 25344afef6SJiaxin Yu reset-names: 26344afef6SJiaxin Yu const: audiosys 27344afef6SJiaxin Yu 28344afef6SJiaxin Yu mediatek,apmixedsys: 29*d9e909e2SRob Herring $ref: /schemas/types.yaml#/definitions/phandle 30344afef6SJiaxin Yu description: The phandle of the mediatek apmixedsys controller 31344afef6SJiaxin Yu 32344afef6SJiaxin Yu mediatek,infracfg: 33*d9e909e2SRob Herring $ref: /schemas/types.yaml#/definitions/phandle 34344afef6SJiaxin Yu description: The phandle of the mediatek infracfg controller 35344afef6SJiaxin Yu 36344afef6SJiaxin Yu mediatek,topckgen: 37*d9e909e2SRob Herring $ref: /schemas/types.yaml#/definitions/phandle 38344afef6SJiaxin Yu description: The phandle of the mediatek topckgen controller 39344afef6SJiaxin Yu 40344afef6SJiaxin Yu clocks: 41344afef6SJiaxin Yu items: 42344afef6SJiaxin Yu - description: audio infra sys clock 43344afef6SJiaxin Yu - description: audio infra 26M clock 44344afef6SJiaxin Yu - description: audio top mux 45344afef6SJiaxin Yu - description: audio intbus mux 46344afef6SJiaxin Yu - description: mainpll 136.5M clock 47344afef6SJiaxin Yu - description: faud1 mux 48344afef6SJiaxin Yu - description: apll1 clock 49344afef6SJiaxin Yu - description: faud2 mux 50344afef6SJiaxin Yu - description: apll2 clock 51344afef6SJiaxin Yu - description: audio engen1 mux 52344afef6SJiaxin Yu - description: apll1_d8 22.5792M clock 53344afef6SJiaxin Yu - description: audio engen2 mux 54344afef6SJiaxin Yu - description: apll2_d8 24.576M clock 55344afef6SJiaxin Yu - description: i2s0 mclk mux 56344afef6SJiaxin Yu - description: i2s1 mclk mux 57344afef6SJiaxin Yu - description: i2s2 mclk mux 58344afef6SJiaxin Yu - description: i2s4 mclk mux 59344afef6SJiaxin Yu - description: tdm mclk mux 60344afef6SJiaxin Yu - description: i2s0_mck divider 61344afef6SJiaxin Yu - description: i2s1_mck divider 62344afef6SJiaxin Yu - description: i2s2_mck divider 63344afef6SJiaxin Yu - description: i2s4_mck divider 64344afef6SJiaxin Yu - description: tdm_mck divider 65344afef6SJiaxin Yu - description: audio hires mux 66344afef6SJiaxin Yu - description: 26M clock 67344afef6SJiaxin Yu 68344afef6SJiaxin Yu clock-names: 69344afef6SJiaxin Yu items: 70344afef6SJiaxin Yu - const: aud_infra_clk 71344afef6SJiaxin Yu - const: mtkaif_26m_clk 72344afef6SJiaxin Yu - const: top_mux_audio 73344afef6SJiaxin Yu - const: top_mux_audio_int 74344afef6SJiaxin Yu - const: top_mainpll_d2_d4 75344afef6SJiaxin Yu - const: top_mux_aud_1 76344afef6SJiaxin Yu - const: top_apll1_ck 77344afef6SJiaxin Yu - const: top_mux_aud_2 78344afef6SJiaxin Yu - const: top_apll2_ck 79344afef6SJiaxin Yu - const: top_mux_aud_eng1 80344afef6SJiaxin Yu - const: top_apll1_d8 81344afef6SJiaxin Yu - const: top_mux_aud_eng2 82344afef6SJiaxin Yu - const: top_apll2_d8 83344afef6SJiaxin Yu - const: top_i2s0_m_sel 84344afef6SJiaxin Yu - const: top_i2s1_m_sel 85344afef6SJiaxin Yu - const: top_i2s2_m_sel 86344afef6SJiaxin Yu - const: top_i2s4_m_sel 87344afef6SJiaxin Yu - const: top_tdm_m_sel 88344afef6SJiaxin Yu - const: top_apll12_div0 89344afef6SJiaxin Yu - const: top_apll12_div1 90344afef6SJiaxin Yu - const: top_apll12_div2 91344afef6SJiaxin Yu - const: top_apll12_div4 92344afef6SJiaxin Yu - const: top_apll12_div_tdm 93344afef6SJiaxin Yu - const: top_mux_audio_h 94344afef6SJiaxin Yu - const: top_clk26m_clk 95344afef6SJiaxin Yu 96344afef6SJiaxin Yurequired: 97344afef6SJiaxin Yu - compatible 98344afef6SJiaxin Yu - interrupts 99344afef6SJiaxin Yu - resets 100344afef6SJiaxin Yu - reset-names 101344afef6SJiaxin Yu - mediatek,apmixedsys 102344afef6SJiaxin Yu - mediatek,infracfg 103344afef6SJiaxin Yu - mediatek,topckgen 104344afef6SJiaxin Yu - clocks 105344afef6SJiaxin Yu - clock-names 106344afef6SJiaxin Yu 107344afef6SJiaxin YuadditionalProperties: false 108344afef6SJiaxin Yu 109344afef6SJiaxin Yuexamples: 110344afef6SJiaxin Yu - | 111344afef6SJiaxin Yu #include <dt-bindings/interrupt-controller/arm-gic.h> 112344afef6SJiaxin Yu #include <dt-bindings/interrupt-controller/irq.h> 113344afef6SJiaxin Yu 114344afef6SJiaxin Yu afe: mt8186-afe-pcm@11210000 { 115344afef6SJiaxin Yu compatible = "mediatek,mt8186-sound"; 116344afef6SJiaxin Yu reg = <0x11210000 0x2000>; 117344afef6SJiaxin Yu interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 118344afef6SJiaxin Yu resets = <&watchdog 17>; //MT8186_TOPRGU_AUDIO_SW_RST 119344afef6SJiaxin Yu reset-names = "audiosys"; 120344afef6SJiaxin Yu mediatek,apmixedsys = <&apmixedsys>; 121344afef6SJiaxin Yu mediatek,infracfg = <&infracfg>; 122344afef6SJiaxin Yu mediatek,topckgen = <&topckgen>; 123344afef6SJiaxin Yu clocks = <&infracfg_ao 44>, //CLK_INFRA_AO_AUDIO 124344afef6SJiaxin Yu <&infracfg_ao 54>, //CLK_INFRA_AO_AUDIO_26M_BCLK 125344afef6SJiaxin Yu <&topckgen 15>, //CLK_TOP_AUDIO 126344afef6SJiaxin Yu <&topckgen 16>, //CLK_TOP_AUD_INTBUS 127344afef6SJiaxin Yu <&topckgen 70>, //CLK_TOP_MAINPLL_D2_D4 128344afef6SJiaxin Yu <&topckgen 17>, //CLK_TOP_AUD_1 129344afef6SJiaxin Yu <&apmixedsys 12>, //CLK_APMIXED_APLL1 130344afef6SJiaxin Yu <&topckgen 18>, //CLK_TOP_AUD_2 131344afef6SJiaxin Yu <&apmixedsys 13>, //CLK_APMIXED_APLL2 132344afef6SJiaxin Yu <&topckgen 19>, //CLK_TOP_AUD_ENGEN1 133344afef6SJiaxin Yu <&topckgen 101>, //CLK_TOP_APLL1_D8 134344afef6SJiaxin Yu <&topckgen 20>, //CLK_TOP_AUD_ENGEN2 135344afef6SJiaxin Yu <&topckgen 104>, //CLK_TOP_APLL2_D8 136344afef6SJiaxin Yu <&topckgen 63>, //CLK_TOP_APLL_I2S0_MCK_SEL 137344afef6SJiaxin Yu <&topckgen 64>, //CLK_TOP_APLL_I2S1_MCK_SEL 138344afef6SJiaxin Yu <&topckgen 65>, //CLK_TOP_APLL_I2S2_MCK_SEL 139344afef6SJiaxin Yu <&topckgen 66>, //CLK_TOP_APLL_I2S4_MCK_SEL 140344afef6SJiaxin Yu <&topckgen 67>, //CLK_TOP_APLL_TDMOUT_MCK_SEL 141344afef6SJiaxin Yu <&topckgen 131>, //CLK_TOP_APLL12_CK_DIV0 142344afef6SJiaxin Yu <&topckgen 132>, //CLK_TOP_APLL12_CK_DIV1 143344afef6SJiaxin Yu <&topckgen 133>, //CLK_TOP_APLL12_CK_DIV2 144344afef6SJiaxin Yu <&topckgen 134>, //CLK_TOP_APLL12_CK_DIV4 145344afef6SJiaxin Yu <&topckgen 135>, //CLK_TOP_APLL12_CK_DIV_TDMOUT_M 146344afef6SJiaxin Yu <&topckgen 44>, //CLK_TOP_AUDIO_H 147344afef6SJiaxin Yu <&clk26m>; 148344afef6SJiaxin Yu clock-names = "aud_infra_clk", 149344afef6SJiaxin Yu "mtkaif_26m_clk", 150344afef6SJiaxin Yu "top_mux_audio", 151344afef6SJiaxin Yu "top_mux_audio_int", 152344afef6SJiaxin Yu "top_mainpll_d2_d4", 153344afef6SJiaxin Yu "top_mux_aud_1", 154344afef6SJiaxin Yu "top_apll1_ck", 155344afef6SJiaxin Yu "top_mux_aud_2", 156344afef6SJiaxin Yu "top_apll2_ck", 157344afef6SJiaxin Yu "top_mux_aud_eng1", 158344afef6SJiaxin Yu "top_apll1_d8", 159344afef6SJiaxin Yu "top_mux_aud_eng2", 160344afef6SJiaxin Yu "top_apll2_d8", 161344afef6SJiaxin Yu "top_i2s0_m_sel", 162344afef6SJiaxin Yu "top_i2s1_m_sel", 163344afef6SJiaxin Yu "top_i2s2_m_sel", 164344afef6SJiaxin Yu "top_i2s4_m_sel", 165344afef6SJiaxin Yu "top_tdm_m_sel", 166344afef6SJiaxin Yu "top_apll12_div0", 167344afef6SJiaxin Yu "top_apll12_div1", 168344afef6SJiaxin Yu "top_apll12_div2", 169344afef6SJiaxin Yu "top_apll12_div4", 170344afef6SJiaxin Yu "top_apll12_div_tdm", 171344afef6SJiaxin Yu "top_mux_audio_h", 172344afef6SJiaxin Yu "top_clk26m_clk"; 173344afef6SJiaxin Yu }; 174344afef6SJiaxin Yu 175344afef6SJiaxin Yu... 176