/openbmc/linux/arch/arm64/boot/dts/freescale/ |
H A D | imx8qxp.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 4 * Copyright 2017-2020 NXP 8 #include <dt-bindings/clock/imx8-clock.h> 9 #include <dt-bindings/clock/imx8-lpcg.h> 10 #include <dt-bindings/firmware/imx/rsrc.h> 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/input.h> 13 #include <dt-bindings/interrupt-controller/arm-gic.h> 14 #include <dt-bindings/pinctrl/pads-imx8qxp.h> 15 #include <dt-bindings/thermal/thermal.h> [all …]
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H A D | imx8dxl.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 6 #include <dt-bindings/clock/imx8-clock.h> 7 #include <dt-bindings/firmware/imx/rsrc.h> 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/interrupt-controller/arm-gic.h> 10 #include <dt-bindings/input/input.h> 11 #include <dt-bindings/pinctrl/pads-imx8dxl.h> 12 #include <dt-bindings/thermal/thermal.h> 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; [all …]
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H A D | imx8qm.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/pinctrl/pads-imx8qm.h> 12 #include <dt-bindings/thermal/thermal.h> 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; [all …]
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H A D | imx8-ss-audio.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright 2018-2019 NXP 7 #include <dt-bindings/clock/imx8-lpcg.h> 8 #include <dt-bindings/firmware/imx/rsrc.h> 11 compatible = "simple-bus"; 12 #address-cells = <1>; 13 #size-cells = <1>; 16 audio_ipg_clk: clock-audio-ipg { 17 compatible = "fixed-clock"; 18 #clock-cells = <0>; [all …]
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H A D | imx8mm-venice-gw71xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/leds/common.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h> 16 led-controller { 17 compatible = "gpio-leds"; 18 pinctrl-names = "default"; 19 pinctrl-0 = <&pinctrl_gpio_leds>; 21 led-0 { 25 default-state = "on"; [all …]
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H A D | imx8mp-venice-gw71xx.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/leds/common.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h> 11 led-controller { 12 compatible = "gpio-leds"; 13 pinctrl-names = "default"; 14 pinctrl-0 = <&pinctrl_gpio_leds>; 16 led-0 { 20 default-state = "on"; [all …]
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H A D | imx8mm-venice-gw7905.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/leds/common.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h> 11 led-controller { 12 compatible = "gpio-leds"; 13 pinctrl-names = "default"; 14 pinctrl-0 = <&pinctrl_gpio_leds>; 16 led-0 { 20 default-state = "on"; [all …]
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H A D | imx8mp-venice-gw7905.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 #include <dt-bindings/gpio/gpio.h> 7 #include <dt-bindings/leds/common.h> 8 #include <dt-bindings/phy/phy-imx8-pcie.h> 11 led-controller { 12 compatible = "gpio-leds"; 13 pinctrl-names = "default"; 14 pinctrl-0 = <&pinctrl_gpio_leds>; 16 led-0 { 20 default-state = "on"; [all …]
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H A D | imx8mp-dhcom-pdk2.dts | 1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT) 6 * DHCM-iMX8ML8-C160-R409-F1638-SPI16-GE-CAN2-SD-RTC-WBTA-ADC-T-RGB-CSI2-HS-I-01D2 7 * DHCOM PCB number: 660-100 or newer 8 * PDK2 PCB number: 516-400 or newer 11 /dts-v1/; 13 #include <dt-bindings/leds/common.h> 14 #include <dt-bindings/phy/phy-imx8-pcie.h> 15 #include "imx8mp-dhcom-som.dtsi" 19 compatible = "dh,imx8mp-dhcom-pdk2", "dh,imx8mp-dhcom-som", 23 stdout-path = &uart1; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | imx8qxp-lpcg.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock 10 - Aisheng Dong <aisheng.dong@nxp.com> 13 The Low-Power Clock Gate (LPCG) modules contain a local programming 14 model to control the clock gates for the peripherals. An LPCG module 17 This level of clock gating is provided after the clocks are generated 18 by the SCU resources and clock controls. Thus even if the clock is [all …]
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H A D | fsl,imx8-acm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/clock/fsl,imx8-acm.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX8 Audio Clock Mux 10 - Shengjiu Wang <shengjiu.wang@nxp.com> 13 NXP i.MX8 Audio Clock Mux is dedicated clock muxing IP 14 used to control Audio related clock on the SoC. 19 - fsl,imx8dxl-acm 20 - fsl,imx8qm-acm [all …]
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | fsl,imx8-pcie-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/phy/fsl,imx8-pcie-phy.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Richard Zhu <hongxing.zhu@nxp.com> 13 "#phy-cells": 18 - fsl,imx8mm-pcie-phy 19 - fsl,imx8mp-pcie-phy 27 clock-names: 29 - const: ref [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | fsl-imx8dx.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ 6 #include <dt-bindings/interrupt-controller/arm-gic.h> 7 #include "fsl-imx8-ca35.dtsi" 8 #include <dt-bindings/soc/imx_rsrc.h> 9 #include <dt-bindings/soc/imx8_pd.h> 10 #include <dt-bindings/clock/imx8qxp-clock.h> 11 #include <dt-bindings/input/input.h> 12 #include <dt-bindings/pinctrl/pads-imx8qxp.h> 13 #include <dt-bindings/gpio/gpio.h> 18 interrupt-parent = <&gic>; [all …]
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/openbmc/linux/drivers/phy/freescale/ |
H A D | phy-fsl-imx8m-pcie.c | 1 // SPDX-License-Identifier: GPL-2.0+ 12 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h> 20 #include <dt-bindings/phy/phy-imx8-pcie.h> 79 pad_mode = imx8_phy->refclk_pad_mode; in imx8_pcie_phy_power_on() 80 switch (imx8_phy->drvdata->variant) { in imx8_pcie_phy_power_on() 82 reset_control_assert(imx8_phy->reset); in imx8_pcie_phy_power_on() 84 /* Tune PHY de-emphasis setting to pass PCIe compliance. */ in imx8_pcie_phy_power_on() 85 if (imx8_phy->tx_deemph_gen1) in imx8_pcie_phy_power_on() 86 writel(imx8_phy->tx_deemph_gen1, in imx8_pcie_phy_power_on() 87 imx8_phy->base + PCIE_PHY_TRSV_REG5); in imx8_pcie_phy_power_on() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/usb/ |
H A D | fsl,imx8qm-cdns3.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/usb/fsl,imx8qm-cdns3.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Frank Li <Frank.Li@nxp.com> 15 const: fsl,imx8qm-usb3 19 - description: Register set for iMX USB3 Platform Control 21 "#address-cells": 24 "#size-cells": 31 - description: Standby clock. Used during ultra low power states. [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | fsl,imx8qxp-pixel-combiner.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-combiner.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Liu Ying <victor.liu@nxp.com> 23 - fsl,imx8qm-pixel-combiner 24 - fsl,imx8qxp-pixel-combiner 26 "#address-cells": 29 "#size-cells": 38 clock-names: [all …]
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/openbmc/linux/Documentation/devicetree/bindings/media/ |
H A D | nxp,imx8-isi.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 16 number and nature is SoC-dependent. They cover both capture interfaces (MIPI 17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support. 22 - fsl,imx8mn-isi 23 - fsl,imx8mp-isi 24 - fsl,imx93-isi [all …]
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/openbmc/u-boot/board/freescale/imx8qxp_mek/ |
H A D | imx8qxp_mek.c | 1 // SPDX-License-Identifier: GPL-2.0+ 13 #include <asm/arch/clock.h> 15 #include <asm/arch/imx8-pins.h> 44 /* Set UART0 clock root to 80 MHz */ in board_early_init_f() 48 ret = sc_pm_set_resource_power_mode(-1, SC_R_UART_0, SC_PM_PW_MODE_ON); in board_early_init_f() 52 ret = sc_pm_set_clock_rate(-1, SC_R_UART_0, 2, &rate); in board_early_init_f() 56 /* Enable UART0 clock root */ in board_early_init_f() 57 ret = sc_pm_clock_enable(-1, SC_R_UART_0, 2, true, false); in board_early_init_f() 100 if (phydev->drv->config) in board_phy_config() 101 phydev->drv->config(phydev); in board_phy_config() [all …]
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/openbmc/linux/drivers/clk/imx/ |
H A D | clk-imx8qxp-lpcg.c | 1 // SPDX-License-Identifier: GPL-2.0+ 7 #include <linux/clk-provider.h> 16 #include "clk-scu.h" 17 #include "clk-imx8qxp-lpcg.h" 19 #include <dt-bindings/clock/imx8-clock.h> 22 * struct imx8qxp_lpcg_data - Description of one LPCG clock 23 * @id: clock ID 24 * @name: clock name 25 * @parent: parent clock name 26 * @flags: common clock flags [all …]
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H A D | clk-imx8-acm.c | 1 // SPDX-License-Identifier: GPL-2.0+ 6 #include <dt-bindings/clock/imx8-clock.h> 7 #include <linux/clk-provider.h> 22 * struct clk_imx_acm_pm_domains - structure for multi power domain 34 * struct clk_imx8_acm_sel - for clock mux 35 * @name: clock name 36 * @clkid: clock id 37 * @parents: clock parents 38 * @num_parents: clock parents number 54 * struct imx8_acm_soc_data - soc specific data [all …]
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/openbmc/linux/Documentation/devicetree/bindings/mfd/ |
H A D | fsl,imx8qxp-csr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/mfd/fsl,imx8qxp-csr.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Liu Ying <victor.liu@nxp.com> 17 use-case is for some other nodes to acquire a reference to the syscon node 18 by phandle, and the other typical use-case is that the operating system 23 pattern: "^syscon@[0-9a-f]+$" 27 - enum: 28 - fsl,imx8qxp-mipi-lvds-csr [all …]
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/openbmc/linux/Documentation/devicetree/bindings/dsp/ |
H A D | fsl,dsp.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Daniel Baluta <daniel.baluta@nxp.com> 11 - Shengjiu Wang <shengjiu.wang@nxp.com> 15 advanced pre- and post- audio processing. 20 - fsl,imx8qxp-dsp 21 - fsl,imx8qm-dsp 22 - fsl,imx8mp-dsp 23 - fsl,imx8ulp-dsp [all …]
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/openbmc/linux/drivers/net/ethernet/stmicro/stmmac/ |
H A D | dwmac-imx.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * dwmac-imx.c - DWMAC Specific Glue layer for NXP imx8 70 struct imx_priv_data *dwmac = plat_dat->bsp_priv; in imx8mp_set_intf_mode() 73 switch (plat_dat->mac_interface) { in imx8mp_set_intf_mode() 79 val |= (dwmac->rmii_refclk_ext ? 0 : GPR_ENET_QOS_CLK_TX_CLK_SEL); in imx8mp_set_intf_mode() 90 plat_dat->mac_interface); in imx8mp_set_intf_mode() 91 return -EINVAL; in imx8mp_set_intf_mode() 95 return regmap_update_bits(dwmac->intf_regmap, dwmac->intf_reg_off, in imx8mp_set_intf_mode() 110 struct imx_priv_data *dwmac = plat_dat->bsp_priv; in imx93_set_intf_mode() 113 switch (plat_dat->mac_interface) { in imx93_set_intf_mode() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/bus/ |
H A D | fsl,imx8qxp-pixel-link-msi-bus.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/bus/fsl,imx8qxp-pixel-link-msi-bus.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Liu Ying <victor.liu@nxp.com> 16 clock and reset through the i.MX8 Distributed Slave System Controller (DSC). 18 i.MX8qxp pixel link MSI bus is a simple memory-mapped bus. Two input clocks, 19 that is, MSI clock and AHB clock, need to be enabled so that peripherals 35 - $ref: simple-pm-bus.yaml# 37 # We need a select here so we don't match all nodes with 'simple-pm-bus'. [all …]
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/openbmc/linux/Documentation/devicetree/bindings/firmware/ |
H A D | fsl,scu.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Dong Aisheng <aisheng.dong@nxp.com> 13 The System Controller Firmware (SCFW) is a low-level system function 14 which runs on a dedicated Cortex-M core to provide power, clock, and 17 The AP communicates with the SC using a multi-ported MU module found 26 const: fsl,imx-scu 28 clock-controller: 30 Clock controller node that provides the clocks controlled by the SCU [all …]
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