1dff49d55SAnson Huang# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2dff49d55SAnson Huang%YAML 1.2 3dff49d55SAnson Huang--- 4dff49d55SAnson Huang$id: http://devicetree.org/schemas/clock/imx8qxp-lpcg.yaml# 5dff49d55SAnson Huang$schema: http://devicetree.org/meta-schemas/core.yaml# 6dff49d55SAnson Huang 7*84e85359SKrzysztof Kozlowskititle: NXP i.MX8QXP LPCG (Low-Power Clock Gating) Clock 8dff49d55SAnson Huang 9dff49d55SAnson Huangmaintainers: 10dff49d55SAnson Huang - Aisheng Dong <aisheng.dong@nxp.com> 11dff49d55SAnson Huang 12dff49d55SAnson Huangdescription: | 13dff49d55SAnson Huang The Low-Power Clock Gate (LPCG) modules contain a local programming 14dff49d55SAnson Huang model to control the clock gates for the peripherals. An LPCG module 15dff49d55SAnson Huang is used to locally gate the clocks for the associated peripheral. 16dff49d55SAnson Huang 17dff49d55SAnson Huang This level of clock gating is provided after the clocks are generated 18dff49d55SAnson Huang by the SCU resources and clock controls. Thus even if the clock is 19dff49d55SAnson Huang enabled by these control bits, it might still not be running based 20dff49d55SAnson Huang on the base resource. 21dff49d55SAnson Huang 22dff49d55SAnson Huang The clock consumer should specify the desired clock by having the clock 23dff49d55SAnson Huang ID in its "clocks" phandle cell. See the full list of clock IDs from: 24540742fbSDong Aisheng include/dt-bindings/clock/imx8-lpcg.h 25dff49d55SAnson Huang 26dff49d55SAnson Huangproperties: 27dff49d55SAnson Huang compatible: 28540742fbSDong Aisheng oneOf: 29540742fbSDong Aisheng - const: fsl,imx8qxp-lpcg 30540742fbSDong Aisheng - items: 31540742fbSDong Aisheng - enum: 32540742fbSDong Aisheng - fsl,imx8qm-lpcg 33540742fbSDong Aisheng - const: fsl,imx8qxp-lpcg 34540742fbSDong Aisheng - enum: 35dff49d55SAnson Huang - fsl,imx8qxp-lpcg-adma 36dff49d55SAnson Huang - fsl,imx8qxp-lpcg-conn 37dff49d55SAnson Huang - fsl,imx8qxp-lpcg-dc 38dff49d55SAnson Huang - fsl,imx8qxp-lpcg-dsp 39dff49d55SAnson Huang - fsl,imx8qxp-lpcg-gpu 40dff49d55SAnson Huang - fsl,imx8qxp-lpcg-hsio 41dff49d55SAnson Huang - fsl,imx8qxp-lpcg-img 42dff49d55SAnson Huang - fsl,imx8qxp-lpcg-lsio 43dff49d55SAnson Huang - fsl,imx8qxp-lpcg-vpu 44540742fbSDong Aisheng deprecated: true 45dff49d55SAnson Huang reg: 46dff49d55SAnson Huang maxItems: 1 47dff49d55SAnson Huang 48dff49d55SAnson Huang '#clock-cells': 49dff49d55SAnson Huang const: 1 50dff49d55SAnson Huang 51540742fbSDong Aisheng clocks: 52540742fbSDong Aisheng description: | 53540742fbSDong Aisheng Input parent clocks phandle array for each clock 54540742fbSDong Aisheng minItems: 1 55540742fbSDong Aisheng maxItems: 8 56540742fbSDong Aisheng 57540742fbSDong Aisheng clock-indices: 58540742fbSDong Aisheng description: | 59540742fbSDong Aisheng An integer array indicating the bit offset for each clock. 60540742fbSDong Aisheng Refer to <include/dt-bindings/clock/imx8-lpcg.h> for the 61540742fbSDong Aisheng supported LPCG clock indices. 62540742fbSDong Aisheng minItems: 1 63540742fbSDong Aisheng maxItems: 8 64540742fbSDong Aisheng 65540742fbSDong Aisheng clock-output-names: 66540742fbSDong Aisheng description: | 67540742fbSDong Aisheng Shall be the corresponding names of the outputs. 68540742fbSDong Aisheng NOTE this property must be specified in the same order 69540742fbSDong Aisheng as the clock-indices property. 70540742fbSDong Aisheng minItems: 1 71540742fbSDong Aisheng maxItems: 8 72540742fbSDong Aisheng 73540742fbSDong Aisheng power-domains: 74540742fbSDong Aisheng maxItems: 1 75540742fbSDong Aisheng 76dff49d55SAnson Huangrequired: 77dff49d55SAnson Huang - compatible 78dff49d55SAnson Huang - reg 79dff49d55SAnson Huang - '#clock-cells' 80dff49d55SAnson Huang 81dff49d55SAnson HuangadditionalProperties: false 82dff49d55SAnson Huang 83dff49d55SAnson Huangexamples: 84dff49d55SAnson Huang - | 85540742fbSDong Aisheng #include <dt-bindings/clock/imx8-lpcg.h> 86dff49d55SAnson Huang #include <dt-bindings/firmware/imx/rsrc.h> 87dff49d55SAnson Huang #include <dt-bindings/interrupt-controller/arm-gic.h> 88dff49d55SAnson Huang 89540742fbSDong Aisheng sdhc0_lpcg: clock-controller@5b200000 { 90540742fbSDong Aisheng compatible = "fsl,imx8qxp-lpcg"; 91540742fbSDong Aisheng reg = <0x5b200000 0x10000>; 92dff49d55SAnson Huang #clock-cells = <1>; 93540742fbSDong Aisheng clocks = <&sdhc0_clk IMX_SC_PM_CLK_PER>, 94540742fbSDong Aisheng <&conn_ipg_clk>, 95540742fbSDong Aisheng <&conn_axi_clk>; 96540742fbSDong Aisheng clock-indices = <IMX_LPCG_CLK_0>, 97540742fbSDong Aisheng <IMX_LPCG_CLK_4>, 98540742fbSDong Aisheng <IMX_LPCG_CLK_5>; 99540742fbSDong Aisheng clock-output-names = "sdhc0_lpcg_per_clk", 100540742fbSDong Aisheng "sdhc0_lpcg_ipg_clk", 101540742fbSDong Aisheng "sdhc0_lpcg_ahb_clk"; 102540742fbSDong Aisheng power-domains = <&pd IMX_SC_R_SDHC_0>; 103dff49d55SAnson Huang }; 104