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/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dfsl_ifc_nand.c1 // SPDX-License-Identifier: GPL-2.0+
2 /* Integrated Flash Controller NAND Machine Driver
11 #include <nand.h>
42 /* overview of the fsl ifc controller */
49 void __iomem *addr; /* Address of assigned IFC buffer */
56 unsigned int eccread; /* Non zero for a full-page ECC read */
61 /* 512-byte page with 4-bit ECC, 8-bit */
68 /* 512-byte page with 4-bit ECC, 16-bit */
75 /* 2048-byte page size with 4-bit ECC */
87 /* 4096-byte page size with 4-bit ECC */
[all …]
H A Dfsl_ifc_spl.c1 // SPDX-License-Identifier: GPL-2.0+
3 * NAND boot for Freescale Integrated Flash Controller, NAND FCM
38 int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf; in check_read_ecc()
58 ver = ifc_in32(&regs.gregs->ifc_rev); in runtime_regs_address()
69 struct fsl_ifc_runtime *ifc = runtime_regs_address(); in nand_wait() local
76 bufnum_end = bufnum + bufperpage - 1; in nand_wait()
79 status = ifc_in32(&ifc->ifc_nand.nand_evter_stat); in nand_wait()
89 eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]); in nand_wait()
96 ifc_out32(&ifc->ifc_nand.nand_evter_stat, status); in nand_wait()
110 struct fsl_ifc_runtime *ifc = NULL; in nand_spl_load_image() local
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Dfsl_ifc_nand.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale Integrated Flash Controller NAND driver
5 * Copyright 2011-2012 Freescale Semiconductor, Inc
25 for IFC NAND Machine */
40 /* overview of the fsl ifc controller */
45 void __iomem *addr; /* Address of assigned IFC buffer */
51 unsigned int eccread; /* Non zero for a full-page ECC read */
67 .offs = 2, /* 0 on 8-bit small page */
77 .offs = 2, /* 0 on 8-bit small page */
90 return -ERANGE; in fsl_ifc_ooblayout_ecc()
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/fsl/
H A Dfsl,ifc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/fsl/fsl,ifc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Li Yang <leoyang.li@nxp.com>
13 NXP's integrated flash controller (IFC) is an advanced version of the
15 interfaces with an extended feature set. The IFC provides access to multiple
16 external memory types, such as NAND flash (SLC and MLC), NOR flash, EPROM,
21 pattern: "^memory-controller@[0-9a-f]+$"
24 const: fsl,ifc
[all …]
/openbmc/linux/drivers/memory/
H A Dfsl_ifc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
29 * convert_ifc_address - convert the base address
39 * fsl_ifc_find - find IFC bank
42 * This function walks IFC banks comparing "Base address" field of the CSPR
51 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->gregs) in fsl_ifc_find()
52 return -ENODEV; in fsl_ifc_find()
54 for (i = 0; i < fsl_ifc_ctrl_dev->banks; i++) { in fsl_ifc_find()
55 u32 cspr = ifc_in32(&fsl_ifc_ctrl_dev->gregs->cspr_cs[i].cspr); in fsl_ifc_find()
62 return -ENOENT; in fsl_ifc_find()
68 struct fsl_ifc_global __iomem *ifc = ctrl->gregs; in fsl_ifc_ctrl_init() local
[all …]
/openbmc/u-boot/board/freescale/p1010rdb/
H A DREADME.P1010RDB-PB3 The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
4 P1010RDB-PB is a variation of previous P1010RDB-PA board.
6 The P1010 is a cost-effective, low-power, highly integrated host processor
13 The P1010RDB-PB board features are as following:
15 - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
16 - 32M bytes NOR flash single-chip memory
17 - 2G bytes NAND flash memory
18 - 16M bytes SPI memory
19 - 256K bit M24256 I2C EEPROM
20 - I2C Board EEPROM 128x8 bit memory
[all …]
H A Dspl.c1 // SPDX-License-Identifier: GPL-2.0+
11 #include <nand.h>
28 struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; in board_init_f() local
32 /* Clock configuration to access CPLD using IFC(GPCM) */ in board_init_f()
33 setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); in board_init_f()
36 setbits_be32(&gur->pmuxcr2, MPC85xx_PMUXCR2_GPIO01_DRVVBUS); in board_init_f()
40 plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; in board_init_f()
42 gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; in board_init_f()
45 gd->bus_clk / 16 / CONFIG_BAUDRATE); in board_init_f()
52 /* copy code to RAM and jump to it - this should not return */ in board_init_f()
[all …]
/openbmc/u-boot/board/freescale/ls2080ardb/
H A DREADME2 --------
3 The LS2080A Reference Design (RDB) is a high-performance computing,
7 The LS2081A Reference Design (RDB) is a high-performance computing,
12 --------------------------------------
13 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
17 -----------------------
18 - SERDES Connections, 16 lanes supporting:
19 - PCI Express - 3.0
20 - SATA 3.0
21 - XFI
[all …]
/openbmc/linux/include/linux/
H A Dfsl_ifc.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
20 * The actual number of banks implemented depends on the IFC version
21 * - IFC version 1.0 implements 4 banks.
22 * - IFC version 1.1 onward implements 8 banks.
35 * CSPR - Chip Select Property Register
55 /* NAND */
69 (__ilog2(n) - IFC_AMASK_SHIFT))
110 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
123 * Chip Select Option Register - NOR Flash Mode
150 * Chip Select Option Register - GPCM Mode
[all …]
/openbmc/u-boot/board/freescale/ls1043ardb/
H A DREADME2 --------
3 The LS1043A Reference Design Board (RDB) is a high-performance computing,
7 debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
15 -----------------------
16 - SERDES Connections, 4 lanes supporting:
17 - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
19 - QSGMII with x4 RJ45 connector
20 - XFI with x1 RJ45 connector
[all …]
/openbmc/u-boot/board/freescale/ls2080aqds/
H A DREADME2 --------
3 The LS2080A Development System (QDS) is a high-performance computing,
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS2080A,
15 -----------------------
16 - SERDES Connections, 16 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
19 - QSGMII
20 - SATA 3.0
[all …]
/openbmc/u-boot/board/freescale/ls1043aqds/
H A DREADME2 --------
3 The LS1043A Development System (QDS) is a high-performance computing,
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A
15 -----------------------
16 - SERDES Connections, 4 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
19 - QSGMII
20 - SATA 3.0
[all …]
/openbmc/u-boot/board/freescale/ls1046aqds/
H A DREADME2 --------
3 The LS1046A Development System (QDS) is a high-performance computing,
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
15 -----------------------
16 - SERDES Connections, 8 lanes supporting:
17 - PCI Express - 3.0
18 - SGMII, SGMII 2.5
19 - QSGMII
20 - SATA 3.0
[all …]
/openbmc/u-boot/include/
H A Dfsl_ifc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
36 * CSPR - Chip Select Property Register
56 /* NAND */
73 (LOG2(n) - IFC_AMASK_SHIFT))
114 #define CSOR_NAND_PB(n) ((LOG2(n) - 5) << CSOR_NAND_PB_SHIFT)
127 * Chip Select Option Register - NOR Flash Mode
154 * Chip Select Option Register - GPCM Mode
156 /* GPCM Mode - Normal */
158 /* GPCM Mode - GenericASIC */
[all …]
/openbmc/u-boot/board/freescale/ls1021aqds/
H A DREADME2 --------
6 ------------------
8 is built on Layerscape architecture, the industry's first software-aware,
9 core-agnostic networking architecture to offer unprecedented efficiency
12 A member of the value-performance tier, the QorIQ LS1021A processor provides
14 enterprise networking applications. Incorporating dual ARM Cortex-A7 cores
15 running up to 1.0 GHz, the LS1021A processor delivers pre-silicon CoreMark
17 security features and the broadest array of high-speed interconnects and
18 optimized peripheral features ever offered in a sub-3 W processor.
23 protection on both L1 and L2 caches. The LS1021A processor is pin- and
[all …]
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dc293pcie.dts35 /include/ "c293si-pre.dtsi"
45 ifc: ifc@fffe1e000 { label
73 &ifc {
75 #address-cells = <1>;
76 #size-cells = <1>;
77 compatible = "cfi-flash";
79 bank-width = <2>;
80 device-width = <1>;
107 /* 512KB for u-boot Bootloader Image and evn */
109 label = "NOR U-Boot Image";
[all …]
/openbmc/u-boot/board/freescale/t102xrdb/
H A DREADME2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
[all …]
/openbmc/u-boot/board/freescale/t104xrdb/
H A DREADME2 --------
9 personality of T1040 SoC without Integrated 8-port Gigabit(L2 Switch).
16 The board is re-designed T1040RDB board with following changes :
17 - Support of DDR4 memory and some enhancements
20 The board is re-designed T1040RDB board with following changes :
21 - Support of DDR4 memory
22 - Support for 0x86 serdes protocol which can support following interfaces
23 - 2 RGMII's on DTSEC4, DTSEC5
24 - 3 SGMII on DTSEC1, DTSEC2 & DTSEC3
27 -------------------------------------------------------------------------
[all …]
/openbmc/u-boot/board/freescale/t102xqds/
H A DREADME2 ------------------
4 combines two or one 64-bit Power Architecture e5500 core respectively with high
9 and general-purpose embedded computing. Its high level of integration offers
14 - two e5500 cores, each with a private 256 KB L2 cache
15 - Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
16 - Three levels of instructions: User, supervisor, and hypervisor
17 - Independent boot and reset
18 - Secure boot capability
19 - 256 KB shared L3 CoreNet platform cache (CPC)
20 - Interconnect CoreNet platform
[all …]
/openbmc/u-boot/include/configs/
H A DBSC9131RDB.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2011-2012 Freescale Semiconductor, Inc.
25 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
31 #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
32 #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE)
35 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
112 * Base addresses -- Note these are effective addresses where the
129 * 0x8800_0000 0x8810_0000 IFC internal SRAM 1M
131 * 0xC100_0000 0xC13F_FFFF MAPLE-2F 4M
137 * 0xFF80_0000 0xFFFF_FFFF Boot Page & NAND flash buffer 8M
[all …]
H A DC29XPCIE.h1 /* SPDX-License-Identifier: GPL-2.0+ */
45 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
46 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
73 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
77 * Memory space is mapped 1-1, but I/O space must start from 0.
143 * IFC Definitions
145 /* NOR Flash on IFC */
159 /* 16Bit NOR Flash - S29GL512S10TFI01 */
182 /* NAND Flash on IFC */
192 /* 8Bit NAND Flash - K9F1G08U0B */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dfsl-ls1043a-rdb.dts1 // SPDX-License-Identifier: GPL-2.0+ OR X11
3 * Device Tree Include file for Freescale Layerscape-1043A family SoC.
10 /dts-v1/;
11 /include/ "fsl-ls1043a.dtsi"
23 bus-num = <0>;
27 #address-cells = <1>;
28 #size-cells = <1>;
29 compatible = "spi-flash";
31 spi-max-frequency = <1000000>; /* input clock */
41 shunt-resistor = <1000>;
[all …]
/openbmc/u-boot/board/freescale/ls1046ardb/
H A DREADME2 --------
3 The LS1046A Reference Design Board (RDB) is a high-performance computing,
7 debugging environment. The LS1046A RDB is lead-free and RoHS-compliant.
10 --------------------
11 Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1046A
15 -----------------------
16 - SERDES1 Connections, 4 lanes supporting:
17 - Lane0: XFI with x1 RJ45 connector
18 - Lane1: XFI Cage
19 - Lane2: SGMII.5
[all …]
/openbmc/u-boot/doc/
H A DREADME.b4860qds2 --------
6 -------------
7 The B4860 QorIQ Qonverge device is a Freescale high-end, multicore SoC based on
11 expanding wireless markets, such as 3GLTE (FDD and TDD), LTE-Advanced, and UMTS.
13 The B4860 is a highly-integrated StarCore and Power Architecture processor that
15 . Six fully-programmable StarCore SC3900 FVP subsystems, divided into three
16 clusters-each core runs up to 1.2 GHz, with an architecture highly optimized for
18 . Four dual-thread e6500 Power Architecture processors organized in one cluster-each
20 . Two DDR3/3L controllers for high-speed, industry-standard memory interface each
22 . MAPLE-B3 hardware acceleration-for forward error correction schemes including
[all …]
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Du-boot-nand_spl.lds1 /* SPDX-License-Identifier: GPL-2.0+ */
27 __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
28 __fixup_entries = (. - _FIXUP_TABLE_) >> 2;
46 #if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
51 #define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
55 #error unknown NAND controller
68 ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big");

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