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/openbmc/linux/Documentation/devicetree/bindings/hwlock/
H A Dhwlock.txt1 Generic hwlock bindings
4 Generic bindings that are common to all the hwlock platform specific driver
7 Please also look through the individual platform specific hwlock binding
11 hwlock providers:
15 - #hwlock-cells: Specifies the number of cells needed to represent a
18 hwlock users:
21 Consumers that require specific hwlock(s) should specify them using the
22 property "hwlocks", and an optional "hwlock-names" property.
25 - hwlocks: List of phandle to a hwlock provider node and an
26 associated hwlock args specifier as indicated by
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H A Dsprd-hwspinlock.txt2 -------------------------------------
5 - compatible : should be "sprd,hwspinlock-r3p0".
6 - reg : the register address of hwspinlock.
7 - #hwlock-cells : hwlock users only use the hwlock id to represent a specific
8 hwlock, so the number of cells should be <1> here.
9 - clock-names : Must contain "enable".
10 - clocks : Must contain a phandle entry for the clock in clock-names, see the
13 Please look at the generic hwlock binding for usage information for consumers,
14 "Documentation/devicetree/bindings/hwlock/hwlock.txt"
16 Example of hwlock provider:
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H A Dst,stm32-hwspinlock.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/hwlock/st,stm32-hwspinlock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Fabien Dessenne <fabien.dessenne@foss.st.com>
13 "#hwlock-cells":
17 const: st,stm32-hwspinlock
25 clock-names:
27 - const: hsem
30 - "#hwlock-cells"
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/openbmc/linux/Documentation/devicetree/bindings/nvmem/
H A Dsprd-efuse.txt4 - compatible: Should be "sprd,ums312-efuse".
5 - reg: Specify the address offset of efuse controller.
6 - clock-names: Should be "enable".
7 - clocks: The phandle and specifier referencing the controller's clock.
8 - hwlocks: Reference to a phandle of a hwlock provider node.
17 compatible = "sprd,ums312-efuse";
19 clock-names = "enable";
20 hwlocks = <&hwlock 8>;
37 nvmem-cells = <&thermal_calib>;
38 nvmem-cell-names = "calibration";
H A Dsc27xx-efuse.txt4 - compatible: Should be one of the following.
5 "sprd,sc2720-efuse"
6 "sprd,sc2721-efuse"
7 "sprd,sc2723-efuse"
8 "sprd,sc2730-efuse"
9 "sprd,sc2731-efuse"
10 - reg: Specify the address offset of efuse controller.
11 - hwlocks: Reference to a phandle of a hwlock provider node.
22 spi-max-frequency = <26000000>;
24 interrupt-controller;
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/openbmc/linux/arch/arm64/boot/dts/sprd/
H A Dwhale2.dtsi6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
9 #include <dt-bindings/clock/sprd,sc9860-clk.h>
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
17 compatible = "simple-bus";
18 #address-cells = <2>;
19 #size-cells = <2>;
67 ap-apb {
68 compatible = "simple-bus";
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H A Dsc2731.dtsi6 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
13 spi-max-frequency = <26000000>;
15 interrupt-controller;
16 #interrupt-cells = <1>;
17 #address-cells = <1>;
18 #size-cells = <0>;
21 compatible = "sprd,sc2731-charger";
23 monitored-battery = <&bat>;
26 led-controller@200 {
27 compatible = "sprd,sc2731-bltc";
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/openbmc/linux/Documentation/devicetree/bindings/iio/adc/
H A Dsprd,sc2720-adc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/adc/sprd,sc2720-adc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Baolin Wang <baolin.wang7@gmail.com>
18 - sprd,sc2720-adc
19 - sprd,sc2721-adc
20 - sprd,sc2723-adc
21 - sprd,sc2730-adc
22 - sprd,sc2731-adc
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/openbmc/linux/drivers/pinctrl/stm32/
H A Dpinctrl-stm32.c1 // SPDX-License-Identifier: GPL-2.0
28 #include <linux/pinctrl/pinconf-generic.h>
35 #include "../pinctrl-utils.h"
36 #include "pinctrl-stm32.h"
116 struct hwspinlock *hwlock; member
149 return function - 1; in stm32_gpio_get_alt()
160 bank->pin_backup[offset] &= ~BIT(STM32_GPIO_BKP_VAL); in stm32_gpio_backup_value()
161 bank->pin_backup[offset] |= value << STM32_GPIO_BKP_VAL; in stm32_gpio_backup_value()
167 bank->pin_backup[offset] &= ~(STM32_GPIO_BKP_MODE_MASK | in stm32_gpio_backup_mode()
169 bank->pin_backup[offset] |= mode << STM32_GPIO_BKP_MODE_SHIFT; in stm32_gpio_backup_mode()
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/openbmc/linux/drivers/hwspinlock/
H A Dhwspinlock_core.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com
7 * Contact: Ohad Ben-Cohen <ohad@wizery.com>
19 #include <linux/radix-tree.h>
36 * and provides easy-to-use API which makes the hwspinlock core code simple
54 * as the radix-tree API requires that users provide all synchronisation.
55 * A mutex is needed because we're using non-atomic radix tree allocations.
61 * __hwspin_trylock() - attempt to lock a specific hwspinlock
62 * @hwlock: an hwspinlock which we want to trylock
72 * user need some time-consuming or sleepable operations under the hardware
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/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dsprd,spi-adi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/sprd,spi-adi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Orson Zhai <orsonzhai@gmail.com>
11 - Baolin Wang <baolin.wang7@gmail.com>
12 - Chunyan Zhang <zhang.lyra@gmail.com>
15 ADI is the abbreviation of Anolog-Digital interface, which is used to access
28 Thus we introduce one property named "sprd,hw-channels" to configure hardware
33 Since we have multi-subsystems will use unique ADI to access analog chip, when
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dipq5332.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
5 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
8 #include <dt-bindings/clock/qcom,apss-ipq.h>
9 #include <dt-bindings/clock/qcom,ipq5332-gcc.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 interrupt-parent = <&intc>;
14 #address-cells = <2>;
15 #size-cells = <2>;
18 sleep_clk: sleep-clk {
19 compatible = "fixed-clock";
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H A Dsm4450.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 interrupt-parent = <&intc>;
12 #address-cells = <2>;
13 #size-cells = <2>;
18 xo_board: xo-board {
19 compatible = "fixed-clock";
20 clock-frequency = <76800000>;
21 #clock-cells = <0>;
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H A Dsdx75.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom,rpmhpd.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
19 interrupt-parent = <&intc>;
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H A Dipq6018.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-ipq6018.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq6018.h>
11 #include <dt-bindings/clock/qcom,apss-ipq.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&intc>;
19 sleep_clk: sleep-clk {
20 compatible = "fixed-clock";
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H A Dipq9574.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&intc>;
17 #address-cells = <2>;
18 #size-cells = <2>;
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H A Dipq8074.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq8074.h>
10 #address-cells = <2>;
11 #size-cells = <2>;
15 interrupt-parent = <&intc>;
19 compatible = "fixed-clock";
20 clock-frequency = <32768>;
21 #clock-cells = <0>;
25 compatible = "fixed-clock";
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H A Dmsm8994.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8994.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8994.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/power/qcom-rpmpd.h>
14 interrupt-parent = <&intc>;
16 #address-cells = <2>;
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H A Dmsm8976.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
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/openbmc/linux/arch/arm/boot/dts/qcom/
H A Dqcom-sdx65.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
15 #include <dt-bindings/interconnect/qcom,sdx65.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
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H A Dqcom-msm8226.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
6 /dts-v1/;
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/clock/qcom,gcc-msm8974.h>
10 #include <dt-bindings/clock/qcom,mmcc-msm8974.h>
11 #include <dt-bindings/clock/qcom,rpmcc.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/reset/qcom,gcc-msm8974.h>
17 #address-cells = <1>;
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H A Dqcom-sdx55.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,gcc-sdx55.h>
10 #include <dt-bindings/clock/qcom,rpmh.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interconnect/qcom,sdx55.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
15 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
18 #address-cells = <1>;
19 #size-cells = <1>;
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H A Dqcom-apq8084.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-apq8084.h>
6 #include <dt-bindings/gpio/gpio.h>
9 #address-cells = <1>;
10 #size-cells = <1>;
13 interrupt-parent = <&intc>;
15 reserved-memory {
16 #address-cells = <1>;
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H A Dqcom-ipq8064.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 /dts-v1/;
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
11 #include <dt-bindings/soc/qcom,gsbi.h>
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/openbmc/u-boot/arch/arm/dts/
H A Ddm816x.dtsi7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/pinctrl/omap.h>
12 interrupt-parent = <&intc>;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
31 compatible = "arm,cortex-a8";
38 compatible = "arm,cortex-a8-pmu";
47 compatible = "ti,omap-infra";
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