| /openbmc/linux/drivers/usb/gadget/udc/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
7 # NOTE: Gadget support ** DOES NOT ** depend on host-side CONFIG_USB !!
9 # - Host systems (like PCs) need CONFIG_USB (with "A" jacks).
10 # - Peripherals (like PDAs) need CONFIG_USB_GADGET (with "B" jacks).
11 # - Some systems have both kinds of controllers.
13 # With help from a special transceiver and a "Mini-AB" jack, systems with
14 # both kinds of controller can also support "USB On-the-Go" (CONFIG_USB_OTG).
22 # - integrated/SOC controllers first
23 # - licensed IP used in both SOC and discrete versions
24 # - discrete ones (including all PCI-only controllers)
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| /openbmc/linux/Documentation/hwmon/ |
| H A D | vt1211.rst | 10 Addresses scanned: none, address read from Super-I/O config space
24 -----------------
29 configuration for channels 1-5.
30 Legal values are in the range of 0-31. Bit 0 maps to
36 Override the BIOS default temperature interrupt mode.
38 mode 0. In this mode, any pending interrupt is cleared
47 -----------
49 The VIA VT1211 Super-I/O chip includes complete hardware monitoring
52 implements 5 universal input channels (UCH1-5) that can be individually
57 mode doesn't seem to work as advertised in the datasheet. In fact I couldn't
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| H A D | w83792d.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
19 -----------------
35 -----------
42 parameter; this will put it into a more well-behaved state first.
44 The driver implements three temperature sensors, seven fan rotation speed
46 strategies called: Smart Fan I (Thermal Cruise mode) and Smart Fan II.
48 The driver also implements up to seven fan control outputs: pwm1-7. Pwm1-7
53 Automatic fan control mode is possible only for fan1-fan3.
55 For all pwmX outputs, a value of 0 means minimum fan speed and a value of
56 255 means maximum fan speed.
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| H A D | nct6775.rst | 19 * Nuvoton NCT5572D/NCT6771F/NCT6772F/NCT6775F/W83677HG-I
83 * Nuvoton NCT6796D-S/NCT6799D-R
93 Guenter Roeck <linux@roeck-us.net>
96 -----------
106 There are 4 to 5 fan rotation speed sensors, 8 to 15 analog voltage sensors,
108 fan regulation strategies (plus manual fan control mode).
116 the high limit; it stays on until the temperature falls below the hysteresis
120 triggered if the rotation speed has dropped below a programmable limit. On
123 do not have a fan speed divider. The driver sets the most suitable fan divisor
124 itself; specifically, it increases the divider value each time a fan speed
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| H A D | f71805f.rst | 44 -----------
57 The Fintek F71806F/FG Super-I/O chip is essentially the same as the
65 ------------------
67 Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported
84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V
89 in6 VIN6 VCC1.5V 10K - 1.00 1.50 V
90 in7 VIN7 VCORE 10K - 1.00 ~1.40 V [1]_
106 Each voltage measured has associated low and high limits, each of which
111 --------------
113 Fan rotation speeds are reported as 12-bit values from a gated clock
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| H A D | adm9240.rst | 10 Addresses scanned: I2C 0x2c - 0x2f
20 Addresses scanned: I2C 0x2c - 0x2f
24 http://pdfserv.maxim-ic.com/en/ds/DS1780.pdf
30 Addresses scanned: I2C 0x2c - 0x2f
37 - Frodo Looijaard <frodol@dds.nl>,
38 - Philip Edelbrock <phil@netroedge.com>,
39 - Michiel Rook <michiel@grendelproject.nl>,
40 - Grant Coady <gcoady.lk@gmail.com> with guidance
44 ---------
46 chip MSB 5-bit address. Each chip reports a unique manufacturer
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| H A D | w83627ehf.rst | 22 * Winbond W83627DHG-P
46 * Winbond W83667HG-B
54 * Nuvoton NCT6775F/W83667HG-I
73 - Jean Delvare <jdelvare@suse.de>
74 - Yuan Mu (Winbond)
75 - Rudolf Marek <r.marek@assembler.cz>
76 - David Hubbard <david.c.hubbard@gmail.com>
77 - Gong Jun <JGong@nuvoton.com>
80 -----------
83 W83627DHG, W83627DHG-P, W83627UHG, W83667HG, W83667HG-B, W83667HG-I
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| /openbmc/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | smu7_thermal.c | 32 if (hwmgr->thermal_controller.fanInfo.bNoFan) in smu7_fan_ctrl_get_fan_speed_info()
33 return -ENODEV; in smu7_fan_ctrl_get_fan_speed_info()
35 fan_speed_info->supports_percent_read = true; in smu7_fan_ctrl_get_fan_speed_info()
36 fan_speed_info->supports_percent_write = true; in smu7_fan_ctrl_get_fan_speed_info()
37 fan_speed_info->min_percent = 0; in smu7_fan_ctrl_get_fan_speed_info()
38 fan_speed_info->max_percent = 100; in smu7_fan_ctrl_get_fan_speed_info()
41 hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) { in smu7_fan_ctrl_get_fan_speed_info()
42 fan_speed_info->supports_rpm_read = true; in smu7_fan_ctrl_get_fan_speed_info()
43 fan_speed_info->supports_rpm_write = true; in smu7_fan_ctrl_get_fan_speed_info()
44 fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM; in smu7_fan_ctrl_get_fan_speed_info()
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| H A D | vega10_thermal.c | 42 if (hwmgr->thermal_controller.fanInfo.bNoFan) in vega10_fan_ctrl_get_fan_speed_info()
45 fan_speed_info->supports_percent_read = true; in vega10_fan_ctrl_get_fan_speed_info()
46 fan_speed_info->supports_percent_write = true; in vega10_fan_ctrl_get_fan_speed_info()
47 fan_speed_info->min_percent = 0; in vega10_fan_ctrl_get_fan_speed_info()
48 fan_speed_info->max_percent = 100; in vega10_fan_ctrl_get_fan_speed_info()
51 hwmgr->thermal_controller.fanInfo. in vega10_fan_ctrl_get_fan_speed_info()
53 fan_speed_info->supports_rpm_read = true; in vega10_fan_ctrl_get_fan_speed_info()
54 fan_speed_info->supports_rpm_write = true; in vega10_fan_ctrl_get_fan_speed_info()
55 fan_speed_info->min_rpm = in vega10_fan_ctrl_get_fan_speed_info()
56 hwmgr->thermal_controller.fanInfo.ulMinRPM; in vega10_fan_ctrl_get_fan_speed_info()
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| H A D | vega20_thermal.c | 34 struct vega20_hwmgr *data = hwmgr->backend; in vega20_disable_fan_control_feature()
37 if (data->smu_features[GNLD_FAN_CONTROL].supported) { in vega20_disable_fan_control_feature()
40 data->smu_features[GNLD_FAN_CONTROL]. in vega20_disable_fan_control_feature()
45 data->smu_features[GNLD_FAN_CONTROL].enabled = false; in vega20_disable_fan_control_feature()
53 struct vega20_hwmgr *data = hwmgr->backend; in vega20_fan_ctrl_stop_smc_fan_control()
55 if (data->smu_features[GNLD_FAN_CONTROL].supported) in vega20_fan_ctrl_stop_smc_fan_control()
63 struct vega20_hwmgr *data = hwmgr->backend; in vega20_enable_fan_control_feature()
66 if (data->smu_features[GNLD_FAN_CONTROL].supported) { in vega20_enable_fan_control_feature()
69 data->smu_features[GNLD_FAN_CONTROL]. in vega20_enable_fan_control_feature()
74 data->smu_features[GNLD_FAN_CONTROL].enabled = true; in vega20_enable_fan_control_feature()
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| /openbmc/linux/Documentation/devicetree/bindings/mmc/ |
| H A D | mmc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cells":
30 "#size-cells":
37 broken-cd:
42 cd-gpios:
47 non-removable:
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| /openbmc/u-boot/drivers/i2c/ |
| H A D | omap24xx_i2c.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2004-2010
51 #define I2C_CON_BE (1 << 14) /* Big endian mode */
52 #define I2C_CON_STB (1 << 11) /* Start byte mode (master mode only) */
53 #define I2C_CON_MST (1 << 10) /* Master/slave mode */
54 #define I2C_CON_TRX (1 << 9) /* Transmitter/receiver mode */
55 /* (master mode only) */
57 #define I2C_CON_STP (1 << 1) /* Stop condition (master mode only) */
58 #define I2C_CON_STT (1 << 0) /* Start condition (master mode only) */
63 #define I2C_SYSTEST_FREE (1 << 14) /* Free running mode, on brkpoint) */
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| /openbmc/linux/drivers/phy/qualcomm/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0-only
36 Support for the USB PHY-s on Qualcomm IPQ40xx SoC-s.
111 PHY transceivers working only in USB3 mode on Qualcomm chips. This
124 controllers on Qualcomm chips. This driver supports the high-speed
133 Enable support for the USB high-speed SNPS eUSB2 phy on Qualcomm
142 Enable support for the USB high-speed SNPS eUSB2 repeater on Qualcomm
155 host only mode configurations.
160 depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in
163 Support for the USB high-speed ULPI compliant phy on Qualcomm
171 Enable support for the USB high-speed SNPS Femto phy on Qualcomm
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| /openbmc/linux/include/dt-bindings/pinctrl/ |
| H A D | k210-fpioa.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
11 * kendryte-standalone-sdk/lib/drivers/include/fpioa.h
16 #define K210_PCF_JTAG_TMS 2 /* JTAG Test Mode Select */
32 #define K210_PCF_UARTHS_RX 18 /* UART High speed Receiver */
33 #define K210_PCF_UARTHS_TX 19 /* UART High speed Transmitter */
38 #define K210_PCF_GPIOHS0 24 /* GPIO High speed 0 */
39 #define K210_PCF_GPIOHS1 25 /* GPIO High speed 1 */
40 #define K210_PCF_GPIOHS2 26 /* GPIO High speed 2 */
41 #define K210_PCF_GPIOHS3 27 /* GPIO High speed 3 */
42 #define K210_PCF_GPIOHS4 28 /* GPIO High speed 4 */
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| /openbmc/linux/drivers/usb/dwc2/ |
| H A D | hcd.h | 1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
3 * hcd.h - DesignWare HS OTG Controller host-mode declarations
5 * Copyright (C) 2004-2013 Synopsys, Inc.
24 * struct dwc2_host_chan - Software host channel descriptor
30 * @speed: Device speed. One of the following values:
31 * - USB_SPEED_LOW
32 * - USB_SPEED_FULL
33 * - USB_SPEED_HIGH
35 * - USB_ENDPOINT_XFER_CONTROL: 0
36 * - USB_ENDPOINT_XFER_ISOC: 1
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
10 Say Y here if your system has a Dual Role Hi-Speed USB
13 For host mode, if you choose to build the driver as dynamically
18 dwc2_platform.ko. For all modes(host, gadget and dual-role), there
24 bool "DWC2 Mode Selection"
30 bool "Host only mode"
33 The Designware USB2.0 high-speed host controller
35 driver to operate in Host-only mode.
37 comment "Gadget/Dual-role mode requires USB Gadget support to be enabled"
40 bool "Gadget only mode"
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| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | nvidia,tegra-pinmux-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 Please refer to pinctrl-bindings.txt in this directory for details of the
22 pin configuration parameters, such as pull-up, tristate, drive strength,
46 $ref: /schemas/types.yaml#/definitions/string-array
57 description: Pull-down/up setting to apply to the pin.
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| /openbmc/u-boot/drivers/clk/ |
| H A D | mpc83xx_clk.c | 1 // SPDX-License-Identifier: GPL-2.0+
8 #include <clk-uclass.h>
11 #include <dt-bindings/clk/mpc83xx-clk.h>
19 * struct mpc83xx_clk_priv - Private data structure for the MPC83xx clock
21 * @speed: Array containing the speed values of all system clocks (initialized
25 u32 speed[MPC83XX_CLK_COUNT]; member
29 * is_clk_valid() - Check if clock ID is valid for given clock device
86 * init_single_clk() - Initialize a clock with a given ID
90 * The clock speed is read from the hardware's registers, and stored in the
94 * Return: 0 if OK, -ve on error
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| H A D | mpc83xx_clk.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
8 * enum ratio - Description of a core clock ratio
34 * struct corecnf - Description for a core clock configuration
79 * enum reg_type - Register to read a field from
89 * enum mode_type - Description of how to read a specific frequency value
99 * @TYPE_SPECIAL: The frequency is calculated in a non-standard way
109 /* Map of each clock index to its human-readable name */
136 * struct clk_mode - Structure for clock mode descriiptions
137 * @low: The low bit of the data field to read for this mode (may not apply to
139 * @high: The high bit of the data field to read for this mode (may not apply to
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| /openbmc/linux/Documentation/devicetree/bindings/media/i2c/ |
| H A D | adv7343.txt | 3 The ADV7343 are high speed, digital-to-analog video encoders in a 64-lead LQFP
4 package. Six high speed, 3.3 V, 11-bit video DACs provide support for composite
5 (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard
6 definition (SD), enhanced definition (ED), or high definition (HD) video
10 - compatible: Must be "adi,adv7343"
13 - adi,power-mode-sleep-mode: on enable the current consumption is reduced to
16 - adi,power-mode-pll-ctrl: PLL and oversampling control. This control allows
19 - ad,adv7343-power-mode-dac: array configuring the power on/off DAC's 1..6,
22 - ad,adv7343-sd-config-dac-out: array configure SD DAC Output's 1 and 2, 0 = OFF
38 adi,power-mode-sleep-mode;
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| /openbmc/linux/tools/spi/ |
| H A D | spidev_test.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * Cross-compile with cross-gcc -I/path/to/cross-kernel/include
39 static uint32_t mode; variable
43 static uint32_t speed = 500000; variable
71 while (length-- > 0) { in hex_dump()
91 * Unescape - process hexadecimal escape character
92 * converts shell input "\x23" -> 0x23
127 .speed_hz = speed, in transfer()
131 if (mode & SPI_TX_OCTAL) in transfer()
133 else if (mode & SPI_TX_QUAD) in transfer()
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| /openbmc/linux/Documentation/admin-guide/pm/ |
| H A D | intel-speed-select.rst | 1 .. SPDX-License-Identifier: GPL-2.0
4 Intel(R) Speed Select Technology User Guide
7 The Intel(R) Speed Select Technology (Intel(R) SST) provides a powerful new
14 - https://www.intel.com/content/www/us/en/architecture-and-technology/speed-select-technology-artic…
15 - https://builders.intel.com/docs/networkbuilders/intel-speed-select-technology-base-frequency-enha…
19 dynamically without pre-configuring via BIOS setup options. This dynamic
21 and configure these features is by using the Intel Speed Select utility.
23 This document explains how to use the Intel Speed Select tool to enumerate and
29 intel-speed-select configuration tool
32 Most Linux distribution packages may include the "intel-speed-select" tool. If not,
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| /openbmc/linux/arch/arm/boot/dts/st/ |
| H A D | stih410-b2260.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "st,stih410-b2260", "st,stih410";
15 stdout-path = &uart1;
29 compatible = "gpio-leds";
30 led-user-green-1 {
33 linux,default-trigger = "heartbeat";
34 default-state = "off";
37 led-user-green-2 {
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| /openbmc/u-boot/arch/arm/dts/ |
| H A D | stih410-b2260.dts | 9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
15 compatible = "st,stih410-b2260", "st,stih410";
19 linux,stdout-path = &uart1;
20 stdout-path = &uart1;
36 compatible = "gpio-leds";
40 linux,default-trigger = "heartbeat";
41 default-state = "off";
47 default-state = "off";
53 default-state = "off";
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| /openbmc/linux/Documentation/devicetree/bindings/i2c/ |
| H A D | i2c-exynos5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-exynos5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung's High Speed I2C controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The Samsung's High Speed I2C controller is used to interface with I2C devices
19 Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml for details.
24 - enum:
25 - samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420
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