1e098bc96SEvan Quan /*
2e098bc96SEvan Quan * Copyright 2016 Advanced Micro Devices, Inc.
3e098bc96SEvan Quan *
4e098bc96SEvan Quan * Permission is hereby granted, free of charge, to any person obtaining a
5e098bc96SEvan Quan * copy of this software and associated documentation files (the "Software"),
6e098bc96SEvan Quan * to deal in the Software without restriction, including without limitation
7e098bc96SEvan Quan * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8e098bc96SEvan Quan * and/or sell copies of the Software, and to permit persons to whom the
9e098bc96SEvan Quan * Software is furnished to do so, subject to the following conditions:
10e098bc96SEvan Quan *
11e098bc96SEvan Quan * The above copyright notice and this permission notice shall be included in
12e098bc96SEvan Quan * all copies or substantial portions of the Software.
13e098bc96SEvan Quan *
14e098bc96SEvan Quan * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15e098bc96SEvan Quan * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16e098bc96SEvan Quan * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17e098bc96SEvan Quan * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18e098bc96SEvan Quan * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19e098bc96SEvan Quan * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20e098bc96SEvan Quan * OTHER DEALINGS IN THE SOFTWARE.
21e098bc96SEvan Quan *
22e098bc96SEvan Quan */
23e098bc96SEvan Quan
24e098bc96SEvan Quan #include "vega10_thermal.h"
25e098bc96SEvan Quan #include "vega10_hwmgr.h"
26e098bc96SEvan Quan #include "vega10_smumgr.h"
27e098bc96SEvan Quan #include "vega10_ppsmc.h"
28e098bc96SEvan Quan #include "vega10_inc.h"
29e098bc96SEvan Quan #include "soc15_common.h"
30e098bc96SEvan Quan #include "pp_debug.h"
31e098bc96SEvan Quan
vega10_get_current_rpm(struct pp_hwmgr * hwmgr,uint32_t * current_rpm)32e098bc96SEvan Quan static int vega10_get_current_rpm(struct pp_hwmgr *hwmgr, uint32_t *current_rpm)
33e098bc96SEvan Quan {
34e098bc96SEvan Quan smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetCurrentRpm, current_rpm);
35e098bc96SEvan Quan return 0;
36e098bc96SEvan Quan }
37e098bc96SEvan Quan
vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr * hwmgr,struct phm_fan_speed_info * fan_speed_info)38e098bc96SEvan Quan int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr,
39e098bc96SEvan Quan struct phm_fan_speed_info *fan_speed_info)
40e098bc96SEvan Quan {
41e098bc96SEvan Quan
42e098bc96SEvan Quan if (hwmgr->thermal_controller.fanInfo.bNoFan)
43e098bc96SEvan Quan return 0;
44e098bc96SEvan Quan
45e098bc96SEvan Quan fan_speed_info->supports_percent_read = true;
46e098bc96SEvan Quan fan_speed_info->supports_percent_write = true;
47e098bc96SEvan Quan fan_speed_info->min_percent = 0;
48e098bc96SEvan Quan fan_speed_info->max_percent = 100;
49e098bc96SEvan Quan
50e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) &&
51e098bc96SEvan Quan hwmgr->thermal_controller.fanInfo.
52e098bc96SEvan Quan ucTachometerPulsesPerRevolution) {
53e098bc96SEvan Quan fan_speed_info->supports_rpm_read = true;
54e098bc96SEvan Quan fan_speed_info->supports_rpm_write = true;
55e098bc96SEvan Quan fan_speed_info->min_rpm =
56e098bc96SEvan Quan hwmgr->thermal_controller.fanInfo.ulMinRPM;
57e098bc96SEvan Quan fan_speed_info->max_rpm =
58e098bc96SEvan Quan hwmgr->thermal_controller.fanInfo.ulMaxRPM;
59e098bc96SEvan Quan } else {
60e098bc96SEvan Quan fan_speed_info->min_rpm = 0;
61e098bc96SEvan Quan fan_speed_info->max_rpm = 0;
62e098bc96SEvan Quan }
63e098bc96SEvan Quan
64e098bc96SEvan Quan return 0;
65e098bc96SEvan Quan }
66e098bc96SEvan Quan
vega10_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr * hwmgr,uint32_t * speed)670d8318e1SEvan Quan int vega10_fan_ctrl_get_fan_speed_pwm(struct pp_hwmgr *hwmgr,
68e098bc96SEvan Quan uint32_t *speed)
69e098bc96SEvan Quan {
70*30b8e7b8SAsher Song struct amdgpu_device *adev = hwmgr->adev;
71*30b8e7b8SAsher Song uint32_t duty100, duty;
72*30b8e7b8SAsher Song uint64_t tmp64;
73e098bc96SEvan Quan
74*30b8e7b8SAsher Song duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
75*30b8e7b8SAsher Song CG_FDO_CTRL1, FMAX_DUTY100);
76*30b8e7b8SAsher Song duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS),
77*30b8e7b8SAsher Song CG_THERMAL_STATUS, FDO_PWM_DUTY);
78e098bc96SEvan Quan
79*30b8e7b8SAsher Song if (!duty100)
80*30b8e7b8SAsher Song return -EINVAL;
81e098bc96SEvan Quan
82*30b8e7b8SAsher Song tmp64 = (uint64_t)duty * 255;
83*30b8e7b8SAsher Song do_div(tmp64, duty100);
84*30b8e7b8SAsher Song *speed = MIN((uint32_t)tmp64, 255);
85e098bc96SEvan Quan
86e098bc96SEvan Quan return 0;
87e098bc96SEvan Quan }
88e098bc96SEvan Quan
vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr * hwmgr,uint32_t * speed)89e098bc96SEvan Quan int vega10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed)
90e098bc96SEvan Quan {
91e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
92e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
93e098bc96SEvan Quan uint32_t tach_period;
94e098bc96SEvan Quan uint32_t crystal_clock_freq;
95e098bc96SEvan Quan int result = 0;
96e098bc96SEvan Quan
97e098bc96SEvan Quan if (hwmgr->thermal_controller.fanInfo.bNoFan)
98e098bc96SEvan Quan return -1;
99e098bc96SEvan Quan
100e098bc96SEvan Quan if (data->smu_features[GNLD_FAN_CONTROL].supported) {
101e098bc96SEvan Quan result = vega10_get_current_rpm(hwmgr, speed);
102e098bc96SEvan Quan } else {
103e098bc96SEvan Quan tach_period =
104e098bc96SEvan Quan REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_STATUS),
105e098bc96SEvan Quan CG_TACH_STATUS,
106e098bc96SEvan Quan TACH_PERIOD);
107e098bc96SEvan Quan
108e098bc96SEvan Quan if (tach_period == 0)
109e098bc96SEvan Quan return -EINVAL;
110e098bc96SEvan Quan
111e098bc96SEvan Quan crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
112e098bc96SEvan Quan
113e098bc96SEvan Quan *speed = 60 * crystal_clock_freq * 10000 / tach_period;
114e098bc96SEvan Quan }
115e098bc96SEvan Quan
116e098bc96SEvan Quan return result;
117e098bc96SEvan Quan }
118e098bc96SEvan Quan
119e098bc96SEvan Quan /**
120d9261648SLee Jones * vega10_fan_ctrl_set_static_mode - Set Fan Speed Control to static mode,
121e098bc96SEvan Quan * so that the user can decide what speed to use.
122d9261648SLee Jones * @hwmgr: the address of the powerplay hardware manager.
123d9261648SLee Jones * @mode: the fan control mode, 0 default, 1 by percent, 5, by RPM
124d9261648SLee Jones * Exception: Should always succeed.
125e098bc96SEvan Quan */
vega10_fan_ctrl_set_static_mode(struct pp_hwmgr * hwmgr,uint32_t mode)126e098bc96SEvan Quan int vega10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
127e098bc96SEvan Quan {
128e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
129e098bc96SEvan Quan
130e098bc96SEvan Quan if (hwmgr->fan_ctrl_is_in_default_mode) {
131e098bc96SEvan Quan hwmgr->fan_ctrl_default_mode =
132e098bc96SEvan Quan REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
133e098bc96SEvan Quan CG_FDO_CTRL2, FDO_PWM_MODE);
134e098bc96SEvan Quan hwmgr->tmin =
135e098bc96SEvan Quan REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
136e098bc96SEvan Quan CG_FDO_CTRL2, TMIN);
137e098bc96SEvan Quan hwmgr->fan_ctrl_is_in_default_mode = false;
138e098bc96SEvan Quan }
139e098bc96SEvan Quan
140e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
141e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
142e098bc96SEvan Quan CG_FDO_CTRL2, TMIN, 0));
143e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
144e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
145e098bc96SEvan Quan CG_FDO_CTRL2, FDO_PWM_MODE, mode));
146e098bc96SEvan Quan
147e098bc96SEvan Quan return 0;
148e098bc96SEvan Quan }
149e098bc96SEvan Quan
150e098bc96SEvan Quan /**
151d9261648SLee Jones * vega10_fan_ctrl_set_default_mode - Reset Fan Speed Control to default mode.
152d9261648SLee Jones * @hwmgr: the address of the powerplay hardware manager.
153d9261648SLee Jones * Exception: Should always succeed.
154e098bc96SEvan Quan */
vega10_fan_ctrl_set_default_mode(struct pp_hwmgr * hwmgr)155e098bc96SEvan Quan int vega10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr)
156e098bc96SEvan Quan {
157e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
158e098bc96SEvan Quan
159e098bc96SEvan Quan if (!hwmgr->fan_ctrl_is_in_default_mode) {
160e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
161e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
162e098bc96SEvan Quan CG_FDO_CTRL2, FDO_PWM_MODE,
163e098bc96SEvan Quan hwmgr->fan_ctrl_default_mode));
164e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
165e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
166e098bc96SEvan Quan CG_FDO_CTRL2, TMIN,
167e098bc96SEvan Quan hwmgr->tmin << CG_FDO_CTRL2__TMIN__SHIFT));
168e098bc96SEvan Quan hwmgr->fan_ctrl_is_in_default_mode = true;
169e098bc96SEvan Quan }
170e098bc96SEvan Quan
171e098bc96SEvan Quan return 0;
172e098bc96SEvan Quan }
173e098bc96SEvan Quan
174e098bc96SEvan Quan /**
175d9261648SLee Jones * vega10_enable_fan_control_feature - Enables the SMC Fan Control Feature.
176e098bc96SEvan Quan *
177d9261648SLee Jones * @hwmgr: the address of the powerplay hardware manager.
178d9261648SLee Jones * Return: 0 on success. -1 otherwise.
179e098bc96SEvan Quan */
vega10_enable_fan_control_feature(struct pp_hwmgr * hwmgr)180e098bc96SEvan Quan static int vega10_enable_fan_control_feature(struct pp_hwmgr *hwmgr)
181e098bc96SEvan Quan {
182e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
183e098bc96SEvan Quan
184e098bc96SEvan Quan if (data->smu_features[GNLD_FAN_CONTROL].supported) {
185e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
186e098bc96SEvan Quan hwmgr, true,
187e098bc96SEvan Quan data->smu_features[GNLD_FAN_CONTROL].
188e098bc96SEvan Quan smu_feature_bitmap),
189e098bc96SEvan Quan "Attempt to Enable FAN CONTROL feature Failed!",
190e098bc96SEvan Quan return -1);
191e098bc96SEvan Quan data->smu_features[GNLD_FAN_CONTROL].enabled = true;
192e098bc96SEvan Quan }
193e098bc96SEvan Quan
194e098bc96SEvan Quan return 0;
195e098bc96SEvan Quan }
196e098bc96SEvan Quan
vega10_disable_fan_control_feature(struct pp_hwmgr * hwmgr)197e098bc96SEvan Quan static int vega10_disable_fan_control_feature(struct pp_hwmgr *hwmgr)
198e098bc96SEvan Quan {
199e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
200e098bc96SEvan Quan
201e098bc96SEvan Quan if (data->smu_features[GNLD_FAN_CONTROL].supported) {
202e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(
203e098bc96SEvan Quan hwmgr, false,
204e098bc96SEvan Quan data->smu_features[GNLD_FAN_CONTROL].
205e098bc96SEvan Quan smu_feature_bitmap),
206e098bc96SEvan Quan "Attempt to Enable FAN CONTROL feature Failed!",
207e098bc96SEvan Quan return -1);
208e098bc96SEvan Quan data->smu_features[GNLD_FAN_CONTROL].enabled = false;
209e098bc96SEvan Quan }
210e098bc96SEvan Quan
211e098bc96SEvan Quan return 0;
212e098bc96SEvan Quan }
213e098bc96SEvan Quan
vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr * hwmgr)214e098bc96SEvan Quan int vega10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr)
215e098bc96SEvan Quan {
216e098bc96SEvan Quan if (hwmgr->thermal_controller.fanInfo.bNoFan)
217e098bc96SEvan Quan return -1;
218e098bc96SEvan Quan
219e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!vega10_enable_fan_control_feature(hwmgr),
220e098bc96SEvan Quan "Attempt to Enable SMC FAN CONTROL Feature Failed!",
221e098bc96SEvan Quan return -1);
222e098bc96SEvan Quan
223e098bc96SEvan Quan return 0;
224e098bc96SEvan Quan }
225e098bc96SEvan Quan
226e098bc96SEvan Quan
vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr * hwmgr)227e098bc96SEvan Quan int vega10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr)
228e098bc96SEvan Quan {
229e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
230e098bc96SEvan Quan
231e098bc96SEvan Quan if (hwmgr->thermal_controller.fanInfo.bNoFan)
232e098bc96SEvan Quan return -1;
233e098bc96SEvan Quan
234e098bc96SEvan Quan if (data->smu_features[GNLD_FAN_CONTROL].supported) {
235e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!vega10_disable_fan_control_feature(hwmgr),
236e098bc96SEvan Quan "Attempt to Disable SMC FAN CONTROL Feature Failed!",
237e098bc96SEvan Quan return -1);
238e098bc96SEvan Quan }
239e098bc96SEvan Quan return 0;
240e098bc96SEvan Quan }
241e098bc96SEvan Quan
242e098bc96SEvan Quan /**
2430d8318e1SEvan Quan * vega10_fan_ctrl_set_fan_speed_pwm - Set Fan Speed in PWM.
244d9261648SLee Jones * @hwmgr: the address of the powerplay hardware manager.
2450d8318e1SEvan Quan * @speed: is the percentage value (0 - 255) to be set.
246e098bc96SEvan Quan */
vega10_fan_ctrl_set_fan_speed_pwm(struct pp_hwmgr * hwmgr,uint32_t speed)2470d8318e1SEvan Quan int vega10_fan_ctrl_set_fan_speed_pwm(struct pp_hwmgr *hwmgr,
248e098bc96SEvan Quan uint32_t speed)
249e098bc96SEvan Quan {
250e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
251e098bc96SEvan Quan uint32_t duty100;
252e098bc96SEvan Quan uint32_t duty;
253e098bc96SEvan Quan uint64_t tmp64;
254e098bc96SEvan Quan
255e098bc96SEvan Quan if (hwmgr->thermal_controller.fanInfo.bNoFan)
256e098bc96SEvan Quan return 0;
257e098bc96SEvan Quan
2580d8318e1SEvan Quan speed = MIN(speed, 255);
259e098bc96SEvan Quan
260e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
261e098bc96SEvan Quan vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
262e098bc96SEvan Quan
263e098bc96SEvan Quan duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
264e098bc96SEvan Quan CG_FDO_CTRL1, FMAX_DUTY100);
265e098bc96SEvan Quan
266e098bc96SEvan Quan if (duty100 == 0)
267e098bc96SEvan Quan return -EINVAL;
268e098bc96SEvan Quan
269e098bc96SEvan Quan tmp64 = (uint64_t)speed * duty100;
2700d8318e1SEvan Quan do_div(tmp64, 255);
271e098bc96SEvan Quan duty = (uint32_t)tmp64;
272e098bc96SEvan Quan
273e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
274e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
275e098bc96SEvan Quan CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
276e098bc96SEvan Quan
277e098bc96SEvan Quan return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
278e098bc96SEvan Quan }
279e098bc96SEvan Quan
280e098bc96SEvan Quan /**
281d9261648SLee Jones * vega10_fan_ctrl_reset_fan_speed_to_default - Reset Fan Speed to default.
282d9261648SLee Jones * @hwmgr: the address of the powerplay hardware manager.
283d9261648SLee Jones * Exception: Always succeeds.
284e098bc96SEvan Quan */
vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr * hwmgr)285e098bc96SEvan Quan int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr)
286e098bc96SEvan Quan {
287e098bc96SEvan Quan if (hwmgr->thermal_controller.fanInfo.bNoFan)
288e098bc96SEvan Quan return 0;
289e098bc96SEvan Quan
290e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
291e098bc96SEvan Quan return vega10_fan_ctrl_start_smc_fan_control(hwmgr);
292e098bc96SEvan Quan else
293e098bc96SEvan Quan return vega10_fan_ctrl_set_default_mode(hwmgr);
294e098bc96SEvan Quan }
295e098bc96SEvan Quan
296e098bc96SEvan Quan /**
297d9261648SLee Jones * vega10_fan_ctrl_set_fan_speed_rpm - Set Fan Speed in RPM.
298d9261648SLee Jones * @hwmgr: the address of the powerplay hardware manager.
299d9261648SLee Jones * @speed: is the percentage value (min - max) to be set.
300d9261648SLee Jones * Exception: Fails is the speed not lie between min and max.
301e098bc96SEvan Quan */
vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr * hwmgr,uint32_t speed)302e098bc96SEvan Quan int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed)
303e098bc96SEvan Quan {
304e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
305e098bc96SEvan Quan uint32_t tach_period;
306e098bc96SEvan Quan uint32_t crystal_clock_freq;
307e098bc96SEvan Quan int result = 0;
308e098bc96SEvan Quan
309e098bc96SEvan Quan if (hwmgr->thermal_controller.fanInfo.bNoFan ||
310e098bc96SEvan Quan speed == 0 ||
311e098bc96SEvan Quan (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) ||
312e098bc96SEvan Quan (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM))
313e098bc96SEvan Quan return -1;
314e098bc96SEvan Quan
315e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
316e098bc96SEvan Quan result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
317e098bc96SEvan Quan
318e098bc96SEvan Quan if (!result) {
319e098bc96SEvan Quan crystal_clock_freq = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
320e098bc96SEvan Quan tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
321e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
322e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
323e098bc96SEvan Quan CG_TACH_CTRL, TARGET_PERIOD,
324e098bc96SEvan Quan tach_period));
325e098bc96SEvan Quan }
326e098bc96SEvan Quan return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
327e098bc96SEvan Quan }
328e098bc96SEvan Quan
329e098bc96SEvan Quan /**
330d9261648SLee Jones * vega10_thermal_get_temperature - Reads the remote temperature from the SIslands thermal controller.
331e098bc96SEvan Quan *
332d9261648SLee Jones * @hwmgr: The address of the hardware manager.
333e098bc96SEvan Quan */
vega10_thermal_get_temperature(struct pp_hwmgr * hwmgr)334e098bc96SEvan Quan int vega10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
335e098bc96SEvan Quan {
336e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
337e098bc96SEvan Quan int temp;
338e098bc96SEvan Quan
339e098bc96SEvan Quan temp = RREG32_SOC15(THM, 0, mmCG_MULT_THERMAL_STATUS);
340e098bc96SEvan Quan
341e098bc96SEvan Quan temp = (temp & CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK) >>
342e098bc96SEvan Quan CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT;
343e098bc96SEvan Quan
344e098bc96SEvan Quan temp = temp & 0x1ff;
345e098bc96SEvan Quan
346e098bc96SEvan Quan temp *= PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
347e098bc96SEvan Quan
348e098bc96SEvan Quan return temp;
349e098bc96SEvan Quan }
350e098bc96SEvan Quan
351e098bc96SEvan Quan /**
352d9261648SLee Jones * vega10_thermal_set_temperature_range - Set the requested temperature range for high and low alert signals
353e098bc96SEvan Quan *
354d9261648SLee Jones * @hwmgr: The address of the hardware manager.
355d9261648SLee Jones * @range: Temperature range to be programmed for
356e098bc96SEvan Quan * high and low alert signals
357d9261648SLee Jones * Exception: PP_Result_BadInput if the input data is not valid.
358e098bc96SEvan Quan */
vega10_thermal_set_temperature_range(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * range)359e098bc96SEvan Quan static int vega10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr,
360e098bc96SEvan Quan struct PP_TemperatureRange *range)
361e098bc96SEvan Quan {
36273239232SEvan Quan struct phm_ppt_v2_information *pp_table_info =
36373239232SEvan Quan (struct phm_ppt_v2_information *)(hwmgr->pptable);
36473239232SEvan Quan struct phm_tdp_table *tdp_table = pp_table_info->tdp_table;
365e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
3661887544dSEvan Quan int low = VEGA10_THERMAL_MINIMUM_ALERT_TEMP;
3671887544dSEvan Quan int high = VEGA10_THERMAL_MAXIMUM_ALERT_TEMP;
368e098bc96SEvan Quan uint32_t val;
369e098bc96SEvan Quan
3701887544dSEvan Quan /* compare them in unit celsius degree */
3711887544dSEvan Quan if (low < range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)
3721887544dSEvan Quan low = range->min / PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
373e1b08ae5SEvan Quan
374e1b08ae5SEvan Quan /*
375e1b08ae5SEvan Quan * As a common sense, usSoftwareShutdownTemp should be bigger
376e1b08ae5SEvan Quan * than ThotspotLimit. For any invalid usSoftwareShutdownTemp,
377e1b08ae5SEvan Quan * we will just use the max possible setting VEGA10_THERMAL_MAXIMUM_ALERT_TEMP
378e1b08ae5SEvan Quan * to avoid false alarms.
379e1b08ae5SEvan Quan */
380e1b08ae5SEvan Quan if ((tdp_table->usSoftwareShutdownTemp >
381e1b08ae5SEvan Quan range->hotspot_crit_max / PP_TEMPERATURE_UNITS_PER_CENTIGRADES)) {
38273239232SEvan Quan if (high > tdp_table->usSoftwareShutdownTemp)
38373239232SEvan Quan high = tdp_table->usSoftwareShutdownTemp;
384e1b08ae5SEvan Quan }
385e098bc96SEvan Quan
386e098bc96SEvan Quan if (low > high)
387e098bc96SEvan Quan return -EINVAL;
388e098bc96SEvan Quan
389e098bc96SEvan Quan val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
390e098bc96SEvan Quan
391e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
392e098bc96SEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
3931887544dSEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, high);
3941887544dSEvan Quan val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, low);
395e098bc96SEvan Quan val &= (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK) &
396e098bc96SEvan Quan (~THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK) &
397e098bc96SEvan Quan (~THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK);
398e098bc96SEvan Quan
399e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
400e098bc96SEvan Quan
401e098bc96SEvan Quan return 0;
402e098bc96SEvan Quan }
403e098bc96SEvan Quan
404e098bc96SEvan Quan /**
405d9261648SLee Jones * vega10_thermal_initialize - Programs thermal controller one-time setting registers
406e098bc96SEvan Quan *
407d9261648SLee Jones * @hwmgr: The address of the hardware manager.
408e098bc96SEvan Quan */
vega10_thermal_initialize(struct pp_hwmgr * hwmgr)409e098bc96SEvan Quan static int vega10_thermal_initialize(struct pp_hwmgr *hwmgr)
410e098bc96SEvan Quan {
411e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
412e098bc96SEvan Quan
413e098bc96SEvan Quan if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
414e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_TACH_CTRL,
415e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL),
416e098bc96SEvan Quan CG_TACH_CTRL, EDGE_PER_REV,
417e098bc96SEvan Quan hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution - 1));
418e098bc96SEvan Quan }
419e098bc96SEvan Quan
420e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
421e098bc96SEvan Quan REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
422e098bc96SEvan Quan CG_FDO_CTRL2, TACH_PWM_RESP_RATE, 0x28));
423e098bc96SEvan Quan
424e098bc96SEvan Quan return 0;
425e098bc96SEvan Quan }
426e098bc96SEvan Quan
427e098bc96SEvan Quan /**
428d9261648SLee Jones * vega10_thermal_enable_alert - Enable thermal alerts on the RV770 thermal controller.
429e098bc96SEvan Quan *
430d9261648SLee Jones * @hwmgr: The address of the hardware manager.
431e098bc96SEvan Quan */
vega10_thermal_enable_alert(struct pp_hwmgr * hwmgr)432e098bc96SEvan Quan static int vega10_thermal_enable_alert(struct pp_hwmgr *hwmgr)
433e098bc96SEvan Quan {
434e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
435e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
436e098bc96SEvan Quan uint32_t val = 0;
437e098bc96SEvan Quan
438e098bc96SEvan Quan if (data->smu_features[GNLD_FW_CTF].supported) {
439e098bc96SEvan Quan if (data->smu_features[GNLD_FW_CTF].enabled)
440e098bc96SEvan Quan printk("[Thermal_EnableAlert] FW CTF Already Enabled!\n");
441e098bc96SEvan Quan
442e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
443e098bc96SEvan Quan true,
444e098bc96SEvan Quan data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
445e098bc96SEvan Quan "Attempt to Enable FW CTF feature Failed!",
446e098bc96SEvan Quan return -1);
447e098bc96SEvan Quan data->smu_features[GNLD_FW_CTF].enabled = true;
448e098bc96SEvan Quan }
449e098bc96SEvan Quan
450e098bc96SEvan Quan val |= (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
451e098bc96SEvan Quan val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
452e098bc96SEvan Quan val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
453e098bc96SEvan Quan
454e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
455e098bc96SEvan Quan
456e098bc96SEvan Quan return 0;
457e098bc96SEvan Quan }
458e098bc96SEvan Quan
459e098bc96SEvan Quan /**
460d9261648SLee Jones * vega10_thermal_disable_alert - Disable thermal alerts on the RV770 thermal controller.
461d9261648SLee Jones * @hwmgr: The address of the hardware manager.
462e098bc96SEvan Quan */
vega10_thermal_disable_alert(struct pp_hwmgr * hwmgr)463e098bc96SEvan Quan int vega10_thermal_disable_alert(struct pp_hwmgr *hwmgr)
464e098bc96SEvan Quan {
465e098bc96SEvan Quan struct amdgpu_device *adev = hwmgr->adev;
466e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
467e098bc96SEvan Quan
468e098bc96SEvan Quan if (data->smu_features[GNLD_FW_CTF].supported) {
469e098bc96SEvan Quan if (!data->smu_features[GNLD_FW_CTF].enabled)
470e098bc96SEvan Quan printk("[Thermal_EnableAlert] FW CTF Already disabled!\n");
471e098bc96SEvan Quan
472e098bc96SEvan Quan
473e098bc96SEvan Quan PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr,
474e098bc96SEvan Quan false,
475e098bc96SEvan Quan data->smu_features[GNLD_FW_CTF].smu_feature_bitmap),
476e098bc96SEvan Quan "Attempt to disable FW CTF feature Failed!",
477e098bc96SEvan Quan return -1);
478e098bc96SEvan Quan data->smu_features[GNLD_FW_CTF].enabled = false;
479e098bc96SEvan Quan }
480e098bc96SEvan Quan
481e098bc96SEvan Quan WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
482e098bc96SEvan Quan
483e098bc96SEvan Quan return 0;
484e098bc96SEvan Quan }
485e098bc96SEvan Quan
486e098bc96SEvan Quan /**
487d9261648SLee Jones * vega10_thermal_stop_thermal_controller - Uninitialize the thermal controller.
488e098bc96SEvan Quan * Currently just disables alerts.
489d9261648SLee Jones * @hwmgr: The address of the hardware manager.
490e098bc96SEvan Quan */
vega10_thermal_stop_thermal_controller(struct pp_hwmgr * hwmgr)491e098bc96SEvan Quan int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
492e098bc96SEvan Quan {
493e098bc96SEvan Quan int result = vega10_thermal_disable_alert(hwmgr);
494e098bc96SEvan Quan
495e098bc96SEvan Quan if (!hwmgr->thermal_controller.fanInfo.bNoFan)
496e098bc96SEvan Quan vega10_fan_ctrl_set_default_mode(hwmgr);
497e098bc96SEvan Quan
498e098bc96SEvan Quan return result;
499e098bc96SEvan Quan }
500e098bc96SEvan Quan
501e098bc96SEvan Quan /**
502d9261648SLee Jones * vega10_thermal_setup_fan_table - Set up the fan table to control the fan using the SMC.
503d9261648SLee Jones * @hwmgr: the address of the powerplay hardware manager.
504d9261648SLee Jones * Return: result from set temperature range routine
505e098bc96SEvan Quan */
vega10_thermal_setup_fan_table(struct pp_hwmgr * hwmgr)506e098bc96SEvan Quan static int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
507e098bc96SEvan Quan {
508e098bc96SEvan Quan int ret;
509e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
510e098bc96SEvan Quan PPTable_t *table = &(data->smc_state_table.pp_table);
511e098bc96SEvan Quan
512e098bc96SEvan Quan if (!data->smu_features[GNLD_FAN_CONTROL].supported)
513e098bc96SEvan Quan return 0;
514e098bc96SEvan Quan
515e098bc96SEvan Quan table->FanMaximumRpm = (uint16_t)hwmgr->thermal_controller.
516e098bc96SEvan Quan advanceFanControlParameters.usMaxFanRPM;
517e098bc96SEvan Quan table->FanThrottlingRpm = hwmgr->thermal_controller.
518e098bc96SEvan Quan advanceFanControlParameters.usFanRPMMaxLimit;
519e098bc96SEvan Quan table->FanAcousticLimitRpm = (uint16_t)(hwmgr->thermal_controller.
520e098bc96SEvan Quan advanceFanControlParameters.ulMinFanSCLKAcousticLimit);
521e098bc96SEvan Quan table->FanTargetTemperature = hwmgr->thermal_controller.
522e098bc96SEvan Quan advanceFanControlParameters.usTMax;
523e098bc96SEvan Quan
524e098bc96SEvan Quan smum_send_msg_to_smc_with_parameter(hwmgr,
525e098bc96SEvan Quan PPSMC_MSG_SetFanTemperatureTarget,
526e098bc96SEvan Quan (uint32_t)table->FanTargetTemperature,
527e098bc96SEvan Quan NULL);
528e098bc96SEvan Quan
529e098bc96SEvan Quan table->FanPwmMin = hwmgr->thermal_controller.
530e098bc96SEvan Quan advanceFanControlParameters.usPWMMin * 255 / 100;
531e098bc96SEvan Quan table->FanTargetGfxclk = (uint16_t)(hwmgr->thermal_controller.
532e098bc96SEvan Quan advanceFanControlParameters.ulTargetGfxClk);
533e098bc96SEvan Quan table->FanGainEdge = hwmgr->thermal_controller.
534e098bc96SEvan Quan advanceFanControlParameters.usFanGainEdge;
535e098bc96SEvan Quan table->FanGainHotspot = hwmgr->thermal_controller.
536e098bc96SEvan Quan advanceFanControlParameters.usFanGainHotspot;
537e098bc96SEvan Quan table->FanGainLiquid = hwmgr->thermal_controller.
538e098bc96SEvan Quan advanceFanControlParameters.usFanGainLiquid;
539e098bc96SEvan Quan table->FanGainVrVddc = hwmgr->thermal_controller.
540e098bc96SEvan Quan advanceFanControlParameters.usFanGainVrVddc;
541e098bc96SEvan Quan table->FanGainVrMvdd = hwmgr->thermal_controller.
542e098bc96SEvan Quan advanceFanControlParameters.usFanGainVrMvdd;
543e098bc96SEvan Quan table->FanGainPlx = hwmgr->thermal_controller.
544e098bc96SEvan Quan advanceFanControlParameters.usFanGainPlx;
545e098bc96SEvan Quan table->FanGainHbm = hwmgr->thermal_controller.
546e098bc96SEvan Quan advanceFanControlParameters.usFanGainHbm;
547e098bc96SEvan Quan table->FanZeroRpmEnable = hwmgr->thermal_controller.
548e098bc96SEvan Quan advanceFanControlParameters.ucEnableZeroRPM;
549e098bc96SEvan Quan table->FanStopTemp = hwmgr->thermal_controller.
550e098bc96SEvan Quan advanceFanControlParameters.usZeroRPMStopTemperature;
551e098bc96SEvan Quan table->FanStartTemp = hwmgr->thermal_controller.
552e098bc96SEvan Quan advanceFanControlParameters.usZeroRPMStartTemperature;
553e098bc96SEvan Quan
554e098bc96SEvan Quan ret = smum_smc_table_manager(hwmgr,
555e098bc96SEvan Quan (uint8_t *)(&(data->smc_state_table.pp_table)),
556e098bc96SEvan Quan PPTABLE, false);
557e098bc96SEvan Quan if (ret)
558e098bc96SEvan Quan pr_info("Failed to update Fan Control Table in PPTable!");
559e098bc96SEvan Quan
560e098bc96SEvan Quan return ret;
561e098bc96SEvan Quan }
562e098bc96SEvan Quan
vega10_enable_mgpu_fan_boost(struct pp_hwmgr * hwmgr)563e098bc96SEvan Quan int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
564e098bc96SEvan Quan {
565e098bc96SEvan Quan struct vega10_hwmgr *data = hwmgr->backend;
566e098bc96SEvan Quan PPTable_t *table = &(data->smc_state_table.pp_table);
567e098bc96SEvan Quan int ret;
568e098bc96SEvan Quan
569e098bc96SEvan Quan if (!data->smu_features[GNLD_FAN_CONTROL].supported)
570e098bc96SEvan Quan return 0;
571e098bc96SEvan Quan
572e098bc96SEvan Quan if (!hwmgr->thermal_controller.advanceFanControlParameters.
573e098bc96SEvan Quan usMGpuThrottlingRPMLimit)
574e098bc96SEvan Quan return 0;
575e098bc96SEvan Quan
576e098bc96SEvan Quan table->FanThrottlingRpm = hwmgr->thermal_controller.
577e098bc96SEvan Quan advanceFanControlParameters.usMGpuThrottlingRPMLimit;
578e098bc96SEvan Quan
579e098bc96SEvan Quan ret = smum_smc_table_manager(hwmgr,
580e098bc96SEvan Quan (uint8_t *)(&(data->smc_state_table.pp_table)),
581e098bc96SEvan Quan PPTABLE, false);
582e098bc96SEvan Quan if (ret) {
583e098bc96SEvan Quan pr_info("Failed to update fan control table in pptable!");
584e098bc96SEvan Quan return ret;
585e098bc96SEvan Quan }
586e098bc96SEvan Quan
587e098bc96SEvan Quan ret = vega10_disable_fan_control_feature(hwmgr);
588e098bc96SEvan Quan if (ret) {
589e098bc96SEvan Quan pr_info("Attempt to disable SMC fan control feature failed!");
590e098bc96SEvan Quan return ret;
591e098bc96SEvan Quan }
592e098bc96SEvan Quan
593e098bc96SEvan Quan ret = vega10_enable_fan_control_feature(hwmgr);
594e098bc96SEvan Quan if (ret)
595e098bc96SEvan Quan pr_info("Attempt to enable SMC fan control feature failed!");
596e098bc96SEvan Quan
597e098bc96SEvan Quan return ret;
598e098bc96SEvan Quan }
599e098bc96SEvan Quan
600e098bc96SEvan Quan /**
601d9261648SLee Jones * vega10_thermal_start_smc_fan_control - Start the fan control on the SMC.
602d9261648SLee Jones * @hwmgr: the address of the powerplay hardware manager.
603d9261648SLee Jones * Return: result from set temperature range routine
604e098bc96SEvan Quan */
vega10_thermal_start_smc_fan_control(struct pp_hwmgr * hwmgr)605e098bc96SEvan Quan static int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
606e098bc96SEvan Quan {
607e098bc96SEvan Quan /* If the fantable setup has failed we could have disabled
608e098bc96SEvan Quan * PHM_PlatformCaps_MicrocodeFanControl even after
609e098bc96SEvan Quan * this function was included in the table.
610e098bc96SEvan Quan * Make sure that we still think controlling the fan is OK.
611e098bc96SEvan Quan */
612e098bc96SEvan Quan if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
613e098bc96SEvan Quan vega10_fan_ctrl_start_smc_fan_control(hwmgr);
614e098bc96SEvan Quan
615e098bc96SEvan Quan return 0;
616e098bc96SEvan Quan }
617e098bc96SEvan Quan
618e098bc96SEvan Quan
vega10_start_thermal_controller(struct pp_hwmgr * hwmgr,struct PP_TemperatureRange * range)619e098bc96SEvan Quan int vega10_start_thermal_controller(struct pp_hwmgr *hwmgr,
620e098bc96SEvan Quan struct PP_TemperatureRange *range)
621e098bc96SEvan Quan {
622e098bc96SEvan Quan int ret = 0;
623e098bc96SEvan Quan
624e098bc96SEvan Quan if (range == NULL)
625e098bc96SEvan Quan return -EINVAL;
626e098bc96SEvan Quan
627e098bc96SEvan Quan vega10_thermal_initialize(hwmgr);
628e098bc96SEvan Quan ret = vega10_thermal_set_temperature_range(hwmgr, range);
629e098bc96SEvan Quan if (ret)
630e098bc96SEvan Quan return -EINVAL;
631e098bc96SEvan Quan
632e098bc96SEvan Quan vega10_thermal_enable_alert(hwmgr);
633e098bc96SEvan Quan /* We should restrict performance levels to low before we halt the SMC.
634e098bc96SEvan Quan * On the other hand we are still in boot state when we do this
635e098bc96SEvan Quan * so it would be pointless.
636e098bc96SEvan Quan * If this assumption changes we have to revisit this table.
637e098bc96SEvan Quan */
638e098bc96SEvan Quan ret = vega10_thermal_setup_fan_table(hwmgr);
639e098bc96SEvan Quan if (ret)
640e098bc96SEvan Quan return -EINVAL;
641e098bc96SEvan Quan
642e098bc96SEvan Quan vega10_thermal_start_smc_fan_control(hwmgr);
643e098bc96SEvan Quan
644e098bc96SEvan Quan return 0;
645e098bc96SEvan Quan };
646e098bc96SEvan Quan
647e098bc96SEvan Quan
648e098bc96SEvan Quan
649e098bc96SEvan Quan
vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr * hwmgr)650e098bc96SEvan Quan int vega10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr)
651e098bc96SEvan Quan {
652e098bc96SEvan Quan if (!hwmgr->thermal_controller.fanInfo.bNoFan) {
653e098bc96SEvan Quan vega10_fan_ctrl_set_default_mode(hwmgr);
654e098bc96SEvan Quan vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
655e098bc96SEvan Quan }
656e098bc96SEvan Quan return 0;
657e098bc96SEvan Quan }
658