xref: /openbmc/u-boot/drivers/clk/mpc83xx_clk.h (revision 9dc8d155)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * (C) Copyright 2018
4  * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
5  */
6 
7 /**
8  * enum ratio - Description of a core clock ratio
9  * @RAT_UNK:      Unknown ratio
10  * @RAT_BYP:      Bypass
11  * @RAT_1_TO_8:   Ratio 1:8
12  * @RAT_1_TO_4:   Ratio 1:4
13  * @RAT_1_TO_2:   Ratio 1:2
14  * @RAT_1_TO_1:   Ratio 1:1
15  * @RAT_1_5_TO_1: Ratio 1.5:1
16  * @RAT_2_TO_1:   Ratio 2:1
17  * @RAT_2_5_TO_1: Ratio 2.5:1
18  * @RAT_3_TO_1:   Ratio 3:1
19  */
20 enum ratio {
21 	RAT_UNK,
22 	RAT_BYP,
23 	RAT_1_TO_8,
24 	RAT_1_TO_4,
25 	RAT_1_TO_2,
26 	RAT_1_TO_1,
27 	RAT_1_5_TO_1,
28 	RAT_2_TO_1,
29 	RAT_2_5_TO_1,
30 	RAT_3_TO_1
31 };
32 
33 /**
34  * struct corecnf - Description for a core clock configuration
35  * @core_csb_ratio: Core clock frequency to CSB clock frequency ratio
36  * @vco_divider: VCO divider (Core VCO frequency = Core frequency * VCO divider)
37  */
38 struct corecnf {
39 	int core_csb_ratio;
40 	int vco_divider;
41 };
42 
43 /*
44  * Table with all valid Core CSB frequency ratio / VCO divider combinations as
45  * indexed by the COREPLL field of the SPMR
46  */
47 static const struct corecnf corecnf_tab[] = {
48 	{RAT_BYP, RAT_BYP},			/* 0x00 */
49 	{RAT_BYP, RAT_BYP},			/* 0x01 */
50 	{RAT_BYP, RAT_BYP},			/* 0x02 */
51 	{RAT_BYP, RAT_BYP},			/* 0x03 */
52 	{RAT_BYP, RAT_BYP},			/* 0x04 */
53 	{RAT_BYP, RAT_BYP},			/* 0x05 */
54 	{RAT_BYP, RAT_BYP},			/* 0x06 */
55 	{RAT_BYP, RAT_BYP},			/* 0x07 */
56 	{RAT_1_TO_1, RAT_1_TO_2},		/* 0x08 */
57 	{RAT_1_TO_1, RAT_1_TO_4},		/* 0x09 */
58 	{RAT_1_TO_1, RAT_1_TO_8},		/* 0x0A */
59 	{RAT_1_TO_1, RAT_1_TO_8},		/* 0x0B */
60 	{RAT_1_5_TO_1, RAT_1_TO_2},		/* 0x0C */
61 	{RAT_1_5_TO_1, RAT_1_TO_4},		/* 0x0D */
62 	{RAT_1_5_TO_1, RAT_1_TO_8},		/* 0x0E */
63 	{RAT_1_5_TO_1, RAT_1_TO_8},		/* 0x0F */
64 	{RAT_2_TO_1, RAT_1_TO_2},		/* 0x10 */
65 	{RAT_2_TO_1, RAT_1_TO_4},		/* 0x11 */
66 	{RAT_2_TO_1, RAT_1_TO_8},		/* 0x12 */
67 	{RAT_2_TO_1, RAT_1_TO_8},		/* 0x13 */
68 	{RAT_2_5_TO_1, RAT_1_TO_2},		/* 0x14 */
69 	{RAT_2_5_TO_1, RAT_1_TO_4},		/* 0x15 */
70 	{RAT_2_5_TO_1, RAT_1_TO_8},		/* 0x16 */
71 	{RAT_2_5_TO_1, RAT_1_TO_8},		/* 0x17 */
72 	{RAT_3_TO_1, RAT_1_TO_2},		/* 0x18 */
73 	{RAT_3_TO_1, RAT_1_TO_4},		/* 0x19 */
74 	{RAT_3_TO_1, RAT_1_TO_8},		/* 0x1A */
75 	{RAT_3_TO_1, RAT_1_TO_8},		/* 0x1B */
76 };
77 
78 /**
79  * enum reg_type - Register to read a field from
80  * @REG_SCCR: Use the SCCR register
81  * @REG_SPMR: Use the SPMR register
82  */
83 enum reg_type {
84 	REG_SCCR,
85 	REG_SPMR,
86 };
87 
88 /**
89  * enum mode_type - Description of how to read a specific frequency value
90  * @TYPE_INVALID: Unknown type, will provoke error
91  * @TYPE_SCCR_STANDARD:        Read a field from the SCCR register, and use it
92  *			       as a divider for the CSB clock to compute the
93  *			       frequency
94  * @TYPE_SCCR_ONOFF:           The field describes a bit flag that can turn the
95  *			       clock on or off
96  * @TYPE_SPMR_DIRECT_MULTIPLY: Read a field from the SPMR register, and use it
97  *			       as a multiplier for the CSB clock to compute the
98  *			       frequency
99  * @TYPE_SPECIAL:              The frequency is calculated in a non-standard way
100  */
101 enum mode_type {
102 	TYPE_INVALID = 0,
103 	TYPE_SCCR_STANDARD,
104 	TYPE_SCCR_ONOFF,
105 	TYPE_SPMR_DIRECT_MULTIPLY,
106 	TYPE_SPECIAL,
107 };
108 
109 /* Map of each clock index to its human-readable name */
110 static const char * const names[] = {
111 	[MPC83XX_CLK_CORE] = "Core",
112 	[MPC83XX_CLK_CSB] = "Coherent System Bus",
113 	[MPC83XX_CLK_QE] = "QE",
114 	[MPC83XX_CLK_BRG] = "BRG",
115 	[MPC83XX_CLK_LBIU] = "Local Bus Controller",
116 	[MPC83XX_CLK_LCLK] = "Local Bus",
117 	[MPC83XX_CLK_MEM] = "DDR",
118 	[MPC83XX_CLK_MEM_SEC] = "DDR Secondary",
119 	[MPC83XX_CLK_ENC] = "SEC",
120 	[MPC83XX_CLK_I2C1] = "I2C1",
121 	[MPC83XX_CLK_I2C2] = "I2C2",
122 	[MPC83XX_CLK_TDM] = "TDM",
123 	[MPC83XX_CLK_SDHC] = "SDHC",
124 	[MPC83XX_CLK_TSEC1] = "TSEC1",
125 	[MPC83XX_CLK_TSEC2] = "TSEC2",
126 	[MPC83XX_CLK_USBDR] = "USB DR",
127 	[MPC83XX_CLK_USBMPH] = "USB MPH",
128 	[MPC83XX_CLK_PCIEXP1] = "PCIEXP1",
129 	[MPC83XX_CLK_PCIEXP2] = "PCIEXP2",
130 	[MPC83XX_CLK_SATA] = "SATA",
131 	[MPC83XX_CLK_DMAC] = "DMAC",
132 	[MPC83XX_CLK_PCI] = "PCI",
133 };
134 
135 /**
136  * struct clk_mode - Structure for clock mode descriiptions
137  * @low:  The low bit of the data field to read for this mode (may not apply to
138  *	  some modes)
139  * @high: The high bit of the data field to read for this mode (may not apply to
140  *	  some modes)
141  * @type: The type of the mode description (one of enum mode_type)
142  */
143 struct clk_mode {
144 	u8 low;
145 	u8 high;
146 	int type;
147 };
148 
149 /**
150  * set_mode() - Build a clock mode description from data
151  * @mode: The clock mode description to be filled out
152  * @low:  The low bit of the data field to read for this mode (may not apply to
153  *	  some modes)
154  * @high: The high bit of the data field to read for this mode (may not apply to
155  *	  some modes)
156  * @type: The type of the mode description (one of enum mode_type)
157  *
158  * Clock mode descriptions are a succinct description of how to read a specific
159  * clock's rate from the hardware; usually by reading a specific field of a
160  * register, such a s the SCCR register, but some types use different methods
161  * for obtaining the clock rate.
162  */
set_mode(struct clk_mode * mode,u8 low,u8 high,int type)163 static void set_mode(struct clk_mode *mode, u8 low, u8 high, int type)
164 {
165 	mode->low = low;
166 	mode->high = high;
167 	mode->type = type;
168 }
169 
170 /**
171  * retrieve_mode() - Get the clock mode description for a specific clock
172  * @clk:      The identifier of the clock for which the clock description should
173  *	      be retrieved
174  * @soc_type: The type of MPC83xx SoC for which the clock description should be
175  *	      retrieved
176  * @mode:     Pointer to a clk_mode structure to be filled with data for the
177  *	      clock
178  *
179  * Since some clock rate are stored in different places on different MPC83xx
180  * SoCs, the SoC type has to be supplied along with the clock's identifier.
181  *
182  * Return: 0 if OK, -ve on error
183  */
retrieve_mode(int clk,int soc_type,struct clk_mode * mode)184 static int retrieve_mode(int clk, int soc_type, struct clk_mode *mode)
185 {
186 	switch (clk) {
187 	case MPC83XX_CLK_CORE:
188 	case MPC83XX_CLK_CSB:
189 	case MPC83XX_CLK_QE:
190 	case MPC83XX_CLK_BRG:
191 	case MPC83XX_CLK_LCLK:
192 	case MPC83XX_CLK_I2C2:
193 		set_mode(mode, 0, 0, TYPE_SPECIAL);
194 		break;
195 	case MPC83XX_CLK_MEM:
196 		set_mode(mode, 1, 1, TYPE_SPMR_DIRECT_MULTIPLY);
197 		break;
198 	case MPC83XX_CLK_LBIU:
199 	case MPC83XX_CLK_MEM_SEC:
200 		set_mode(mode, 0, 0, TYPE_SPMR_DIRECT_MULTIPLY);
201 		break;
202 	case MPC83XX_CLK_TSEC1:
203 		set_mode(mode, 0, 1, TYPE_SCCR_STANDARD);
204 		break;
205 	case MPC83XX_CLK_TSEC2:
206 		if (soc_type == SOC_MPC8313) /* I2C and TSEC2 are the same register */
207 			set_mode(mode, 2, 3, TYPE_SCCR_STANDARD);
208 		else /* FIXME(mario.six@gdsys.cc): This has separate enable/disable bit! */
209 			set_mode(mode, 0, 1, TYPE_SCCR_STANDARD);
210 		break;
211 	case MPC83XX_CLK_SDHC:
212 		set_mode(mode, 4, 5, TYPE_SCCR_STANDARD);
213 		break;
214 	case MPC83XX_CLK_ENC:
215 		set_mode(mode, 6, 7, TYPE_SCCR_STANDARD);
216 		break;
217 	case MPC83XX_CLK_I2C1:
218 		if (soc_type == SOC_MPC8349)
219 			set_mode(mode, 2, 3, TYPE_SCCR_STANDARD);
220 		else /* I2C and ENC are the same register */
221 			set_mode(mode, 6, 7, TYPE_SCCR_STANDARD);
222 		break;
223 	case MPC83XX_CLK_PCIEXP1:
224 		set_mode(mode, 10, 11, TYPE_SCCR_STANDARD);
225 		break;
226 	case MPC83XX_CLK_PCIEXP2:
227 		set_mode(mode, 12, 13, TYPE_SCCR_STANDARD);
228 		break;
229 	case MPC83XX_CLK_USBDR:
230 		if (soc_type == SOC_MPC8313 || soc_type == SOC_MPC8349)
231 			set_mode(mode, 10, 11, TYPE_SCCR_STANDARD);
232 		else
233 			set_mode(mode, 8, 9, TYPE_SCCR_STANDARD);
234 		break;
235 	case MPC83XX_CLK_USBMPH:
236 		set_mode(mode, 8, 9, TYPE_SCCR_STANDARD);
237 		break;
238 	case MPC83XX_CLK_PCI:
239 		set_mode(mode, 15, 15, TYPE_SCCR_ONOFF);
240 		break;
241 	case MPC83XX_CLK_DMAC:
242 		set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
243 		break;
244 	case MPC83XX_CLK_SATA:
245 		/* FIXME(mario.six@gdsys.cc): All SATA controllers must have the same clock ratio */
246 		if (soc_type == SOC_MPC8379) {
247 			set_mode(mode, 24, 25, TYPE_SCCR_STANDARD);
248 			set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
249 			set_mode(mode, 28, 29, TYPE_SCCR_STANDARD);
250 			set_mode(mode, 30, 31, TYPE_SCCR_STANDARD);
251 		} else {
252 			set_mode(mode, 18, 19, TYPE_SCCR_STANDARD);
253 			set_mode(mode, 20, 21, TYPE_SCCR_STANDARD);
254 		}
255 		break;
256 	case MPC83XX_CLK_TDM:
257 		set_mode(mode, 26, 27, TYPE_SCCR_STANDARD);
258 		break;
259 	default:
260 		debug("%s: Unknown clock type %d on soc type %d\n",
261 		      __func__, clk, soc_type);
262 		set_mode(mode, 0, 0, TYPE_INVALID);
263 		return -EINVAL;
264 	}
265 
266 	return 0;
267 }
268 
269 /**
270  * get_spmr() - Read the SPMR (System PLL Mode Register)
271  * @im: Pointer to the MPC83xx main register map in question
272  *
273  * Return: The SPMR value as a 32-bit number.
274  */
get_spmr(immap_t * im)275 static inline u32 get_spmr(immap_t *im)
276 {
277 	u32 res = in_be32(&im->clk.spmr);
278 
279 	return res;
280 }
281 
282 /**
283  * get_sccr() - Read the SCCR (System Clock Control Register)
284  * @im: Pointer to the MPC83xx main register map in question
285  *
286  * Return: The SCCR value as a 32-bit number.
287  */
get_sccr(immap_t * im)288 static inline u32 get_sccr(immap_t *im)
289 {
290 	u32 res = in_be32(&im->clk.sccr);
291 
292 	return res;
293 }
294 
295 /**
296  * get_lcrr() - Read the LCRR (Clock Ratio Register)
297  * @im: Pointer to the MPC83xx main register map in question
298  *
299  * Return: The LCRR value as a 32-bit number.
300  */
get_lcrr(immap_t * im)301 static inline u32 get_lcrr(immap_t *im)
302 {
303 	u32 res = in_be32(&im->im_lbc.lcrr);
304 
305 	return res;
306 }
307 
308 /**
309  * get_pci_sync_in() - Read the PCI synchronization clock speed
310  * @im: Pointer to the MPC83xx main register map in question
311  *
312  * Return: The PCI synchronization clock speed value as a 32-bit number.
313  */
get_pci_sync_in(immap_t * im)314 static inline u32 get_pci_sync_in(immap_t *im)
315 {
316 	u8 clkin_div;
317 
318 	clkin_div = (get_spmr(im) & SPMR_CKID) >> SPMR_CKID_SHIFT;
319 	return CONFIG_SYS_CLK_FREQ / (1 + clkin_div);
320 }
321 
322 /**
323  * get_csb_clk() - Read the CSB (Coheren System Bus) clock speed
324  * @im: Pointer to the MPC83xx main register map in question
325  *
326  * Return: The CSB clock speed value as a 32-bit number.
327  */
get_csb_clk(immap_t * im)328 static inline u32 get_csb_clk(immap_t *im)
329 {
330 	u8 spmf;
331 
332 	spmf = (get_spmr(im) & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
333 	return CONFIG_SYS_CLK_FREQ * spmf;
334 }
335 
336 /**
337  * spmr_field() - Read a specific SPMR field
338  * @im:   Pointer to the MPC83xx main register map in question
339  * @mask: A bitmask that describes the bitfield to be read
340  *
341  * Return: The value of the bit field as a 32-bit number.
342  */
spmr_field(immap_t * im,u32 mask)343 static inline uint spmr_field(immap_t *im, u32 mask)
344 {
345 	/* Extract shift from bitmask */
346 	uint shift = mask ? ffs(mask) - 1 : 0;
347 
348 	return (get_spmr(im) & mask) >> shift;
349 }
350 
351 /**
352  * sccr_field() - Read a specific SCCR field
353  * @im:   Pointer to the MPC83xx main register map in question
354  * @mask: A bitmask that describes the bitfield to be read
355  *
356  * Return: The value of the bit field as a 32-bit number.
357  */
sccr_field(immap_t * im,u32 mask)358 static inline uint sccr_field(immap_t *im, u32 mask)
359 {
360 	/* Extract shift from bitmask */
361 	uint shift = mask ? ffs(mask) - 1 : 0;
362 
363 	return (get_sccr(im) & mask) >> shift;
364 }
365 
366 /**
367  * lcrr_field() - Read a specific LCRR field
368  * @im:   Pointer to the MPC83xx main register map in question
369  * @mask: A bitmask that describes the bitfield to be read
370  *
371  * Return: The value of the bit field as a 32-bit number.
372  */
lcrr_field(immap_t * im,u32 mask)373 static inline uint lcrr_field(immap_t *im, u32 mask)
374 {
375 	/* Extract shift from bitmask */
376 	uint shift = mask ? ffs(mask) - 1 : 0;
377 
378 	return (get_lcrr(im) & mask) >> shift;
379 }
380