Home
last modified time | relevance | path

Searched +full:hdmi +full:- +full:dp2 (Results 1 – 21 of 21) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/arm/tegra/
H A Dnvidia,tegra186-pmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra186-pmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - nvidia,tegra186-pmc
17 - nvidia,tegra194-pmc
18 - nvidia,tegra234-pmc
24 reg-names:
[all …]
/openbmc/linux/sound/soc/intel/boards/
H A Dskl_nau88l25_max98357a.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <sound/soc-acpi.h>
20 #define SKL_NUVOTON_CODEC_DAI "nau8825-hifi"
22 #define DMIC_CH(p) p->list[p->count-1]
52 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
53 struct snd_soc_card *card = dapm->card; in platform_clock_control()
59 dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n"); in platform_clock_control()
60 return -EIO; in platform_clock_control()
67 dev_err(card->dev, "set sysclk err = %d\n", ret); in platform_clock_control()
68 return -EIO; in platform_clock_control()
[all …]
H A Dskl_nau88l25_ssm4567.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <sound/soc-acpi.h>
24 #define SKL_NUVOTON_CODEC_DAI "nau8825-hifi"
25 #define SKL_SSM_CODEC_DAI "ssm4567-hifi"
26 #define DMIC_CH(p) p->list[p->count-1]
62 struct snd_soc_dapm_context *dapm = w->dapm; in platform_clock_control()
63 struct snd_soc_card *card = dapm->card; in platform_clock_control()
69 dev_err(card->dev, "Codec dai not found\n"); in platform_clock_control()
70 return -EIO; in platform_clock_control()
77 dev_err(card->dev, "set sysclk err = %d\n", ret); in platform_clock_control()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_dpms.c31 * TODO - The reason link owns stream's dpms programming sequence is
80 for (i = 0; i < dc->link_count; i++) { in link_blank_all_dp_displays()
81 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_DISPLAY_PORT) || in link_blank_all_dp_displays()
82 (dc->links[i]->priv == NULL) || (dc->links[i]->local_sink == NULL)) in link_blank_all_dp_displays()
86 dp_retrieve_lttpr_cap(dc->links[i]); in link_blank_all_dp_displays()
88 status = core_link_read_dpcd(dc->links[i], DP_SET_POWER, in link_blank_all_dp_displays()
92 link_blank_dp_stream(dc->links[i], true); in link_blank_all_dp_displays()
103 for (i = 0; i < dc->link_count; i++) { in link_blank_all_edp_displays()
104 if ((dc->links[i]->connector_signal != SIGNAL_TYPE_EDP) || in link_blank_all_edp_displays()
105 (!dc->links[i]->edp_sink_present)) in link_blank_all_edp_displays()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_capability.c55 link->ctx->logger
108 return (link->dpcd_caps.dongle_type >= DISPLAY_DONGLE_DP_VGA_CONVERTER) && in is_dp_active_dongle()
109 (link->dpcd_caps.dongle_type <= DISPLAY_DONGLE_DP_HDMI_CONVERTER); in is_dp_active_dongle()
114 return link->dpcd_caps.is_branch_dev; in is_dp_branch_device()
132 return -1; in translate_dpcd_max_bpc()
186 link_rate = LINK_RATE_LOW; // Rate_1 (RBR) - 1.62 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
189 link_rate = LINK_RATE_RATE_2; // Rate_2 - 2.16 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
192 link_rate = LINK_RATE_RATE_3; // Rate_3 - 2.43 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
195 link_rate = LINK_RATE_HIGH; // Rate_4 (HBR) - 2.70 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
198 link_rate = LINK_RATE_RBR2; // Rate_5 (RBR2)- 3.24 Gbps/Lane in linkRateInKHzToLinkRateMultiplier()
[all …]
/openbmc/linux/drivers/gpu/drm/i915/display/
H A Dintel_cx0_phy.c1 // SPDX-License-Identifier: MIT
55 drm_WARN_ON(&i915->drm, !enabled); in assert_dc_off()
66 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_begin()
75 struct drm_i915_private *i915 = to_i915(encoder->base.dev); in intel_cx0_phy_transaction_end()
99 drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy)); in intel_cx0_bus_reset()
117 drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n", in intel_cx0_wait_for_ack()
120 return -ETIMEDOUT; in intel_cx0_wait_for_ack()
124 drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy), in intel_cx0_wait_for_ack()
127 return -EINVAL; in intel_cx0_wait_for_ack()
131 drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy), in intel_cx0_wait_for_ack()
[all …]
H A Dintel_ddi.c96 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
98 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
121 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
124 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers()
127 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
128 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
133 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers()
138 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers()
140 trans->entries[i].hsw.trans2); in hsw_prepare_dp_ddi_buffers()
147 * HDMI/DVI use cases.
[all …]
H A Dintel_dp.c107 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH)
119 return dig_port->base.type == INTEL_OUTPUT_EDP; in intel_dp_is_edp()
127 return crtc_state->port_clock >= 1000000; in intel_dp_is_uhbr()
132 intel_dp->sink_rates[0] = 162000; in intel_dp_set_default_sink_rates()
133 intel_dp->num_sink_rates = 1; in intel_dp_set_default_sink_rates()
145 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { in intel_dp_set_dpcd_sink_rates()
149 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); in intel_dp_set_dpcd_sink_rates()
150 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); in intel_dp_set_dpcd_sink_rates()
158 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); in intel_dp_set_dpcd_sink_rates()
159 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); in intel_dp_set_dpcd_sink_rates()
[all …]
H A Dintel_ddi_buf_trans.c1 // SPDX-License-Identifier: MIT
14 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
16 * automatically adapt to HDMI connections as well
399 /* BSpec has 2 recommended values - entries 0 and 8.
419 .hdmi_default_entry = ARRAY_SIZE(_bxt_trans_hdmi) - 1,
475 .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_trans_hdmi) - 1,
593 /* Voltage swing pre-emphasis */
612 /* Voltage swing pre-emphasis */
631 /* HDMI Preset VS Pre-emph */
637 { .mg = { 0x3A, 0x0, 0x5 } }, /* 6 Full -1.5 dB */
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_link_encoder.c2 * Copyright 2012-15 Advanced Micro Devices, Inc.
37 enc10->base.ctx
39 enc10->base.ctx->logger
42 (enc10->link_regs->reg)
46 enc10->link_shift->field_name, enc10->link_mask->field_name
49 (enc10->link_regs->index)
177 enable ? "Enabling" : "Disabling", enc->id.enum_id); in enc2_fec_set_enable()
205 REG_GET(DP_DPHY_CNTL, DPHY_FEC_EN, &s->dphy_fec_en); in link_enc2_read_state()
206 REG_GET(DP_DPHY_CNTL, DPHY_FEC_READY_SHADOW, &s->dphy_fec_ready_shadow); in link_enc2_read_state()
207 REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); in link_enc2_read_state()
[all …]
/openbmc/linux/sound/pci/hda/
H A Dpatch_hdmi.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * patch_hdmi.c - routines for HDMI/DisplayPort codecs
6 * Copyright(c) 2008-2010 Intel Corporation. All rights reserved.
48 MODULE_PARM_DESC(enable_silent_stream, "Enable Silent Stream for HDMI devices");
82 struct hdmi_pcm *pcm; /* pointer to spec->pcm_rec[n] dynamically*/
83 int pcm_idx; /* which pcm is attached. -1 means no pcm is attached */
90 bool chmap_set; /* channel-map override by ALSA API? */
91 unsigned char chmap[8]; /* ALSA API channel-map */
127 SILENT_STREAM_KAE, /* use standard HDA Keep-Alive */
172 /* hdmi interrupt trigger control flag for Nvidia codec */
[all …]
/openbmc/linux/drivers/soc/tegra/
H A Dpmc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
58 #include <dt-bindings/gpio/tegra186-gpio.h>
[all …]
/openbmc/linux/drivers/gpu/drm/amd/include/
H A Datomfirmware.h6 * Description header file of general definitions for OS and pre-OS video drivers
31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the chan…
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
202 #define BIOS_VERSION_PREFIX "ATOMBIOSBK-AMD"
245 …tom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
604 uint32_t maco_pwrlimit_mw; // bomaco mode power limit in unit of m-watt
605 uint32_t usb_pwrlimit_mw; // power limit when USB is enable in unit of m-watt
656 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
657 …eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without A…
[all …]
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
107 #define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
108 #define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
110 #define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV,…
222 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
245 UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
427 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
433 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
440 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
538 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
[all …]
/openbmc/linux/drivers/gpu/drm/radeon/
H A Datombios.h2 * Copyright 2006-2007 Advanced Micro Devices, Inc.
214 UCHAR uaFirmWareSignature[4]; /*Signature to distinguish between Atombios and non-atombios,
397 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
403 …ONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_…
410 …ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Di…
504 …UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0)…
536 #define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
544 …bDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
549 … //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
707 // =3: HDMI encoder
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_hw_sequencer.c73 * For eDP, after power-up/power/down,
83 hws->ctx
88 hws->regs->reg
92 hws->shifts->field_name, hws->masks->field_name
100 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
103 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
106 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
109 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
209 struct dc_context *ctx = dc->ctx; in dce110_enable_display_power_gating()
210 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; in dce110_enable_display_power_gating()
[all …]
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
16 #include "clk-id.h"
130 #define MASK(x) (BIT(x) - 1)
714 MUX8("hdmi", mux_pllp_pllm_plld_plla_pllc_plld2_clkm, CLK_SOURCE_HDMI, 51, 0, tegra_clk_hdmi),
787 GATE("mipi-cal", "clk72mhz", 56, 0, tegra_clk_mipi_cal, 0),
795 GATE("dp2", "clk_m", 152, TEGRA_PERIPH_ON_APB, tegra_clk_dp2, 0),
873 dt_clk = tegra_lookup_dt_id(data->clk_id, tegra_clks); in periph_clk_init()
877 bank = get_reg_bank(data->periph.gate.clk_num); in periph_clk_init()
881 data->periph.gate.regs = bank; in periph_clk_init()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_debugfs.c64 /* parse_write_buffer_into_params - Helper function to parse debugfs write buffer into an array
91 return -EFAULT; in parse_write_buffer_into_params()
105 /* skip non-space*/ in parse_write_buffer_into_params()
154 * debugfs is located at /sys/kernel/debug/dri/0/DP-x/link_settings
156 * --- to get dp configuration
158 * cat /sys/kernel/debug/dri/0/DP-x/link_settings
161 * current -- for current video mode
162 * verified --- maximum configuration which pass link training
163 * reported --- DP rx report caps (DPCD register offset 0, 1 2)
164 * preferred --- user force settings
[all …]
H A Damdgpu_dm.c167 switch (link->dpcd_caps.dongle_type) { in get_subconnector_type()
186 struct dc_link *link = aconnector->dc_link; in update_subconnector_property()
187 struct drm_connector *connector = &aconnector->base; in update_subconnector_property()
190 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) in update_subconnector_property()
193 if (aconnector->dc_sink) in update_subconnector_property()
196 drm_object_property_set_value(&connector->base, in update_subconnector_property()
197 connector->dev->mode_config.dp_subconnector_property, in update_subconnector_property()
240 * struct amdgpu_device *adev - [in] desired amdgpu device
241 * int disp_idx - [in] which CRTC to get the counter from
250 if (crtc >= adev->mode_info.num_crtc) in dm_vblank_get_counter()
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dmub/inc/
H A Ddmub_cmd.h141 * Physical framebuffer address location, 64-bit.
243 * @knee_threshold: Current x-position of ACE knee (u0.16).
263 * union dmub_addr - DMUB physical/virtual 64-bit address.
488 * struct dmub_fw_meta_info - metadata associated with fw binary
510 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
523 * dmub_trace_code_t - firmware trace code, 32-bits
528 * struct dmcub_trace_buf_entry - Firmware trace entry
551 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
564 uint32_t all; /**< 32-bit access to status bits */
568 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
[all …]
/openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_hwseq.c57 hws->ctx
59 hws->regs->reg
61 dc->ctx->logger
66 hws->shifts->field_name, hws->masks->field_name
77 if (hws->ctx->dc->debug.disable_dsc_power_gate) in dcn32_dsc_pg_control()
80 if (!hws->ctx->dc->debug.enable_double_buffered_dsc_pg_support) in dcn32_dsc_pg_control()
165 if (hws->ctx->dc->debug.disable_hubp_power_gate) in dcn32_hubp_pg_control()
198 /* First, check no-memory-request case */ in dcn32_check_no_memory_request_for_cab()
199 for (i = 0; i < dc->current_state->stream_count; i++) { in dcn32_check_no_memory_request_for_cab()
200 if ((dc->current_state->stream_status[i].plane_count) && in dcn32_check_no_memory_request_for_cab()
[all …]