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/openbmc/linux/drivers/ufs/core/
H A Dufshcd-crypto.c1 // SPDX-License-Identifier: GPL-2.0
7 #include "ufshcd-crypto.h"
9 /* Blk-crypto modes supported by UFS crypto */
20 static int ufshcd_program_key(struct ufs_hba *hba, in ufshcd_program_key() argument
24 u32 slot_offset = hba->crypto_cfg_register + slot * sizeof(*cfg); in ufshcd_program_key()
27 ufshcd_hold(hba); in ufshcd_program_key()
29 if (hba->vops && hba->vops->program_key) { in ufshcd_program_key()
30 err = hba->vops->program_key(hba, cfg, slot); in ufshcd_program_key()
35 ufshcd_writel(hba, 0, slot_offset + 16 * sizeof(cfg->reg_val[0])); in ufshcd_program_key()
37 ufshcd_writel(hba, le32_to_cpu(cfg->reg_val[i]), in ufshcd_program_key()
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H A Dufshcd.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved.
17 #include <linux/blk-pm.h>
30 #include "ufshcd-priv.h"
33 #include "ufs-sysfs.h"
34 #include "ufs-debugfs.h"
35 #include "ufs-fault-injection.h"
37 #include "ufshcd-crypto.h"
74 /* maximum number of link-startup retries */
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/openbmc/linux/Documentation/devicetree/bindings/ata/
H A Dahci-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
24 - $ref: sata-common.yaml#
32 reg-names:
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H A Dahci-platform.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
13 It is possible, but not required, to represent each port as a sub-node.
18 - Hans de Goede <hdegoede@redhat.com>
19 - Jens Axboe <axboe@kernel.dk>
26 - brcm,iproc-ahci
27 - cavium,octeon-7130-ahci
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H A Dsnps,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
26 - $ref: snps,dwc-ahci-common.yaml#
31 - description: Synopsys AHCI SATA-compatible devices
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H A Drockchip,dwc-ahci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Serge Semin <fancer.lancer@gmail.com>
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
25 - compatible
30 - enum:
31 - rockchip,rk3568-dwc-ahci
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/openbmc/linux/drivers/ufs/host/
H A Dufs-qcom.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2013-2016, Linux Foundation. All rights reserved.
16 #include <linux/reset-controller.h>
22 #include "ufshcd-pltfrm.h"
24 #include "ufs-qcom.h"
102 static int ufs_qcom_set_dme_vs_core_clk_ctrl_clear_div(struct ufs_hba *hba,
114 if (host->hba->caps & UFSHCD_CAP_CRYPTO) in ufs_qcom_ice_enable()
115 qcom_ice_enable(host->ice); in ufs_qcom_ice_enable()
120 struct ufs_hba *hba = host->hba; in ufs_qcom_ice_init() local
121 struct device *dev = hba->dev; in ufs_qcom_ice_init()
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H A Dufs-hisi.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2016-2017 Linaro Ltd.
6 * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
14 #include <linux/dma-mapping.h>
19 #include "ufshcd-pltfrm.h"
21 #include "ufs-hisi.h"
25 static int ufs_hisi_check_hibern8(struct ufs_hba *hba) in ufs_hisi_check_hibern8() argument
33 err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), in ufs_hisi_check_hibern8()
35 err |= ufshcd_dme_get(hba, in ufs_hisi_check_hibern8()
50 err = ufshcd_dme_get(hba, UIC_ARG_MIB_SEL(MPHY_TX_FSM_STATE, 0), in ufs_hisi_check_hibern8()
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/openbmc/qemu/hw/ide/
H A Dahci.c28 #include "hw/qdev-properties.h"
31 #include "qemu/error-report.h"
33 #include "qemu/main-loop.h"
35 #include "sysemu/block-backend.h"
38 #include "hw/ide/ahci-pci.h"
39 #include "hw/ide/ahci-sysbus.h"
40 #include "ahci-internal.h"
41 #include "ide-internal.h"
58 [AHCI_HOST_REG_CAP] = "CAP",
120 AHCIPortRegs *pr = &s->dev[port].port_regs; in ahci_port_read()
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H A Dich.c21 * lspci dump of a ICH-9 real device
23 …2801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-if 01 [AHCI 1.0])
25 …* Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- Fast…
26 …* Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR…
34 * Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
35 * Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
38 * Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
39 * Status: D0 PME-Enable- DSel=0 DScale=0 PME-
40 * Capabilities: [a8] SATA HBA <?>
72 #include "hw/ide/ahci-pci.h"
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H A Dahci-internal.h29 #include "ide-internal.h"
60 AHCI_HOST_REG_CAP = 0, /* CAP: host capabilities */
75 #define HOST_CTL_RESET (1 << 0) /* reset controller; self-clear */
83 #define HOST_CAP_SSS (1 << 27) /* Staggered Spin-up */
85 #define HOST_CAP_64 (1U << 31) /* PCI DAC (64-bit DMA) support */
146 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
187 /* ap->flags bits */
315 struct AHCIState *hba; member
339 * but some fields have been re-mapped and re-purposed, as seen in
347 * bytes 16-19 become an le32 "auxiliary" field.
/openbmc/qemu/tests/qtest/
H A Dahci-test.c29 #include "libqos/libqos-pc.h"
31 #include "libqos/pci-pc.h"
34 #include "qemu/host-utils.h"
72 while (bytes--) { in string_bswap16()
88 ahci_fingerprint = qpci_config_readl(ahci->dev, PCI_VENDOR_ID); in verify_state()
89 g_assert_cmphex(ahci_fingerprint, ==, ahci->fingerprint); in verify_state()
92 if (!ahci->enabled) { in verify_state()
96 hba_base = (uint64_t)qpci_config_readl(ahci->dev, PCI_BASE_ADDRESS_5); in verify_state()
99 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP), ==, ahci->cap); in verify_state()
100 g_assert_cmphex(ahci_rreg(ahci, AHCI_CAP2), ==, ahci->cap2); in verify_state()
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/openbmc/linux/drivers/s390/scsi/
H A Dzfcp_dbf.c1 // SPDX-License-Identifier: GPL-2.0
36 return sizeof(struct zfcp_dbf_pay) + offset - ZFCP_DBF_PAY_MAX_REC; in zfcp_dbf_plen()
43 struct zfcp_dbf_pay *pl = &dbf->pay_buf; in zfcp_dbf_pl_write()
46 spin_lock(&dbf->pay_lock); in zfcp_dbf_pl_write()
48 pl->fsf_req_id = req_id; in zfcp_dbf_pl_write()
49 memcpy(pl->area, area, ZFCP_DBF_TAG_LEN); in zfcp_dbf_pl_write()
53 (u16) (length - offset)); in zfcp_dbf_pl_write()
54 memcpy(pl->data, data + offset, rec_length); in zfcp_dbf_pl_write()
55 debug_event(dbf->pay, 1, pl, zfcp_dbf_plen(rec_length)); in zfcp_dbf_pl_write()
58 pl->counter++; in zfcp_dbf_pl_write()
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/openbmc/linux/drivers/ata/
H A Dlibahci_platform.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2004-2005 Red Hat, Inc.
37 * ahci_platform_enable_phys - Enable PHYs
40 * This function enables all the PHYs found in hpriv->phys, if any.
51 for (i = 0; i < hpriv->nports; i++) { in ahci_platform_enable_phys()
52 rc = phy_init(hpriv->phys[i]); in ahci_platform_enable_phys()
56 rc = phy_set_mode(hpriv->phys[i], PHY_MODE_SATA); in ahci_platform_enable_phys()
58 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
62 rc = phy_power_on(hpriv->phys[i]); in ahci_platform_enable_phys()
64 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
[all …]
H A Dlibahci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * libahci.c - Common AHCI SATA low-level routines
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
27 #include <linux/dma-mapping.h>
236 * ahci_rpm_get_port - Make sure the port is powered on
245 return pm_runtime_get_sync(ap->dev); in ahci_rpm_get_port()
249 * ahci_rpm_put_port - Undoes ahci_rpm_get_port()
257 pm_runtime_put(ap->dev); in ahci_rpm_put_port()
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H A Dacard-ahci.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * acard-ahci.c - ACard AHCI SATA support
7 * Please ALWAYS copy linux-ide@vger.kernel.org
13 * as Documentation/driver-api/libata.rst
26 #include <linux/dma-mapping.h>
35 #define DRV_NAME "acard-ahci"
70 AHCI_SHT("acard-ahci"),
115 struct ahci_host_priv *hpriv = host->private_data; in acard_ahci_pci_device_suspend()
116 void __iomem *mmio = hpriv->mmio; in acard_ahci_pci_device_suspend()
120 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) { in acard_ahci_pci_device_suspend()
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H A Dahci_dwc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
25 #define DRV_NAME "ahci-dwc"
95 /* Baikal-T1 AHCI SATA specific registers */
127 struct ahci_dwc_host_priv *dpriv = hpriv->plat_data; in ahci_bt1_init()
134 dev_err(&dpriv->pdev->dev, "No system clocks specified\n"); in ahci_bt1_init()
135 return -EINVAL; in ahci_bt1_init()
145 dev_err(&dpriv->pdev->dev, "Couldn't assert the resets\n"); in ahci_bt1_init()
151 dev_err(&dpriv->pdev->dev, "Couldn't de-assert the resets\n"); in ahci_bt1_init()
163 dpriv = devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL); in ahci_dwc_get_resources()
165 return ERR_PTR(-ENOMEM); in ahci_dwc_get_resources()
[all …]
H A Dsata_highbank.c1 // SPDX-License-Identifier: GPL-2.0-only
53 /* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
91 return 1 << (3 * pdata->port_to_sgpio[port] + shift); in sgpio_bit_shift()
97 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
100 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
103 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
106 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
109 pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
112 pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port, in ecx_parse_sgpio()
122 gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 1); in ecx_led_cycle_clock()
[all …]
/openbmc/linux/include/scsi/
H A Dscsi_host.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 #include <linux/blk-mq.h>
31 * enum scsi_timeout_action - How to handle a command that timed out.
49 * Additional per-command data allocated for the driver.
59 * command. It must also push it to the HBA if the scsi_cmnd
77 * For compatibility, any other non-zero return is treated the
123 * When unknown ioctl is passed return -ENOIOCTLCMD.
136 * define one of these if you don't want to - there is a default
139 * own strategy routine, this is where it is specified. Note - the
168 * Return values: 0 on success, non-0 on failure
[all …]
/openbmc/linux/drivers/char/agp/
H A Dparisc-agp.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (c) 2006, Kyle McMartin <kyle@parisc-linux.org>
7 * Based on drivers/char/agpgart/hp-agp.c which is
8 * (c) Copyright 2002, 2003 Hewlett-Packard Development Company, L.P.
20 #include <asm/parisc-device.h>
71 agp_bridge->current_size = (void *) &parisc_agp_sizes[0]; in parisc_agp_fetch_size()
81 agp_bridge->gart_bus_addr = info->gart_base; in parisc_agp_configure()
82 agp_bridge->capndx = info->lba_cap_offset; in parisc_agp_configure()
83 agp_bridge->mode = readl(info->lba_regs+info->lba_cap_offset+PCI_AGP_STATUS); in parisc_agp_configure()
96 writeq(info->gart_base | ilog2(info->gart_size), info->ioc_regs+IOC_PCOM); in parisc_agp_tlbflush()
[all …]
/openbmc/u-boot/arch/x86/cpu/ivybridge/
H A Dsata.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2008-2009 coresystems GmbH
41 const void *blob = gd->fdt_blob; in bd82x6x_sata_init()
50 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); in bd82x6x_sata_init()
54 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); in bd82x6x_sata_init()
73 /* Initialize AHCI memory-mapped space */ in bd82x6x_sata_init()
76 /* CAP (HBA Capabilities) : enable power management */ in bd82x6x_sata_init()
90 /* CAP2 (HBA Capabilities Extended)*/ in bd82x6x_sata_init()
123 debug("SATA: Controller in plain-ide mode\n"); in bd82x6x_sata_init()
155 port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0); in bd82x6x_sata_init()
[all …]
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dsata.c1 // SPDX-License-Identifier: GPL-2.0
57 reg16 |= 0x8000 | plat->port_map; in broadwell_sata_init()
75 reg32 |= (plat->port_map ^ 0xf) << 24; in broadwell_sata_init()
76 reg32 |= (plat->devslp_mux & 1) << 15; in broadwell_sata_init()
79 /* Initialize AHCI memory-mapped space */ in broadwell_sata_init()
84 /* CAP (HBA Capabilities) : enable power management */ in broadwell_sata_init()
90 writel(plat->port_map, abar + 0x0c); in broadwell_sata_init()
94 /* CAP2 (HBA Capabilities Extended)*/ in broadwell_sata_init()
95 if (plat->devslp_disable) { in broadwell_sata_init()
102 if (!(plat->port_map & (1 << port))) in broadwell_sata_init()
[all …]
/openbmc/u-boot/drivers/ata/
H A Ddwc_ahsata.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
49 u32 cap; member
99 return (i < timeout_msec) ? 0 : -1; in waiting_for_cmd_completed()
104 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in ahci_setup_oobr()
106 writel(SATA_HOST_OOBR_WE, &host_mmio->oobr); in ahci_setup_oobr()
107 writel(0x02060b14, &host_mmio->oobr); in ahci_setup_oobr()
117 struct sata_host_regs *host_mmio = uc_priv->mmio_base; in ahci_host_init()
120 cap_save = readl(&host_mmio->cap); in ahci_host_init()
124 tmp = readl(&host_mmio->ghc); in ahci_host_init()
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/openbmc/qemu/tests/qtest/libqos/
H A Dahci.c29 #include "pci-pc.h"
31 #include "qemu/host-utils.h"
107 g_assert(ahci->parent); in ahci_alloc()
108 return qmalloc(ahci->parent, bytes); in ahci_alloc()
114 g_assert(ahci->parent); in ahci_free()
115 qfree(ahci->parent, addr); in ahci_free()
156 QPCIBus *pcibus = dev ? dev->bus : NULL; in free_ahci_device()
163 /* Free all memory in-use by the AHCI device. */
169 if (ahci->port[port].fb) { in ahci_clean_mem()
170 ahci_free(ahci, ahci->port[port].fb); in ahci_clean_mem()
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H A Dahci.h30 #include "malloc-pc.h"
44 /*** AHCI/HBA Register Offsets and Bitmasks ***/
320 #define ATA_DEVICE_MAGIC 0xA0 /* used in ata1-3 */
342 uint32_t cap; member
358 * Register device-to-host FIS structure.
380 * Register device-to-host FIS structure;
405 * Register host-to-device FIS structure.
428 * Register host-to-device FIS structure, for NCQ commands.
455 * The command list contains between 1-32 of these structures.
458 uint16_t flags; /* Cmd-Fis-Len, PMP#, and flags. */
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