1*83d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+
2f2105c61SSimon Glass /*
3f2105c61SSimon Glass * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
4f2105c61SSimon Glass * Terry Lv <r65388@freescale.com>
5f2105c61SSimon Glass */
6f2105c61SSimon Glass
70f07df43SSimon Glass #include <common.h>
8f2105c61SSimon Glass #include <ahci.h>
9c893f1e6SSimon Glass #include <dm.h>
10c893f1e6SSimon Glass #include <dwc_ahsata.h>
11f2105c61SSimon Glass #include <fis.h>
120f07df43SSimon Glass #include <libata.h>
13f2105c61SSimon Glass #include <malloc.h>
14752126a0SSimon Glass #include <memalign.h>
150f07df43SSimon Glass #include <sata.h>
16f2105c61SSimon Glass #include <asm/io.h>
17f2105c61SSimon Glass #include <asm/arch/clock.h>
18f2105c61SSimon Glass #include <asm/arch/sys_proto.h>
190f07df43SSimon Glass #include <linux/bitops.h>
200f07df43SSimon Glass #include <linux/ctype.h>
210f07df43SSimon Glass #include <linux/errno.h>
2290abb28fSSimon Glass #include "dwc_ahsata_priv.h"
23f2105c61SSimon Glass
24f2105c61SSimon Glass struct sata_port_regs {
25f2105c61SSimon Glass u32 clb;
26f2105c61SSimon Glass u32 clbu;
27f2105c61SSimon Glass u32 fb;
28f2105c61SSimon Glass u32 fbu;
29f2105c61SSimon Glass u32 is;
30f2105c61SSimon Glass u32 ie;
31f2105c61SSimon Glass u32 cmd;
32f2105c61SSimon Glass u32 res1[1];
33f2105c61SSimon Glass u32 tfd;
34f2105c61SSimon Glass u32 sig;
35f2105c61SSimon Glass u32 ssts;
36f2105c61SSimon Glass u32 sctl;
37f2105c61SSimon Glass u32 serr;
38f2105c61SSimon Glass u32 sact;
39f2105c61SSimon Glass u32 ci;
40f2105c61SSimon Glass u32 sntf;
41f2105c61SSimon Glass u32 res2[1];
42f2105c61SSimon Glass u32 dmacr;
43f2105c61SSimon Glass u32 res3[1];
44f2105c61SSimon Glass u32 phycr;
45f2105c61SSimon Glass u32 physr;
46f2105c61SSimon Glass };
47f2105c61SSimon Glass
48f2105c61SSimon Glass struct sata_host_regs {
49f2105c61SSimon Glass u32 cap;
50f2105c61SSimon Glass u32 ghc;
51f2105c61SSimon Glass u32 is;
52f2105c61SSimon Glass u32 pi;
53f2105c61SSimon Glass u32 vs;
54f2105c61SSimon Glass u32 ccc_ctl;
55f2105c61SSimon Glass u32 ccc_ports;
56f2105c61SSimon Glass u32 res1[2];
57f2105c61SSimon Glass u32 cap2;
58f2105c61SSimon Glass u32 res2[30];
59f2105c61SSimon Glass u32 bistafr;
60f2105c61SSimon Glass u32 bistcr;
61f2105c61SSimon Glass u32 bistfctr;
62f2105c61SSimon Glass u32 bistsr;
63f2105c61SSimon Glass u32 bistdecr;
64f2105c61SSimon Glass u32 res3[2];
65f2105c61SSimon Glass u32 oobr;
66f2105c61SSimon Glass u32 res4[8];
67f2105c61SSimon Glass u32 timer1ms;
68f2105c61SSimon Glass u32 res5[1];
69f2105c61SSimon Glass u32 gparam1r;
70f2105c61SSimon Glass u32 gparam2r;
71f2105c61SSimon Glass u32 pparamr;
72f2105c61SSimon Glass u32 testr;
73f2105c61SSimon Glass u32 versionr;
74f2105c61SSimon Glass u32 idr;
75f2105c61SSimon Glass };
76f2105c61SSimon Glass
77f2105c61SSimon Glass #define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
78f2105c61SSimon Glass #define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
79f2105c61SSimon Glass
80f2105c61SSimon Glass #define writel_with_flush(a, b) do { writel(a, b); readl(b); } while (0)
81f2105c61SSimon Glass
ahci_port_base(void __iomem * base,u32 port)82f2105c61SSimon Glass static inline void __iomem *ahci_port_base(void __iomem *base, u32 port)
83f2105c61SSimon Glass {
84f2105c61SSimon Glass return base + 0x100 + (port * 0x80);
85f2105c61SSimon Glass }
86f2105c61SSimon Glass
waiting_for_cmd_completed(u8 * offset,int timeout_msec,u32 sign)87f2105c61SSimon Glass static int waiting_for_cmd_completed(u8 *offset,
88f2105c61SSimon Glass int timeout_msec,
89f2105c61SSimon Glass u32 sign)
90f2105c61SSimon Glass {
91f2105c61SSimon Glass int i;
92f2105c61SSimon Glass u32 status;
93f2105c61SSimon Glass
94f2105c61SSimon Glass for (i = 0;
95f2105c61SSimon Glass ((status = readl(offset)) & sign) && i < timeout_msec;
96f2105c61SSimon Glass ++i)
97f2105c61SSimon Glass mdelay(1);
98f2105c61SSimon Glass
99f2105c61SSimon Glass return (i < timeout_msec) ? 0 : -1;
100f2105c61SSimon Glass }
101f2105c61SSimon Glass
ahci_setup_oobr(struct ahci_uc_priv * uc_priv,int clk)10209bb951bSSimon Glass static int ahci_setup_oobr(struct ahci_uc_priv *uc_priv, int clk)
103f2105c61SSimon Glass {
1044b640dbcSSimon Glass struct sata_host_regs *host_mmio = uc_priv->mmio_base;
105f2105c61SSimon Glass
1063e59c30fSSimon Glass writel(SATA_HOST_OOBR_WE, &host_mmio->oobr);
1073e59c30fSSimon Glass writel(0x02060b14, &host_mmio->oobr);
108f2105c61SSimon Glass
109f2105c61SSimon Glass return 0;
110f2105c61SSimon Glass }
111f2105c61SSimon Glass
ahci_host_init(struct ahci_uc_priv * uc_priv)11209bb951bSSimon Glass static int ahci_host_init(struct ahci_uc_priv *uc_priv)
113f2105c61SSimon Glass {
114f2105c61SSimon Glass u32 tmp, cap_save, num_ports;
115f2105c61SSimon Glass int i, j, timeout = 1000;
116f2105c61SSimon Glass struct sata_port_regs *port_mmio = NULL;
1174b640dbcSSimon Glass struct sata_host_regs *host_mmio = uc_priv->mmio_base;
118f2105c61SSimon Glass int clk = mxc_get_clock(MXC_SATA_CLK);
119f2105c61SSimon Glass
1203e59c30fSSimon Glass cap_save = readl(&host_mmio->cap);
121f2105c61SSimon Glass cap_save |= SATA_HOST_CAP_SSS;
122f2105c61SSimon Glass
123f2105c61SSimon Glass /* global controller reset */
1243e59c30fSSimon Glass tmp = readl(&host_mmio->ghc);
125f2105c61SSimon Glass if ((tmp & SATA_HOST_GHC_HR) == 0)
1263e59c30fSSimon Glass writel_with_flush(tmp | SATA_HOST_GHC_HR, &host_mmio->ghc);
127f2105c61SSimon Glass
1283e59c30fSSimon Glass while ((readl(&host_mmio->ghc) & SATA_HOST_GHC_HR) && --timeout)
129f2105c61SSimon Glass ;
130f2105c61SSimon Glass
131f2105c61SSimon Glass if (timeout <= 0) {
132f2105c61SSimon Glass debug("controller reset failed (0x%x)\n", tmp);
133f2105c61SSimon Glass return -1;
134f2105c61SSimon Glass }
135f2105c61SSimon Glass
136f2105c61SSimon Glass /* Set timer 1ms */
1373e59c30fSSimon Glass writel(clk / 1000, &host_mmio->timer1ms);
138f2105c61SSimon Glass
13909bb951bSSimon Glass ahci_setup_oobr(uc_priv, 0);
140f2105c61SSimon Glass
1413e59c30fSSimon Glass writel_with_flush(SATA_HOST_GHC_AE, &host_mmio->ghc);
1423e59c30fSSimon Glass writel(cap_save, &host_mmio->cap);
143f2105c61SSimon Glass num_ports = (cap_save & SATA_HOST_CAP_NP_MASK) + 1;
1443e59c30fSSimon Glass writel_with_flush((1 << num_ports) - 1, &host_mmio->pi);
145f2105c61SSimon Glass
146f2105c61SSimon Glass /*
147f2105c61SSimon Glass * Determine which Ports are implemented by the DWC_ahsata,
148f2105c61SSimon Glass * by reading the PI register. This bit map value aids the
149f2105c61SSimon Glass * software to determine how many Ports are available and
150f2105c61SSimon Glass * which Port registers need to be initialized.
151f2105c61SSimon Glass */
1523e59c30fSSimon Glass uc_priv->cap = readl(&host_mmio->cap);
1533e59c30fSSimon Glass uc_priv->port_map = readl(&host_mmio->pi);
154f2105c61SSimon Glass
155f2105c61SSimon Glass /* Determine how many command slots the HBA supports */
15609bb951bSSimon Glass uc_priv->n_ports = (uc_priv->cap & SATA_HOST_CAP_NP_MASK) + 1;
157f2105c61SSimon Glass
158f2105c61SSimon Glass debug("cap 0x%x port_map 0x%x n_ports %d\n",
15909bb951bSSimon Glass uc_priv->cap, uc_priv->port_map, uc_priv->n_ports);
160f2105c61SSimon Glass
16109bb951bSSimon Glass for (i = 0; i < uc_priv->n_ports; i++) {
16209bb951bSSimon Glass uc_priv->port[i].port_mmio = ahci_port_base(host_mmio, i);
1634b640dbcSSimon Glass port_mmio = uc_priv->port[i].port_mmio;
164f2105c61SSimon Glass
165f2105c61SSimon Glass /* Ensure that the DWC_ahsata is in idle state */
1663e59c30fSSimon Glass tmp = readl(&port_mmio->cmd);
167f2105c61SSimon Glass
168f2105c61SSimon Glass /*
169f2105c61SSimon Glass * When P#CMD.ST, P#CMD.CR, P#CMD.FRE and P#CMD.FR
170f2105c61SSimon Glass * are all cleared, the Port is in an idle state.
171f2105c61SSimon Glass */
172f2105c61SSimon Glass if (tmp & (SATA_PORT_CMD_CR | SATA_PORT_CMD_FR |
173f2105c61SSimon Glass SATA_PORT_CMD_FRE | SATA_PORT_CMD_ST)) {
174f2105c61SSimon Glass
175f2105c61SSimon Glass /*
176f2105c61SSimon Glass * System software places a Port into the idle state by
177f2105c61SSimon Glass * clearing P#CMD.ST and waiting for P#CMD.CR to return
178f2105c61SSimon Glass * 0 when read.
179f2105c61SSimon Glass */
180f2105c61SSimon Glass tmp &= ~SATA_PORT_CMD_ST;
1813e59c30fSSimon Glass writel_with_flush(tmp, &port_mmio->cmd);
182f2105c61SSimon Glass
183f2105c61SSimon Glass /*
184f2105c61SSimon Glass * spec says 500 msecs for each bit, so
185f2105c61SSimon Glass * this is slightly incorrect.
186f2105c61SSimon Glass */
187f2105c61SSimon Glass mdelay(500);
188f2105c61SSimon Glass
189f2105c61SSimon Glass timeout = 1000;
1903e59c30fSSimon Glass while ((readl(&port_mmio->cmd) & SATA_PORT_CMD_CR)
191f2105c61SSimon Glass && --timeout)
192f2105c61SSimon Glass ;
193f2105c61SSimon Glass
194f2105c61SSimon Glass if (timeout <= 0) {
195f2105c61SSimon Glass debug("port reset failed (0x%x)\n", tmp);
196f2105c61SSimon Glass return -1;
197f2105c61SSimon Glass }
198f2105c61SSimon Glass }
199f2105c61SSimon Glass
200f2105c61SSimon Glass /* Spin-up device */
2013e59c30fSSimon Glass tmp = readl(&port_mmio->cmd);
2023e59c30fSSimon Glass writel((tmp | SATA_PORT_CMD_SUD), &port_mmio->cmd);
203f2105c61SSimon Glass
204f2105c61SSimon Glass /* Wait for spin-up to finish */
205f2105c61SSimon Glass timeout = 1000;
2063e59c30fSSimon Glass while (!(readl(&port_mmio->cmd) | SATA_PORT_CMD_SUD)
207f2105c61SSimon Glass && --timeout)
208f2105c61SSimon Glass ;
209f2105c61SSimon Glass if (timeout <= 0) {
210f2105c61SSimon Glass debug("Spin-Up can't finish!\n");
211f2105c61SSimon Glass return -1;
212f2105c61SSimon Glass }
213f2105c61SSimon Glass
214f2105c61SSimon Glass for (j = 0; j < 100; ++j) {
215f2105c61SSimon Glass mdelay(10);
2163e59c30fSSimon Glass tmp = readl(&port_mmio->ssts);
217f2105c61SSimon Glass if (((tmp & SATA_PORT_SSTS_DET_MASK) == 0x3) ||
218f2105c61SSimon Glass ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x1))
219f2105c61SSimon Glass break;
220f2105c61SSimon Glass }
221f2105c61SSimon Glass
222f2105c61SSimon Glass /* Wait for COMINIT bit 26 (DIAG_X) in SERR */
223f2105c61SSimon Glass timeout = 1000;
2243e59c30fSSimon Glass while (!(readl(&port_mmio->serr) | SATA_PORT_SERR_DIAG_X)
225f2105c61SSimon Glass && --timeout)
226f2105c61SSimon Glass ;
227f2105c61SSimon Glass if (timeout <= 0) {
228f2105c61SSimon Glass debug("Can't find DIAG_X set!\n");
229f2105c61SSimon Glass return -1;
230f2105c61SSimon Glass }
231f2105c61SSimon Glass
232f2105c61SSimon Glass /*
233f2105c61SSimon Glass * For each implemented Port, clear the P#SERR
234f2105c61SSimon Glass * register, by writing ones to each implemented\
235f2105c61SSimon Glass * bit location.
236f2105c61SSimon Glass */
2373e59c30fSSimon Glass tmp = readl(&port_mmio->serr);
238f2105c61SSimon Glass debug("P#SERR 0x%x\n",
239f2105c61SSimon Glass tmp);
2403e59c30fSSimon Glass writel(tmp, &port_mmio->serr);
241f2105c61SSimon Glass
242f2105c61SSimon Glass /* Ack any pending irq events for this port */
2433e59c30fSSimon Glass tmp = readl(&host_mmio->is);
244f2105c61SSimon Glass debug("IS 0x%x\n", tmp);
245f2105c61SSimon Glass if (tmp)
2463e59c30fSSimon Glass writel(tmp, &host_mmio->is);
247f2105c61SSimon Glass
2483e59c30fSSimon Glass writel(1 << i, &host_mmio->is);
249f2105c61SSimon Glass
250f2105c61SSimon Glass /* set irq mask (enables interrupts) */
2513e59c30fSSimon Glass writel(DEF_PORT_IRQ, &port_mmio->ie);
252f2105c61SSimon Glass
253f2105c61SSimon Glass /* register linkup ports */
2543e59c30fSSimon Glass tmp = readl(&port_mmio->ssts);
255f2105c61SSimon Glass debug("Port %d status: 0x%x\n", i, tmp);
256f2105c61SSimon Glass if ((tmp & SATA_PORT_SSTS_DET_MASK) == 0x03)
25709bb951bSSimon Glass uc_priv->link_port_map |= (0x01 << i);
258f2105c61SSimon Glass }
259f2105c61SSimon Glass
2603e59c30fSSimon Glass tmp = readl(&host_mmio->ghc);
261f2105c61SSimon Glass debug("GHC 0x%x\n", tmp);
2623e59c30fSSimon Glass writel(tmp | SATA_HOST_GHC_IE, &host_mmio->ghc);
2633e59c30fSSimon Glass tmp = readl(&host_mmio->ghc);
264f2105c61SSimon Glass debug("GHC 0x%x\n", tmp);
265f2105c61SSimon Glass
266f2105c61SSimon Glass return 0;
267f2105c61SSimon Glass }
268f2105c61SSimon Glass
ahci_print_info(struct ahci_uc_priv * uc_priv)26909bb951bSSimon Glass static void ahci_print_info(struct ahci_uc_priv *uc_priv)
270f2105c61SSimon Glass {
2714b640dbcSSimon Glass struct sata_host_regs *host_mmio = uc_priv->mmio_base;
272f2105c61SSimon Glass u32 vers, cap, impl, speed;
273f2105c61SSimon Glass const char *speed_s;
274f2105c61SSimon Glass const char *scc_s;
275f2105c61SSimon Glass
2763e59c30fSSimon Glass vers = readl(&host_mmio->vs);
27709bb951bSSimon Glass cap = uc_priv->cap;
27809bb951bSSimon Glass impl = uc_priv->port_map;
279f2105c61SSimon Glass
280f2105c61SSimon Glass speed = (cap & SATA_HOST_CAP_ISS_MASK)
281f2105c61SSimon Glass >> SATA_HOST_CAP_ISS_OFFSET;
282f2105c61SSimon Glass if (speed == 1)
283f2105c61SSimon Glass speed_s = "1.5";
284f2105c61SSimon Glass else if (speed == 2)
285f2105c61SSimon Glass speed_s = "3";
286f2105c61SSimon Glass else
287f2105c61SSimon Glass speed_s = "?";
288f2105c61SSimon Glass
289f2105c61SSimon Glass scc_s = "SATA";
290f2105c61SSimon Glass
291f2105c61SSimon Glass printf("AHCI %02x%02x.%02x%02x "
292f2105c61SSimon Glass "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
293f2105c61SSimon Glass (vers >> 24) & 0xff,
294f2105c61SSimon Glass (vers >> 16) & 0xff,
295f2105c61SSimon Glass (vers >> 8) & 0xff,
296f2105c61SSimon Glass vers & 0xff,
297f2105c61SSimon Glass ((cap >> 8) & 0x1f) + 1,
298f2105c61SSimon Glass (cap & 0x1f) + 1,
299f2105c61SSimon Glass speed_s,
300f2105c61SSimon Glass impl,
301f2105c61SSimon Glass scc_s);
302f2105c61SSimon Glass
303f2105c61SSimon Glass printf("flags: "
304f2105c61SSimon Glass "%s%s%s%s%s%s"
305f2105c61SSimon Glass "%s%s%s%s%s%s%s\n",
306f2105c61SSimon Glass cap & (1 << 31) ? "64bit " : "",
307f2105c61SSimon Glass cap & (1 << 30) ? "ncq " : "",
308f2105c61SSimon Glass cap & (1 << 28) ? "ilck " : "",
309f2105c61SSimon Glass cap & (1 << 27) ? "stag " : "",
310f2105c61SSimon Glass cap & (1 << 26) ? "pm " : "",
311f2105c61SSimon Glass cap & (1 << 25) ? "led " : "",
312f2105c61SSimon Glass cap & (1 << 24) ? "clo " : "",
313f2105c61SSimon Glass cap & (1 << 19) ? "nz " : "",
314f2105c61SSimon Glass cap & (1 << 18) ? "only " : "",
315f2105c61SSimon Glass cap & (1 << 17) ? "pmp " : "",
316f2105c61SSimon Glass cap & (1 << 15) ? "pio " : "",
317f2105c61SSimon Glass cap & (1 << 14) ? "slum " : "",
318f2105c61SSimon Glass cap & (1 << 13) ? "part " : "");
319f2105c61SSimon Glass }
320f2105c61SSimon Glass
ahci_fill_sg(struct ahci_uc_priv * uc_priv,u8 port,unsigned char * buf,int buf_len)32109bb951bSSimon Glass static int ahci_fill_sg(struct ahci_uc_priv *uc_priv, u8 port,
32209bb951bSSimon Glass unsigned char *buf, int buf_len)
323f2105c61SSimon Glass {
3243e59c30fSSimon Glass struct ahci_ioports *pp = &uc_priv->port[port];
325f2105c61SSimon Glass struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
326f2105c61SSimon Glass u32 sg_count, max_bytes;
327f2105c61SSimon Glass int i;
328f2105c61SSimon Glass
329f2105c61SSimon Glass max_bytes = MAX_DATA_BYTES_PER_SG;
330f2105c61SSimon Glass sg_count = ((buf_len - 1) / max_bytes) + 1;
331f2105c61SSimon Glass if (sg_count > AHCI_MAX_SG) {
332f2105c61SSimon Glass printf("Error:Too much sg!\n");
333f2105c61SSimon Glass return -1;
334f2105c61SSimon Glass }
335f2105c61SSimon Glass
336f2105c61SSimon Glass for (i = 0; i < sg_count; i++) {
337f2105c61SSimon Glass ahci_sg->addr =
338f2105c61SSimon Glass cpu_to_le32((u32)buf + i * max_bytes);
339f2105c61SSimon Glass ahci_sg->addr_hi = 0;
340f2105c61SSimon Glass ahci_sg->flags_size = cpu_to_le32(0x3fffff &
341f2105c61SSimon Glass (buf_len < max_bytes
342f2105c61SSimon Glass ? (buf_len - 1)
343f2105c61SSimon Glass : (max_bytes - 1)));
344f2105c61SSimon Glass ahci_sg++;
345f2105c61SSimon Glass buf_len -= max_bytes;
346f2105c61SSimon Glass }
347f2105c61SSimon Glass
348f2105c61SSimon Glass return sg_count;
349f2105c61SSimon Glass }
350f2105c61SSimon Glass
ahci_fill_cmd_slot(struct ahci_ioports * pp,u32 cmd_slot,u32 opts)351f2105c61SSimon Glass static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 cmd_slot, u32 opts)
352f2105c61SSimon Glass {
353f2105c61SSimon Glass struct ahci_cmd_hdr *cmd_hdr = (struct ahci_cmd_hdr *)(pp->cmd_slot +
354f2105c61SSimon Glass AHCI_CMD_SLOT_SZ * cmd_slot);
355f2105c61SSimon Glass
356f2105c61SSimon Glass memset(cmd_hdr, 0, AHCI_CMD_SLOT_SZ);
357f2105c61SSimon Glass cmd_hdr->opts = cpu_to_le32(opts);
358f2105c61SSimon Glass cmd_hdr->status = 0;
359f2105c61SSimon Glass pp->cmd_slot->tbl_addr = cpu_to_le32((u32)pp->cmd_tbl & 0xffffffff);
360f2105c61SSimon Glass #ifdef CONFIG_PHYS_64BIT
361f2105c61SSimon Glass pp->cmd_slot->tbl_addr_hi =
362f2105c61SSimon Glass cpu_to_le32((u32)(((pp->cmd_tbl) >> 16) >> 16));
363f2105c61SSimon Glass #endif
364f2105c61SSimon Glass }
365f2105c61SSimon Glass
366f2105c61SSimon Glass #define AHCI_GET_CMD_SLOT(c) ((c) ? ffs(c) : 0)
367f2105c61SSimon Glass
ahci_exec_ata_cmd(struct ahci_uc_priv * uc_priv,u8 port,struct sata_fis_h2d * cfis,u8 * buf,u32 buf_len,s32 is_write)36809bb951bSSimon Glass static int ahci_exec_ata_cmd(struct ahci_uc_priv *uc_priv, u8 port,
36909bb951bSSimon Glass struct sata_fis_h2d *cfis, u8 *buf, u32 buf_len,
37009bb951bSSimon Glass s32 is_write)
371f2105c61SSimon Glass {
3723e59c30fSSimon Glass struct ahci_ioports *pp = &uc_priv->port[port];
3734b640dbcSSimon Glass struct sata_port_regs *port_mmio = pp->port_mmio;
374f2105c61SSimon Glass u32 opts;
375f2105c61SSimon Glass int sg_count = 0, cmd_slot = 0;
376f2105c61SSimon Glass
3773e59c30fSSimon Glass cmd_slot = AHCI_GET_CMD_SLOT(readl(&port_mmio->ci));
378f2105c61SSimon Glass if (32 == cmd_slot) {
379f2105c61SSimon Glass printf("Can't find empty command slot!\n");
380f2105c61SSimon Glass return 0;
381f2105c61SSimon Glass }
382f2105c61SSimon Glass
383f2105c61SSimon Glass /* Check xfer length */
384f2105c61SSimon Glass if (buf_len > MAX_BYTES_PER_TRANS) {
385f2105c61SSimon Glass printf("Max transfer length is %dB\n\r",
386f2105c61SSimon Glass MAX_BYTES_PER_TRANS);
387f2105c61SSimon Glass return 0;
388f2105c61SSimon Glass }
389f2105c61SSimon Glass
390f2105c61SSimon Glass memcpy((u8 *)(pp->cmd_tbl), cfis, sizeof(struct sata_fis_h2d));
391f2105c61SSimon Glass if (buf && buf_len)
39209bb951bSSimon Glass sg_count = ahci_fill_sg(uc_priv, port, buf, buf_len);
393f2105c61SSimon Glass opts = (sizeof(struct sata_fis_h2d) >> 2) | (sg_count << 16);
394f2105c61SSimon Glass if (is_write) {
395f2105c61SSimon Glass opts |= 0x40;
396f2105c61SSimon Glass flush_cache((ulong)buf, buf_len);
397f2105c61SSimon Glass }
398f2105c61SSimon Glass ahci_fill_cmd_slot(pp, cmd_slot, opts);
399f2105c61SSimon Glass
400f2105c61SSimon Glass flush_cache((int)(pp->cmd_slot), AHCI_PORT_PRIV_DMA_SZ);
4013e59c30fSSimon Glass writel_with_flush(1 << cmd_slot, &port_mmio->ci);
402f2105c61SSimon Glass
4033e59c30fSSimon Glass if (waiting_for_cmd_completed((u8 *)&port_mmio->ci, 10000,
4043e59c30fSSimon Glass 0x1 << cmd_slot)) {
405f2105c61SSimon Glass printf("timeout exit!\n");
406f2105c61SSimon Glass return -1;
407f2105c61SSimon Glass }
408f2105c61SSimon Glass invalidate_dcache_range((int)(pp->cmd_slot),
409f2105c61SSimon Glass (int)(pp->cmd_slot)+AHCI_PORT_PRIV_DMA_SZ);
410f2105c61SSimon Glass debug("ahci_exec_ata_cmd: %d byte transferred.\n",
411f2105c61SSimon Glass pp->cmd_slot->status);
412f2105c61SSimon Glass if (!is_write)
413f2105c61SSimon Glass invalidate_dcache_range((ulong)buf, (ulong)buf+buf_len);
414f2105c61SSimon Glass
415f2105c61SSimon Glass return buf_len;
416f2105c61SSimon Glass }
417f2105c61SSimon Glass
ahci_set_feature(struct ahci_uc_priv * uc_priv,u8 port)41847c0f369SSimon Glass static void ahci_set_feature(struct ahci_uc_priv *uc_priv, u8 port)
419f2105c61SSimon Glass {
420f2105c61SSimon Glass struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
421f2105c61SSimon Glass struct sata_fis_h2d *cfis = &h2d;
422f2105c61SSimon Glass
423f2105c61SSimon Glass memset(cfis, 0, sizeof(struct sata_fis_h2d));
424f2105c61SSimon Glass cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
425f2105c61SSimon Glass cfis->pm_port_c = 1 << 7;
426f2105c61SSimon Glass cfis->command = ATA_CMD_SET_FEATURES;
427f2105c61SSimon Glass cfis->features = SETFEATURES_XFER;
42809bb951bSSimon Glass cfis->sector_count = ffs(uc_priv->udma_mask + 1) + 0x3e;
429f2105c61SSimon Glass
43009bb951bSSimon Glass ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, READ_CMD);
431f2105c61SSimon Glass }
432f2105c61SSimon Glass
ahci_port_start(struct ahci_uc_priv * uc_priv,u8 port)43309bb951bSSimon Glass static int ahci_port_start(struct ahci_uc_priv *uc_priv, u8 port)
434f2105c61SSimon Glass {
4353e59c30fSSimon Glass struct ahci_ioports *pp = &uc_priv->port[port];
4364b640dbcSSimon Glass struct sata_port_regs *port_mmio = pp->port_mmio;
437f2105c61SSimon Glass u32 port_status;
438f2105c61SSimon Glass u32 mem;
439f2105c61SSimon Glass int timeout = 10000000;
440f2105c61SSimon Glass
441f2105c61SSimon Glass debug("Enter start port: %d\n", port);
4423e59c30fSSimon Glass port_status = readl(&port_mmio->ssts);
443f2105c61SSimon Glass debug("Port %d status: %x\n", port, port_status);
444f2105c61SSimon Glass if ((port_status & 0xf) != 0x03) {
445f2105c61SSimon Glass printf("No Link on this port!\n");
446f2105c61SSimon Glass return -1;
447f2105c61SSimon Glass }
448f2105c61SSimon Glass
449f2105c61SSimon Glass mem = (u32)malloc(AHCI_PORT_PRIV_DMA_SZ + 1024);
450f2105c61SSimon Glass if (!mem) {
451f2105c61SSimon Glass free(pp);
452f2105c61SSimon Glass printf("No mem for table!\n");
453f2105c61SSimon Glass return -ENOMEM;
454f2105c61SSimon Glass }
455f2105c61SSimon Glass
456f2105c61SSimon Glass mem = (mem + 0x400) & (~0x3ff); /* Aligned to 1024-bytes */
457f2105c61SSimon Glass memset((u8 *)mem, 0, AHCI_PORT_PRIV_DMA_SZ);
458f2105c61SSimon Glass
459f2105c61SSimon Glass /*
460f2105c61SSimon Glass * First item in chunk of DMA memory: 32-slot command table,
461f2105c61SSimon Glass * 32 bytes each in size
462f2105c61SSimon Glass */
463f2105c61SSimon Glass pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
464f2105c61SSimon Glass debug("cmd_slot = 0x%x\n", (unsigned int) pp->cmd_slot);
465f2105c61SSimon Glass mem += (AHCI_CMD_SLOT_SZ * DWC_AHSATA_MAX_CMD_SLOTS);
466f2105c61SSimon Glass
467f2105c61SSimon Glass /*
468f2105c61SSimon Glass * Second item: Received-FIS area, 256-Byte aligned
469f2105c61SSimon Glass */
470f2105c61SSimon Glass pp->rx_fis = mem;
471f2105c61SSimon Glass mem += AHCI_RX_FIS_SZ;
472f2105c61SSimon Glass
473f2105c61SSimon Glass /*
474f2105c61SSimon Glass * Third item: data area for storing a single command
475f2105c61SSimon Glass * and its scatter-gather table
476f2105c61SSimon Glass */
477f2105c61SSimon Glass pp->cmd_tbl = mem;
478f2105c61SSimon Glass debug("cmd_tbl_dma = 0x%lx\n", pp->cmd_tbl);
479f2105c61SSimon Glass
480f2105c61SSimon Glass mem += AHCI_CMD_TBL_HDR;
481f2105c61SSimon Glass
4823e59c30fSSimon Glass writel_with_flush(0x00004444, &port_mmio->dmacr);
483f2105c61SSimon Glass pp->cmd_tbl_sg = (struct ahci_sg *)mem;
4843e59c30fSSimon Glass writel_with_flush((u32)pp->cmd_slot, &port_mmio->clb);
4853e59c30fSSimon Glass writel_with_flush(pp->rx_fis, &port_mmio->fb);
486f2105c61SSimon Glass
487f2105c61SSimon Glass /* Enable FRE */
4883e59c30fSSimon Glass writel_with_flush((SATA_PORT_CMD_FRE | readl(&port_mmio->cmd)),
4893e59c30fSSimon Glass &port_mmio->cmd);
490f2105c61SSimon Glass
491f2105c61SSimon Glass /* Wait device ready */
4923e59c30fSSimon Glass while ((readl(&port_mmio->tfd) & (SATA_PORT_TFD_STS_ERR |
493f2105c61SSimon Glass SATA_PORT_TFD_STS_DRQ | SATA_PORT_TFD_STS_BSY))
494f2105c61SSimon Glass && --timeout)
495f2105c61SSimon Glass ;
496f2105c61SSimon Glass if (timeout <= 0) {
497f2105c61SSimon Glass debug("Device not ready for BSY, DRQ and"
498f2105c61SSimon Glass "ERR in TFD!\n");
499f2105c61SSimon Glass return -1;
500f2105c61SSimon Glass }
501f2105c61SSimon Glass
502f2105c61SSimon Glass writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
503f2105c61SSimon Glass PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
5043e59c30fSSimon Glass PORT_CMD_START, &port_mmio->cmd);
505f2105c61SSimon Glass
506f2105c61SSimon Glass debug("Exit start port %d\n", port);
507f2105c61SSimon Glass
508f2105c61SSimon Glass return 0;
509f2105c61SSimon Glass }
510f2105c61SSimon Glass
dwc_ahsata_print_info(struct blk_desc * pdev)51147c0f369SSimon Glass static void dwc_ahsata_print_info(struct blk_desc *pdev)
512f2105c61SSimon Glass {
513f2105c61SSimon Glass printf("SATA Device Info:\n\r");
514f2105c61SSimon Glass #ifdef CONFIG_SYS_64BIT_LBA
515f2105c61SSimon Glass printf("S/N: %s\n\rProduct model number: %s\n\r"
516f2105c61SSimon Glass "Firmware version: %s\n\rCapacity: %lld sectors\n\r",
517f2105c61SSimon Glass pdev->product, pdev->vendor, pdev->revision, pdev->lba);
518f2105c61SSimon Glass #else
519f2105c61SSimon Glass printf("S/N: %s\n\rProduct model number: %s\n\r"
520f2105c61SSimon Glass "Firmware version: %s\n\rCapacity: %ld sectors\n\r",
521f2105c61SSimon Glass pdev->product, pdev->vendor, pdev->revision, pdev->lba);
522f2105c61SSimon Glass #endif
523f2105c61SSimon Glass }
524f2105c61SSimon Glass
dwc_ahsata_identify(struct ahci_uc_priv * uc_priv,u16 * id)52547c0f369SSimon Glass static void dwc_ahsata_identify(struct ahci_uc_priv *uc_priv, u16 *id)
526f2105c61SSimon Glass {
527f2105c61SSimon Glass struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
528f2105c61SSimon Glass struct sata_fis_h2d *cfis = &h2d;
52909bb951bSSimon Glass u8 port = uc_priv->hard_port_no;
530f2105c61SSimon Glass
531f2105c61SSimon Glass memset(cfis, 0, sizeof(struct sata_fis_h2d));
532f2105c61SSimon Glass
533f2105c61SSimon Glass cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
534f2105c61SSimon Glass cfis->pm_port_c = 0x80; /* is command */
535f2105c61SSimon Glass cfis->command = ATA_CMD_ID_ATA;
536f2105c61SSimon Glass
53709bb951bSSimon Glass ahci_exec_ata_cmd(uc_priv, port, cfis, (u8 *)id, ATA_ID_WORDS * 2,
53809bb951bSSimon Glass READ_CMD);
539f2105c61SSimon Glass ata_swap_buf_le16(id, ATA_ID_WORDS);
540f2105c61SSimon Glass }
541f2105c61SSimon Glass
dwc_ahsata_xfer_mode(struct ahci_uc_priv * uc_priv,u16 * id)54247c0f369SSimon Glass static void dwc_ahsata_xfer_mode(struct ahci_uc_priv *uc_priv, u16 *id)
543f2105c61SSimon Glass {
54409bb951bSSimon Glass uc_priv->pio_mask = id[ATA_ID_PIO_MODES];
54509bb951bSSimon Glass uc_priv->udma_mask = id[ATA_ID_UDMA_MODES];
54609bb951bSSimon Glass debug("pio %04x, udma %04x\n\r", uc_priv->pio_mask, uc_priv->udma_mask);
547f2105c61SSimon Glass }
548f2105c61SSimon Glass
dwc_ahsata_rw_cmd(struct ahci_uc_priv * uc_priv,u32 start,u32 blkcnt,u8 * buffer,int is_write)54947c0f369SSimon Glass static u32 dwc_ahsata_rw_cmd(struct ahci_uc_priv *uc_priv, u32 start,
55047c0f369SSimon Glass u32 blkcnt, u8 *buffer, int is_write)
551f2105c61SSimon Glass {
552f2105c61SSimon Glass struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
553f2105c61SSimon Glass struct sata_fis_h2d *cfis = &h2d;
55409bb951bSSimon Glass u8 port = uc_priv->hard_port_no;
555f2105c61SSimon Glass u32 block;
556f2105c61SSimon Glass
557f2105c61SSimon Glass block = start;
558f2105c61SSimon Glass
559f2105c61SSimon Glass memset(cfis, 0, sizeof(struct sata_fis_h2d));
560f2105c61SSimon Glass
561f2105c61SSimon Glass cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
562f2105c61SSimon Glass cfis->pm_port_c = 0x80; /* is command */
563f2105c61SSimon Glass cfis->command = (is_write) ? ATA_CMD_WRITE : ATA_CMD_READ;
564f2105c61SSimon Glass cfis->device = ATA_LBA;
565f2105c61SSimon Glass
566f2105c61SSimon Glass cfis->device |= (block >> 24) & 0xf;
567f2105c61SSimon Glass cfis->lba_high = (block >> 16) & 0xff;
568f2105c61SSimon Glass cfis->lba_mid = (block >> 8) & 0xff;
569f2105c61SSimon Glass cfis->lba_low = block & 0xff;
570f2105c61SSimon Glass cfis->sector_count = (u8)(blkcnt & 0xff);
571f2105c61SSimon Glass
57209bb951bSSimon Glass if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
57309bb951bSSimon Glass ATA_SECT_SIZE * blkcnt, is_write) > 0)
574f2105c61SSimon Glass return blkcnt;
575f2105c61SSimon Glass else
576f2105c61SSimon Glass return 0;
577f2105c61SSimon Glass }
578f2105c61SSimon Glass
dwc_ahsata_flush_cache(struct ahci_uc_priv * uc_priv)57947c0f369SSimon Glass static void dwc_ahsata_flush_cache(struct ahci_uc_priv *uc_priv)
580f2105c61SSimon Glass {
581f2105c61SSimon Glass struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
582f2105c61SSimon Glass struct sata_fis_h2d *cfis = &h2d;
58309bb951bSSimon Glass u8 port = uc_priv->hard_port_no;
584f2105c61SSimon Glass
585f2105c61SSimon Glass memset(cfis, 0, sizeof(struct sata_fis_h2d));
586f2105c61SSimon Glass
587f2105c61SSimon Glass cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
588f2105c61SSimon Glass cfis->pm_port_c = 0x80; /* is command */
589f2105c61SSimon Glass cfis->command = ATA_CMD_FLUSH;
590f2105c61SSimon Glass
59109bb951bSSimon Glass ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
592f2105c61SSimon Glass }
593f2105c61SSimon Glass
dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv * uc_priv,u32 start,lbaint_t blkcnt,u8 * buffer,int is_write)59447c0f369SSimon Glass static u32 dwc_ahsata_rw_cmd_ext(struct ahci_uc_priv *uc_priv, u32 start,
59547c0f369SSimon Glass lbaint_t blkcnt, u8 *buffer, int is_write)
596f2105c61SSimon Glass {
597f2105c61SSimon Glass struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
598f2105c61SSimon Glass struct sata_fis_h2d *cfis = &h2d;
59909bb951bSSimon Glass u8 port = uc_priv->hard_port_no;
600f2105c61SSimon Glass u64 block;
601f2105c61SSimon Glass
602f2105c61SSimon Glass block = (u64)start;
603f2105c61SSimon Glass
604f2105c61SSimon Glass memset(cfis, 0, sizeof(struct sata_fis_h2d));
605f2105c61SSimon Glass
606f2105c61SSimon Glass cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
607f2105c61SSimon Glass cfis->pm_port_c = 0x80; /* is command */
608f2105c61SSimon Glass
609f2105c61SSimon Glass cfis->command = (is_write) ? ATA_CMD_WRITE_EXT
610f2105c61SSimon Glass : ATA_CMD_READ_EXT;
611f2105c61SSimon Glass
612f2105c61SSimon Glass cfis->lba_high_exp = (block >> 40) & 0xff;
613f2105c61SSimon Glass cfis->lba_mid_exp = (block >> 32) & 0xff;
614f2105c61SSimon Glass cfis->lba_low_exp = (block >> 24) & 0xff;
615f2105c61SSimon Glass cfis->lba_high = (block >> 16) & 0xff;
616f2105c61SSimon Glass cfis->lba_mid = (block >> 8) & 0xff;
617f2105c61SSimon Glass cfis->lba_low = block & 0xff;
618f2105c61SSimon Glass cfis->device = ATA_LBA;
619f2105c61SSimon Glass cfis->sector_count_exp = (blkcnt >> 8) & 0xff;
620f2105c61SSimon Glass cfis->sector_count = blkcnt & 0xff;
621f2105c61SSimon Glass
62209bb951bSSimon Glass if (ahci_exec_ata_cmd(uc_priv, port, cfis, buffer,
623f2105c61SSimon Glass ATA_SECT_SIZE * blkcnt, is_write) > 0)
624f2105c61SSimon Glass return blkcnt;
625f2105c61SSimon Glass else
626f2105c61SSimon Glass return 0;
627f2105c61SSimon Glass }
628f2105c61SSimon Glass
dwc_ahsata_flush_cache_ext(struct ahci_uc_priv * uc_priv)62947c0f369SSimon Glass static void dwc_ahsata_flush_cache_ext(struct ahci_uc_priv *uc_priv)
630f2105c61SSimon Glass {
631f2105c61SSimon Glass struct sata_fis_h2d h2d __aligned(ARCH_DMA_MINALIGN);
632f2105c61SSimon Glass struct sata_fis_h2d *cfis = &h2d;
63309bb951bSSimon Glass u8 port = uc_priv->hard_port_no;
634f2105c61SSimon Glass
635f2105c61SSimon Glass memset(cfis, 0, sizeof(struct sata_fis_h2d));
636f2105c61SSimon Glass
637f2105c61SSimon Glass cfis->fis_type = SATA_FIS_TYPE_REGISTER_H2D;
638f2105c61SSimon Glass cfis->pm_port_c = 0x80; /* is command */
639f2105c61SSimon Glass cfis->command = ATA_CMD_FLUSH_EXT;
640f2105c61SSimon Glass
64109bb951bSSimon Glass ahci_exec_ata_cmd(uc_priv, port, cfis, NULL, 0, 0);
642f2105c61SSimon Glass }
643f2105c61SSimon Glass
dwc_ahsata_init_wcache(struct ahci_uc_priv * uc_priv,u16 * id)64447c0f369SSimon Glass static void dwc_ahsata_init_wcache(struct ahci_uc_priv *uc_priv, u16 *id)
645f2105c61SSimon Glass {
646f2105c61SSimon Glass if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
64709bb951bSSimon Glass uc_priv->flags |= SATA_FLAG_WCACHE;
648f2105c61SSimon Glass if (ata_id_has_flush(id))
64909bb951bSSimon Glass uc_priv->flags |= SATA_FLAG_FLUSH;
650f2105c61SSimon Glass if (ata_id_has_flush_ext(id))
65109bb951bSSimon Glass uc_priv->flags |= SATA_FLAG_FLUSH_EXT;
652f2105c61SSimon Glass }
653f2105c61SSimon Glass
ata_low_level_rw_lba48(struct ahci_uc_priv * uc_priv,u32 blknr,lbaint_t blkcnt,const void * buffer,int is_write)65447c0f369SSimon Glass static u32 ata_low_level_rw_lba48(struct ahci_uc_priv *uc_priv, u32 blknr,
65547c0f369SSimon Glass lbaint_t blkcnt, const void *buffer,
65647c0f369SSimon Glass int is_write)
657f2105c61SSimon Glass {
658f2105c61SSimon Glass u32 start, blks;
659f2105c61SSimon Glass u8 *addr;
660f2105c61SSimon Glass int max_blks;
661f2105c61SSimon Glass
662f2105c61SSimon Glass start = blknr;
663f2105c61SSimon Glass blks = blkcnt;
664f2105c61SSimon Glass addr = (u8 *)buffer;
665f2105c61SSimon Glass
666f2105c61SSimon Glass max_blks = ATA_MAX_SECTORS_LBA48;
667f2105c61SSimon Glass
668f2105c61SSimon Glass do {
669f2105c61SSimon Glass if (blks > max_blks) {
67047c0f369SSimon Glass if (max_blks != dwc_ahsata_rw_cmd_ext(uc_priv, start,
67147c0f369SSimon Glass max_blks, addr,
67247c0f369SSimon Glass is_write))
673f2105c61SSimon Glass return 0;
674f2105c61SSimon Glass start += max_blks;
675f2105c61SSimon Glass blks -= max_blks;
676f2105c61SSimon Glass addr += ATA_SECT_SIZE * max_blks;
677f2105c61SSimon Glass } else {
67847c0f369SSimon Glass if (blks != dwc_ahsata_rw_cmd_ext(uc_priv, start, blks,
67947c0f369SSimon Glass addr, is_write))
680f2105c61SSimon Glass return 0;
681f2105c61SSimon Glass start += blks;
682f2105c61SSimon Glass blks = 0;
683f2105c61SSimon Glass addr += ATA_SECT_SIZE * blks;
684f2105c61SSimon Glass }
685f2105c61SSimon Glass } while (blks != 0);
686f2105c61SSimon Glass
687f2105c61SSimon Glass return blkcnt;
688f2105c61SSimon Glass }
689f2105c61SSimon Glass
ata_low_level_rw_lba28(struct ahci_uc_priv * uc_priv,u32 blknr,lbaint_t blkcnt,const void * buffer,int is_write)69047c0f369SSimon Glass static u32 ata_low_level_rw_lba28(struct ahci_uc_priv *uc_priv, u32 blknr,
69147c0f369SSimon Glass lbaint_t blkcnt, const void *buffer,
69247c0f369SSimon Glass int is_write)
693f2105c61SSimon Glass {
694f2105c61SSimon Glass u32 start, blks;
695f2105c61SSimon Glass u8 *addr;
696f2105c61SSimon Glass int max_blks;
697f2105c61SSimon Glass
698f2105c61SSimon Glass start = blknr;
699f2105c61SSimon Glass blks = blkcnt;
700f2105c61SSimon Glass addr = (u8 *)buffer;
701f2105c61SSimon Glass
702f2105c61SSimon Glass max_blks = ATA_MAX_SECTORS;
703f2105c61SSimon Glass do {
704f2105c61SSimon Glass if (blks > max_blks) {
70547c0f369SSimon Glass if (max_blks != dwc_ahsata_rw_cmd(uc_priv, start,
70647c0f369SSimon Glass max_blks, addr,
70747c0f369SSimon Glass is_write))
708f2105c61SSimon Glass return 0;
709f2105c61SSimon Glass start += max_blks;
710f2105c61SSimon Glass blks -= max_blks;
711f2105c61SSimon Glass addr += ATA_SECT_SIZE * max_blks;
712f2105c61SSimon Glass } else {
71347c0f369SSimon Glass if (blks != dwc_ahsata_rw_cmd(uc_priv, start, blks,
71447c0f369SSimon Glass addr, is_write))
715f2105c61SSimon Glass return 0;
716f2105c61SSimon Glass start += blks;
717f2105c61SSimon Glass blks = 0;
718f2105c61SSimon Glass addr += ATA_SECT_SIZE * blks;
719f2105c61SSimon Glass }
720f2105c61SSimon Glass } while (blks != 0);
721f2105c61SSimon Glass
722f2105c61SSimon Glass return blkcnt;
723f2105c61SSimon Glass }
724f2105c61SSimon Glass
dwc_ahci_start_ports(struct ahci_uc_priv * uc_priv)725752126a0SSimon Glass static int dwc_ahci_start_ports(struct ahci_uc_priv *uc_priv)
726752126a0SSimon Glass {
727752126a0SSimon Glass u32 linkmap;
728752126a0SSimon Glass int i;
729752126a0SSimon Glass
730752126a0SSimon Glass linkmap = uc_priv->link_port_map;
731752126a0SSimon Glass
732752126a0SSimon Glass if (0 == linkmap) {
733752126a0SSimon Glass printf("No port device detected!\n");
734752126a0SSimon Glass return -ENXIO;
735752126a0SSimon Glass }
736752126a0SSimon Glass
737752126a0SSimon Glass for (i = 0; i < uc_priv->n_ports; i++) {
738752126a0SSimon Glass if ((linkmap >> i) && ((linkmap >> i) & 0x01)) {
739752126a0SSimon Glass if (ahci_port_start(uc_priv, (u8)i)) {
740752126a0SSimon Glass printf("Can not start port %d\n", i);
741752126a0SSimon Glass return 1;
742752126a0SSimon Glass }
743752126a0SSimon Glass uc_priv->hard_port_no = i;
744752126a0SSimon Glass break;
745752126a0SSimon Glass }
746752126a0SSimon Glass }
747752126a0SSimon Glass
748752126a0SSimon Glass return 0;
749752126a0SSimon Glass }
750752126a0SSimon Glass
dwc_ahsata_scan_common(struct ahci_uc_priv * uc_priv,struct blk_desc * pdev)751752126a0SSimon Glass static int dwc_ahsata_scan_common(struct ahci_uc_priv *uc_priv,
752752126a0SSimon Glass struct blk_desc *pdev)
753752126a0SSimon Glass {
754752126a0SSimon Glass u8 serial[ATA_ID_SERNO_LEN + 1] = { 0 };
755752126a0SSimon Glass u8 firmware[ATA_ID_FW_REV_LEN + 1] = { 0 };
756752126a0SSimon Glass u8 product[ATA_ID_PROD_LEN + 1] = { 0 };
757752126a0SSimon Glass u64 n_sectors;
758752126a0SSimon Glass u8 port = uc_priv->hard_port_no;
759752126a0SSimon Glass ALLOC_CACHE_ALIGN_BUFFER(u16, id, ATA_ID_WORDS);
760752126a0SSimon Glass
761752126a0SSimon Glass /* Identify device to get information */
762752126a0SSimon Glass dwc_ahsata_identify(uc_priv, id);
763752126a0SSimon Glass
764752126a0SSimon Glass /* Serial number */
765752126a0SSimon Glass ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
766752126a0SSimon Glass memcpy(pdev->product, serial, sizeof(serial));
767752126a0SSimon Glass
768752126a0SSimon Glass /* Firmware version */
769752126a0SSimon Glass ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
770752126a0SSimon Glass memcpy(pdev->revision, firmware, sizeof(firmware));
771752126a0SSimon Glass
772752126a0SSimon Glass /* Product model */
773752126a0SSimon Glass ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
774752126a0SSimon Glass memcpy(pdev->vendor, product, sizeof(product));
775752126a0SSimon Glass
776752126a0SSimon Glass /* Totoal sectors */
777752126a0SSimon Glass n_sectors = ata_id_n_sectors(id);
778752126a0SSimon Glass pdev->lba = (u32)n_sectors;
779752126a0SSimon Glass
780752126a0SSimon Glass pdev->type = DEV_TYPE_HARDDISK;
781752126a0SSimon Glass pdev->blksz = ATA_SECT_SIZE;
782752126a0SSimon Glass pdev->lun = 0;
783752126a0SSimon Glass
784752126a0SSimon Glass /* Check if support LBA48 */
785752126a0SSimon Glass if (ata_id_has_lba48(id)) {
786752126a0SSimon Glass pdev->lba48 = 1;
787752126a0SSimon Glass debug("Device support LBA48\n\r");
788752126a0SSimon Glass }
789752126a0SSimon Glass
790752126a0SSimon Glass /* Get the NCQ queue depth from device */
791752126a0SSimon Glass uc_priv->flags &= (~SATA_FLAG_Q_DEP_MASK);
792752126a0SSimon Glass uc_priv->flags |= ata_id_queue_depth(id);
793752126a0SSimon Glass
794752126a0SSimon Glass /* Get the xfer mode from device */
795752126a0SSimon Glass dwc_ahsata_xfer_mode(uc_priv, id);
796752126a0SSimon Glass
797752126a0SSimon Glass /* Get the write cache status from device */
798752126a0SSimon Glass dwc_ahsata_init_wcache(uc_priv, id);
799752126a0SSimon Glass
800752126a0SSimon Glass /* Set the xfer mode to highest speed */
801752126a0SSimon Glass ahci_set_feature(uc_priv, port);
802752126a0SSimon Glass
803752126a0SSimon Glass dwc_ahsata_print_info(pdev);
804752126a0SSimon Glass
805752126a0SSimon Glass return 0;
806752126a0SSimon Glass }
807752126a0SSimon Glass
808752126a0SSimon Glass /*
809752126a0SSimon Glass * SATA interface between low level driver and command layer
810752126a0SSimon Glass */
sata_read_common(struct ahci_uc_priv * uc_priv,struct blk_desc * desc,ulong blknr,lbaint_t blkcnt,void * buffer)811752126a0SSimon Glass static ulong sata_read_common(struct ahci_uc_priv *uc_priv,
812752126a0SSimon Glass struct blk_desc *desc, ulong blknr,
813752126a0SSimon Glass lbaint_t blkcnt, void *buffer)
814752126a0SSimon Glass {
815752126a0SSimon Glass u32 rc;
816752126a0SSimon Glass
817752126a0SSimon Glass if (desc->lba48)
818752126a0SSimon Glass rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
819752126a0SSimon Glass READ_CMD);
820752126a0SSimon Glass else
821752126a0SSimon Glass rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
822752126a0SSimon Glass READ_CMD);
823752126a0SSimon Glass
824752126a0SSimon Glass return rc;
825752126a0SSimon Glass }
826752126a0SSimon Glass
sata_write_common(struct ahci_uc_priv * uc_priv,struct blk_desc * desc,ulong blknr,lbaint_t blkcnt,const void * buffer)827752126a0SSimon Glass static ulong sata_write_common(struct ahci_uc_priv *uc_priv,
828752126a0SSimon Glass struct blk_desc *desc, ulong blknr,
829752126a0SSimon Glass lbaint_t blkcnt, const void *buffer)
830752126a0SSimon Glass {
831752126a0SSimon Glass u32 rc;
832752126a0SSimon Glass u32 flags = uc_priv->flags;
833752126a0SSimon Glass
834752126a0SSimon Glass if (desc->lba48) {
835752126a0SSimon Glass rc = ata_low_level_rw_lba48(uc_priv, blknr, blkcnt, buffer,
836752126a0SSimon Glass WRITE_CMD);
837752126a0SSimon Glass if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH_EXT))
838752126a0SSimon Glass dwc_ahsata_flush_cache_ext(uc_priv);
839752126a0SSimon Glass } else {
840752126a0SSimon Glass rc = ata_low_level_rw_lba28(uc_priv, blknr, blkcnt, buffer,
841752126a0SSimon Glass WRITE_CMD);
842752126a0SSimon Glass if ((flags & SATA_FLAG_WCACHE) && (flags & SATA_FLAG_FLUSH))
843752126a0SSimon Glass dwc_ahsata_flush_cache(uc_priv);
844752126a0SSimon Glass }
845752126a0SSimon Glass
846752126a0SSimon Glass return rc;
847752126a0SSimon Glass }
848752126a0SSimon Glass
849c893f1e6SSimon Glass #if !CONFIG_IS_ENABLED(AHCI)
ahci_init_one(int pdev)850036a803eSSimon Glass static int ahci_init_one(int pdev)
851036a803eSSimon Glass {
852036a803eSSimon Glass int rc;
853036a803eSSimon Glass struct ahci_uc_priv *uc_priv = NULL;
854036a803eSSimon Glass
855036a803eSSimon Glass uc_priv = malloc(sizeof(struct ahci_uc_priv));
856036a803eSSimon Glass memset(uc_priv, 0, sizeof(struct ahci_uc_priv));
857036a803eSSimon Glass uc_priv->dev = pdev;
858036a803eSSimon Glass
859036a803eSSimon Glass uc_priv->host_flags = ATA_FLAG_SATA
860036a803eSSimon Glass | ATA_FLAG_NO_LEGACY
861036a803eSSimon Glass | ATA_FLAG_MMIO
862036a803eSSimon Glass | ATA_FLAG_PIO_DMA
863036a803eSSimon Glass | ATA_FLAG_NO_ATAPI;
864036a803eSSimon Glass
865036a803eSSimon Glass uc_priv->mmio_base = (void __iomem *)CONFIG_DWC_AHSATA_BASE_ADDR;
866036a803eSSimon Glass
867036a803eSSimon Glass /* initialize adapter */
868036a803eSSimon Glass rc = ahci_host_init(uc_priv);
869036a803eSSimon Glass if (rc)
870036a803eSSimon Glass goto err_out;
871036a803eSSimon Glass
872036a803eSSimon Glass ahci_print_info(uc_priv);
873036a803eSSimon Glass
874036a803eSSimon Glass /* Save the uc_private struct to block device struct */
875036a803eSSimon Glass sata_dev_desc[pdev].priv = uc_priv;
876036a803eSSimon Glass
877036a803eSSimon Glass return 0;
878036a803eSSimon Glass
879036a803eSSimon Glass err_out:
880036a803eSSimon Glass return rc;
881036a803eSSimon Glass }
882036a803eSSimon Glass
init_sata(int dev)883c5273acfSSimon Glass int init_sata(int dev)
884c5273acfSSimon Glass {
88509bb951bSSimon Glass struct ahci_uc_priv *uc_priv = NULL;
886c5273acfSSimon Glass
887c5273acfSSimon Glass #if defined(CONFIG_MX6)
888c5273acfSSimon Glass if (!is_mx6dq() && !is_mx6dqp())
889c5273acfSSimon Glass return 1;
890c5273acfSSimon Glass #endif
891c5273acfSSimon Glass if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
892c5273acfSSimon Glass printf("The sata index %d is out of ranges\n\r", dev);
893c5273acfSSimon Glass return -1;
894c5273acfSSimon Glass }
895c5273acfSSimon Glass
896c5273acfSSimon Glass ahci_init_one(dev);
897c5273acfSSimon Glass
8984b640dbcSSimon Glass uc_priv = sata_dev_desc[dev].priv;
899c5273acfSSimon Glass
900752126a0SSimon Glass return dwc_ahci_start_ports(uc_priv) ? 1 : 0;
901c5273acfSSimon Glass }
902c5273acfSSimon Glass
reset_sata(int dev)903c5273acfSSimon Glass int reset_sata(int dev)
904c5273acfSSimon Glass {
90509bb951bSSimon Glass struct ahci_uc_priv *uc_priv;
906c5273acfSSimon Glass struct sata_host_regs *host_mmio;
907c5273acfSSimon Glass
908c5273acfSSimon Glass if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) {
909c5273acfSSimon Glass printf("The sata index %d is out of ranges\n\r", dev);
910c5273acfSSimon Glass return -1;
911c5273acfSSimon Glass }
912c5273acfSSimon Glass
9134b640dbcSSimon Glass uc_priv = sata_dev_desc[dev].priv;
91409bb951bSSimon Glass if (NULL == uc_priv)
915c5273acfSSimon Glass /* not initialized, so nothing to reset */
916c5273acfSSimon Glass return 0;
917c5273acfSSimon Glass
9184b640dbcSSimon Glass host_mmio = uc_priv->mmio_base;
919c5273acfSSimon Glass setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
920c5273acfSSimon Glass while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
921c5273acfSSimon Glass udelay(100);
922c5273acfSSimon Glass
923c5273acfSSimon Glass return 0;
924c5273acfSSimon Glass }
925c5273acfSSimon Glass
sata_port_status(int dev,int port)926f2105c61SSimon Glass int sata_port_status(int dev, int port)
927f2105c61SSimon Glass {
928f2105c61SSimon Glass struct sata_port_regs *port_mmio;
92909bb951bSSimon Glass struct ahci_uc_priv *uc_priv = NULL;
930f2105c61SSimon Glass
931f2105c61SSimon Glass if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1))
932f2105c61SSimon Glass return -EINVAL;
933f2105c61SSimon Glass
934f2105c61SSimon Glass if (sata_dev_desc[dev].priv == NULL)
935f2105c61SSimon Glass return -ENODEV;
936f2105c61SSimon Glass
9374b640dbcSSimon Glass uc_priv = sata_dev_desc[dev].priv;
9384b640dbcSSimon Glass port_mmio = uc_priv->port[port].port_mmio;
939f2105c61SSimon Glass
9403e59c30fSSimon Glass return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK;
941f2105c61SSimon Glass }
942f2105c61SSimon Glass
943f2105c61SSimon Glass /*
944f2105c61SSimon Glass * SATA interface between low level driver and command layer
945f2105c61SSimon Glass */
sata_read(int dev,ulong blknr,lbaint_t blkcnt,void * buffer)946f2105c61SSimon Glass ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
947f2105c61SSimon Glass {
94847c0f369SSimon Glass struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
949f2105c61SSimon Glass
950752126a0SSimon Glass return sata_read_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
951752126a0SSimon Glass buffer);
952f2105c61SSimon Glass }
953f2105c61SSimon Glass
sata_write(int dev,ulong blknr,lbaint_t blkcnt,const void * buffer)954f2105c61SSimon Glass ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
955f2105c61SSimon Glass {
9564b640dbcSSimon Glass struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
957f2105c61SSimon Glass
958752126a0SSimon Glass return sata_write_common(uc_priv, &sata_dev_desc[dev], blknr, blkcnt,
959752126a0SSimon Glass buffer);
960f2105c61SSimon Glass }
961f2105c61SSimon Glass
scan_sata(int dev)962f2105c61SSimon Glass int scan_sata(int dev)
963f2105c61SSimon Glass {
9644b640dbcSSimon Glass struct ahci_uc_priv *uc_priv = sata_dev_desc[dev].priv;
9653e59c30fSSimon Glass struct blk_desc *pdev = &sata_dev_desc[dev];
966f2105c61SSimon Glass
967752126a0SSimon Glass return dwc_ahsata_scan_common(uc_priv, pdev);
968f2105c61SSimon Glass }
969c893f1e6SSimon Glass #endif /* CONFIG_IS_ENABLED(AHCI) */
970c893f1e6SSimon Glass
971c893f1e6SSimon Glass #if CONFIG_IS_ENABLED(AHCI)
972c893f1e6SSimon Glass
dwc_ahsata_port_status(struct udevice * dev,int port)973c893f1e6SSimon Glass int dwc_ahsata_port_status(struct udevice *dev, int port)
974c893f1e6SSimon Glass {
975c893f1e6SSimon Glass struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
976c893f1e6SSimon Glass struct sata_port_regs *port_mmio;
977c893f1e6SSimon Glass
978c893f1e6SSimon Glass port_mmio = uc_priv->port[port].port_mmio;
979c893f1e6SSimon Glass return readl(&port_mmio->ssts) & SATA_PORT_SSTS_DET_MASK ? 0 : -ENXIO;
980c893f1e6SSimon Glass }
981c893f1e6SSimon Glass
dwc_ahsata_bus_reset(struct udevice * dev)982c893f1e6SSimon Glass int dwc_ahsata_bus_reset(struct udevice *dev)
983c893f1e6SSimon Glass {
984c893f1e6SSimon Glass struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
985c893f1e6SSimon Glass struct sata_host_regs *host_mmio = uc_priv->mmio_base;
986c893f1e6SSimon Glass
987c893f1e6SSimon Glass setbits_le32(&host_mmio->ghc, SATA_HOST_GHC_HR);
988c893f1e6SSimon Glass while (readl(&host_mmio->ghc) & SATA_HOST_GHC_HR)
989c893f1e6SSimon Glass udelay(100);
990c893f1e6SSimon Glass
991c893f1e6SSimon Glass return 0;
992c893f1e6SSimon Glass }
993c893f1e6SSimon Glass
dwc_ahsata_scan(struct udevice * dev)994c893f1e6SSimon Glass int dwc_ahsata_scan(struct udevice *dev)
995c893f1e6SSimon Glass {
996c893f1e6SSimon Glass struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
997c893f1e6SSimon Glass struct blk_desc *desc;
998c893f1e6SSimon Glass struct udevice *blk;
999c893f1e6SSimon Glass int ret;
1000c893f1e6SSimon Glass
1001c893f1e6SSimon Glass /*
1002c893f1e6SSimon Glass * Create only one block device and do detection
1003c893f1e6SSimon Glass * to make sure that there won't be a lot of
1004c893f1e6SSimon Glass * block devices created
1005c893f1e6SSimon Glass */
1006c893f1e6SSimon Glass device_find_first_child(dev, &blk);
1007c893f1e6SSimon Glass if (!blk) {
1008c893f1e6SSimon Glass ret = blk_create_devicef(dev, "dwc_ahsata_blk", "blk",
1009c893f1e6SSimon Glass IF_TYPE_SATA, -1, 512, 0, &blk);
1010c893f1e6SSimon Glass if (ret) {
1011c893f1e6SSimon Glass debug("Can't create device\n");
1012c893f1e6SSimon Glass return ret;
1013c893f1e6SSimon Glass }
1014c893f1e6SSimon Glass }
1015c893f1e6SSimon Glass
1016c893f1e6SSimon Glass desc = dev_get_uclass_platdata(blk);
1017c893f1e6SSimon Glass ret = dwc_ahsata_scan_common(uc_priv, desc);
1018c893f1e6SSimon Glass if (ret) {
1019c893f1e6SSimon Glass debug("%s: Failed to scan bus\n", __func__);
1020c893f1e6SSimon Glass return ret;
1021c893f1e6SSimon Glass }
1022c893f1e6SSimon Glass
1023c893f1e6SSimon Glass return 0;
1024c893f1e6SSimon Glass }
1025c893f1e6SSimon Glass
dwc_ahsata_probe(struct udevice * dev)1026c893f1e6SSimon Glass int dwc_ahsata_probe(struct udevice *dev)
1027c893f1e6SSimon Glass {
1028c893f1e6SSimon Glass struct ahci_uc_priv *uc_priv = dev_get_uclass_priv(dev);
1029c893f1e6SSimon Glass int ret;
1030c893f1e6SSimon Glass
1031c893f1e6SSimon Glass uc_priv->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
1032c893f1e6SSimon Glass ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | ATA_FLAG_NO_ATAPI;
1033c893f1e6SSimon Glass uc_priv->mmio_base = (void __iomem *)dev_read_addr(dev);
1034c893f1e6SSimon Glass
1035c893f1e6SSimon Glass /* initialize adapter */
1036c893f1e6SSimon Glass ret = ahci_host_init(uc_priv);
1037c893f1e6SSimon Glass if (ret)
1038c893f1e6SSimon Glass return ret;
1039c893f1e6SSimon Glass
1040c893f1e6SSimon Glass ahci_print_info(uc_priv);
1041c893f1e6SSimon Glass
1042c893f1e6SSimon Glass return dwc_ahci_start_ports(uc_priv);
1043c893f1e6SSimon Glass }
1044c893f1e6SSimon Glass
dwc_ahsata_read(struct udevice * blk,lbaint_t blknr,lbaint_t blkcnt,void * buffer)1045c893f1e6SSimon Glass static ulong dwc_ahsata_read(struct udevice *blk, lbaint_t blknr,
1046c893f1e6SSimon Glass lbaint_t blkcnt, void *buffer)
1047c893f1e6SSimon Glass {
1048c893f1e6SSimon Glass struct blk_desc *desc = dev_get_uclass_platdata(blk);
1049c893f1e6SSimon Glass struct udevice *dev = dev_get_parent(blk);
1050c893f1e6SSimon Glass struct ahci_uc_priv *uc_priv;
1051c893f1e6SSimon Glass
1052c893f1e6SSimon Glass uc_priv = dev_get_uclass_priv(dev);
1053c893f1e6SSimon Glass return sata_read_common(uc_priv, desc, blknr, blkcnt, buffer);
1054c893f1e6SSimon Glass }
1055c893f1e6SSimon Glass
dwc_ahsata_write(struct udevice * blk,lbaint_t blknr,lbaint_t blkcnt,const void * buffer)1056c893f1e6SSimon Glass static ulong dwc_ahsata_write(struct udevice *blk, lbaint_t blknr,
1057c893f1e6SSimon Glass lbaint_t blkcnt, const void *buffer)
1058c893f1e6SSimon Glass {
1059c893f1e6SSimon Glass struct blk_desc *desc = dev_get_uclass_platdata(blk);
1060c893f1e6SSimon Glass struct udevice *dev = dev_get_parent(blk);
1061c893f1e6SSimon Glass struct ahci_uc_priv *uc_priv;
1062c893f1e6SSimon Glass
1063c893f1e6SSimon Glass uc_priv = dev_get_uclass_priv(dev);
1064c893f1e6SSimon Glass return sata_write_common(uc_priv, desc, blknr, blkcnt, buffer);
1065c893f1e6SSimon Glass }
1066c893f1e6SSimon Glass
1067c893f1e6SSimon Glass static const struct blk_ops dwc_ahsata_blk_ops = {
1068c893f1e6SSimon Glass .read = dwc_ahsata_read,
1069c893f1e6SSimon Glass .write = dwc_ahsata_write,
1070c893f1e6SSimon Glass };
1071c893f1e6SSimon Glass
1072c893f1e6SSimon Glass U_BOOT_DRIVER(dwc_ahsata_blk) = {
1073c893f1e6SSimon Glass .name = "dwc_ahsata_blk",
1074c893f1e6SSimon Glass .id = UCLASS_BLK,
1075c893f1e6SSimon Glass .ops = &dwc_ahsata_blk_ops,
1076c893f1e6SSimon Glass };
1077c893f1e6SSimon Glass
1078c893f1e6SSimon Glass #endif
1079